2 * PowerPC64 port by Mike Corrigan and Dave Engebretsen
3 * {mikejc|engebret}@us.ibm.com
5 * Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com>
7 * SMP scalability work:
8 * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
13 * PowerPC Hashed Page Table functions
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
24 #include <linux/spinlock.h>
25 #include <linux/errno.h>
26 #include <linux/sched.h>
27 #include <linux/proc_fs.h>
28 #include <linux/stat.h>
29 #include <linux/sysctl.h>
30 #include <linux/export.h>
31 #include <linux/ctype.h>
32 #include <linux/cache.h>
33 #include <linux/init.h>
34 #include <linux/signal.h>
35 #include <linux/memblock.h>
36 #include <linux/context_tracking.h>
37 #include <linux/libfdt.h>
39 #include <asm/processor.h>
40 #include <asm/pgtable.h>
42 #include <asm/mmu_context.h>
44 #include <asm/types.h>
45 #include <asm/uaccess.h>
46 #include <asm/machdep.h>
48 #include <asm/tlbflush.h>
52 #include <asm/cacheflush.h>
53 #include <asm/cputable.h>
54 #include <asm/sections.h>
55 #include <asm/copro.h>
57 #include <asm/code-patching.h>
58 #include <asm/fadump.h>
59 #include <asm/firmware.h>
61 #include <asm/trace.h>
65 #define DBG(fmt...) udbg_printf(fmt)
71 #define DBG_LOW(fmt...) udbg_printf(fmt)
73 #define DBG_LOW(fmt...)
81 * Note: pte --> Linux PTE
82 * HPTE --> PowerPC Hashed Page Table Entry
85 * htab_initialize is called with the MMU off (of course), but
86 * the kernel has been copied down to zero so it can directly
87 * reference global data. At this point it is very difficult
88 * to print debug info.
92 static unsigned long _SDR1
;
93 struct mmu_psize_def mmu_psize_defs
[MMU_PAGE_COUNT
];
94 EXPORT_SYMBOL_GPL(mmu_psize_defs
);
96 struct hash_pte
*htab_address
;
97 unsigned long htab_size_bytes
;
98 unsigned long htab_hash_mask
;
99 EXPORT_SYMBOL_GPL(htab_hash_mask
);
100 int mmu_linear_psize
= MMU_PAGE_4K
;
101 EXPORT_SYMBOL_GPL(mmu_linear_psize
);
102 int mmu_virtual_psize
= MMU_PAGE_4K
;
103 int mmu_vmalloc_psize
= MMU_PAGE_4K
;
104 #ifdef CONFIG_SPARSEMEM_VMEMMAP
105 int mmu_vmemmap_psize
= MMU_PAGE_4K
;
107 int mmu_io_psize
= MMU_PAGE_4K
;
108 int mmu_kernel_ssize
= MMU_SEGSIZE_256M
;
109 EXPORT_SYMBOL_GPL(mmu_kernel_ssize
);
110 int mmu_highuser_ssize
= MMU_SEGSIZE_256M
;
111 u16 mmu_slb_size
= 64;
112 EXPORT_SYMBOL_GPL(mmu_slb_size
);
113 #ifdef CONFIG_PPC_64K_PAGES
114 int mmu_ci_restrictions
;
116 #ifdef CONFIG_DEBUG_PAGEALLOC
117 static u8
*linear_map_hash_slots
;
118 static unsigned long linear_map_hash_count
;
119 static DEFINE_SPINLOCK(linear_map_hash_lock
);
120 #endif /* CONFIG_DEBUG_PAGEALLOC */
121 struct mmu_hash_ops mmu_hash_ops
;
122 EXPORT_SYMBOL(mmu_hash_ops
);
124 /* There are definitions of page sizes arrays to be used when none
125 * is provided by the firmware.
128 /* Pre-POWER4 CPUs (4k pages only)
130 static struct mmu_psize_def mmu_psize_defaults_old
[] = {
134 .penc
= {[MMU_PAGE_4K
] = 0, [1 ... MMU_PAGE_COUNT
- 1] = -1},
140 /* POWER4, GPUL, POWER5
142 * Support for 16Mb large pages
144 static struct mmu_psize_def mmu_psize_defaults_gp
[] = {
148 .penc
= {[MMU_PAGE_4K
] = 0, [1 ... MMU_PAGE_COUNT
- 1] = -1},
155 .penc
= {[0 ... MMU_PAGE_16M
- 1] = -1, [MMU_PAGE_16M
] = 0,
156 [MMU_PAGE_16M
+ 1 ... MMU_PAGE_COUNT
- 1] = -1 },
163 * 'R' and 'C' update notes:
164 * - Under pHyp or KVM, the updatepp path will not set C, thus it *will*
165 * create writeable HPTEs without C set, because the hcall H_PROTECT
166 * that we use in that case will not update C
167 * - The above is however not a problem, because we also don't do that
168 * fancy "no flush" variant of eviction and we use H_REMOVE which will
169 * do the right thing and thus we don't have the race I described earlier
171 * - Under bare metal, we do have the race, so we need R and C set
172 * - We make sure R is always set and never lost
173 * - C is _PAGE_DIRTY, and *should* always be set for a writeable mapping
175 unsigned long htab_convert_pte_flags(unsigned long pteflags
)
177 unsigned long rflags
= 0;
179 /* _PAGE_EXEC -> NOEXEC */
180 if ((pteflags
& _PAGE_EXEC
) == 0)
184 * Linux uses slb key 0 for kernel and 1 for user.
185 * kernel RW areas are mapped with PPP=0b000
186 * User area is mapped with PPP=0b010 for read/write
187 * or PPP=0b011 for read-only (including writeable but clean pages).
189 if (pteflags
& _PAGE_PRIVILEGED
) {
191 * Kernel read only mapped with ppp bits 0b110
193 if (!(pteflags
& _PAGE_WRITE
))
194 rflags
|= (HPTE_R_PP0
| 0x2);
196 if (pteflags
& _PAGE_RWX
)
198 if (!((pteflags
& _PAGE_WRITE
) && (pteflags
& _PAGE_DIRTY
)))
202 * We can't allow hardware to update hpte bits. Hence always
203 * set 'R' bit and set 'C' if it is a write fault
207 if (pteflags
& _PAGE_DIRTY
)
213 if ((pteflags
& _PAGE_CACHE_CTL
) == _PAGE_TOLERANT
)
215 else if ((pteflags
& _PAGE_CACHE_CTL
) == _PAGE_NON_IDEMPOTENT
)
216 rflags
|= (HPTE_R_I
| HPTE_R_G
);
217 else if ((pteflags
& _PAGE_CACHE_CTL
) == _PAGE_SAO
)
218 rflags
|= (HPTE_R_W
| HPTE_R_I
| HPTE_R_M
);
221 * Add memory coherence if cache inhibited is not set
228 int htab_bolt_mapping(unsigned long vstart
, unsigned long vend
,
229 unsigned long pstart
, unsigned long prot
,
230 int psize
, int ssize
)
232 unsigned long vaddr
, paddr
;
233 unsigned int step
, shift
;
236 shift
= mmu_psize_defs
[psize
].shift
;
239 prot
= htab_convert_pte_flags(prot
);
241 DBG("htab_bolt_mapping(%lx..%lx -> %lx (%lx,%d,%d)\n",
242 vstart
, vend
, pstart
, prot
, psize
, ssize
);
244 for (vaddr
= vstart
, paddr
= pstart
; vaddr
< vend
;
245 vaddr
+= step
, paddr
+= step
) {
246 unsigned long hash
, hpteg
;
247 unsigned long vsid
= get_kernel_vsid(vaddr
, ssize
);
248 unsigned long vpn
= hpt_vpn(vaddr
, vsid
, ssize
);
249 unsigned long tprot
= prot
;
252 * If we hit a bad address return error.
256 /* Make kernel text executable */
257 if (overlaps_kernel_text(vaddr
, vaddr
+ step
))
260 /* Make kvm guest trampolines executable */
261 if (overlaps_kvm_tmp(vaddr
, vaddr
+ step
))
265 * If relocatable, check if it overlaps interrupt vectors that
266 * are copied down to real 0. For relocatable kernel
267 * (e.g. kdump case) we copy interrupt vectors down to real
268 * address 0. Mark that region as executable. This is
269 * because on p8 system with relocation on exception feature
270 * enabled, exceptions are raised with MMU (IR=DR=1) ON. Hence
271 * in order to execute the interrupt handlers in virtual
272 * mode the vector region need to be marked as executable.
274 if ((PHYSICAL_START
> MEMORY_START
) &&
275 overlaps_interrupt_vector_text(vaddr
, vaddr
+ step
))
278 hash
= hpt_hash(vpn
, shift
, ssize
);
279 hpteg
= ((hash
& htab_hash_mask
) * HPTES_PER_GROUP
);
281 BUG_ON(!mmu_hash_ops
.hpte_insert
);
282 ret
= mmu_hash_ops
.hpte_insert(hpteg
, vpn
, paddr
, tprot
,
283 HPTE_V_BOLTED
, psize
, psize
,
289 #ifdef CONFIG_DEBUG_PAGEALLOC
290 if (debug_pagealloc_enabled() &&
291 (paddr
>> PAGE_SHIFT
) < linear_map_hash_count
)
292 linear_map_hash_slots
[paddr
>> PAGE_SHIFT
] = ret
| 0x80;
293 #endif /* CONFIG_DEBUG_PAGEALLOC */
295 return ret
< 0 ? ret
: 0;
298 int htab_remove_mapping(unsigned long vstart
, unsigned long vend
,
299 int psize
, int ssize
)
302 unsigned int step
, shift
;
306 shift
= mmu_psize_defs
[psize
].shift
;
309 if (!mmu_hash_ops
.hpte_removebolted
)
312 for (vaddr
= vstart
; vaddr
< vend
; vaddr
+= step
) {
313 rc
= mmu_hash_ops
.hpte_removebolted(vaddr
, psize
, ssize
);
325 static bool disable_1tb_segments
= false;
327 static int __init
parse_disable_1tb_segments(char *p
)
329 disable_1tb_segments
= true;
332 early_param("disable_1tb_segments", parse_disable_1tb_segments
);
334 static int __init
htab_dt_scan_seg_sizes(unsigned long node
,
335 const char *uname
, int depth
,
338 const char *type
= of_get_flat_dt_prop(node
, "device_type", NULL
);
342 /* We are scanning "cpu" nodes only */
343 if (type
== NULL
|| strcmp(type
, "cpu") != 0)
346 prop
= of_get_flat_dt_prop(node
, "ibm,processor-segment-sizes", &size
);
349 for (; size
>= 4; size
-= 4, ++prop
) {
350 if (be32_to_cpu(prop
[0]) == 40) {
351 DBG("1T segment support detected\n");
353 if (disable_1tb_segments
) {
354 DBG("1T segments disabled by command line\n");
358 cur_cpu_spec
->mmu_features
|= MMU_FTR_1T_SEGMENT
;
362 cur_cpu_spec
->mmu_features
&= ~MMU_FTR_NO_SLBIE_B
;
366 static void __init
htab_init_seg_sizes(void)
368 of_scan_flat_dt(htab_dt_scan_seg_sizes
, NULL
);
371 static int __init
get_idx_from_shift(unsigned int shift
)
395 static int __init
htab_dt_scan_page_sizes(unsigned long node
,
396 const char *uname
, int depth
,
399 const char *type
= of_get_flat_dt_prop(node
, "device_type", NULL
);
403 /* We are scanning "cpu" nodes only */
404 if (type
== NULL
|| strcmp(type
, "cpu") != 0)
407 prop
= of_get_flat_dt_prop(node
, "ibm,segment-page-sizes", &size
);
411 pr_info("Page sizes from device-tree:\n");
413 cur_cpu_spec
->mmu_features
&= ~(MMU_FTR_16M_PAGE
);
415 unsigned int base_shift
= be32_to_cpu(prop
[0]);
416 unsigned int slbenc
= be32_to_cpu(prop
[1]);
417 unsigned int lpnum
= be32_to_cpu(prop
[2]);
418 struct mmu_psize_def
*def
;
421 size
-= 3; prop
+= 3;
422 base_idx
= get_idx_from_shift(base_shift
);
424 /* skip the pte encoding also */
425 prop
+= lpnum
* 2; size
-= lpnum
* 2;
428 def
= &mmu_psize_defs
[base_idx
];
429 if (base_idx
== MMU_PAGE_16M
)
430 cur_cpu_spec
->mmu_features
|= MMU_FTR_16M_PAGE
;
432 def
->shift
= base_shift
;
433 if (base_shift
<= 23)
436 def
->avpnm
= (1 << (base_shift
- 23)) - 1;
439 * We don't know for sure what's up with tlbiel, so
440 * for now we only set it for 4K and 64K pages
442 if (base_idx
== MMU_PAGE_4K
|| base_idx
== MMU_PAGE_64K
)
447 while (size
> 0 && lpnum
) {
448 unsigned int shift
= be32_to_cpu(prop
[0]);
449 int penc
= be32_to_cpu(prop
[1]);
451 prop
+= 2; size
-= 2;
454 idx
= get_idx_from_shift(shift
);
459 pr_err("Invalid penc for base_shift=%d "
460 "shift=%d\n", base_shift
, shift
);
462 def
->penc
[idx
] = penc
;
463 pr_info("base_shift=%d: shift=%d, sllp=0x%04lx,"
464 " avpnm=0x%08lx, tlbiel=%d, penc=%d\n",
465 base_shift
, shift
, def
->sllp
,
466 def
->avpnm
, def
->tlbiel
, def
->penc
[idx
]);
473 #ifdef CONFIG_HUGETLB_PAGE
474 /* Scan for 16G memory blocks that have been set aside for huge pages
475 * and reserve those blocks for 16G huge pages.
477 static int __init
htab_dt_scan_hugepage_blocks(unsigned long node
,
478 const char *uname
, int depth
,
480 const char *type
= of_get_flat_dt_prop(node
, "device_type", NULL
);
481 const __be64
*addr_prop
;
482 const __be32
*page_count_prop
;
483 unsigned int expected_pages
;
484 long unsigned int phys_addr
;
485 long unsigned int block_size
;
487 /* We are scanning "memory" nodes only */
488 if (type
== NULL
|| strcmp(type
, "memory") != 0)
491 /* This property is the log base 2 of the number of virtual pages that
492 * will represent this memory block. */
493 page_count_prop
= of_get_flat_dt_prop(node
, "ibm,expected#pages", NULL
);
494 if (page_count_prop
== NULL
)
496 expected_pages
= (1 << be32_to_cpu(page_count_prop
[0]));
497 addr_prop
= of_get_flat_dt_prop(node
, "reg", NULL
);
498 if (addr_prop
== NULL
)
500 phys_addr
= be64_to_cpu(addr_prop
[0]);
501 block_size
= be64_to_cpu(addr_prop
[1]);
502 if (block_size
!= (16 * GB
))
504 printk(KERN_INFO
"Huge page(16GB) memory: "
505 "addr = 0x%lX size = 0x%lX pages = %d\n",
506 phys_addr
, block_size
, expected_pages
);
507 if (phys_addr
+ (16 * GB
) <= memblock_end_of_DRAM()) {
508 memblock_reserve(phys_addr
, block_size
* expected_pages
);
509 add_gpage(phys_addr
, block_size
, expected_pages
);
513 #endif /* CONFIG_HUGETLB_PAGE */
515 static void mmu_psize_set_default_penc(void)
518 for (bpsize
= 0; bpsize
< MMU_PAGE_COUNT
; bpsize
++)
519 for (apsize
= 0; apsize
< MMU_PAGE_COUNT
; apsize
++)
520 mmu_psize_defs
[bpsize
].penc
[apsize
] = -1;
523 #ifdef CONFIG_PPC_64K_PAGES
525 static bool might_have_hea(void)
528 * The HEA ethernet adapter requires awareness of the
529 * GX bus. Without that awareness we can easily assume
530 * we will never see an HEA ethernet device.
532 #ifdef CONFIG_IBMEBUS
533 return !cpu_has_feature(CPU_FTR_ARCH_207S
) &&
534 !firmware_has_feature(FW_FEATURE_SPLPAR
);
540 #endif /* #ifdef CONFIG_PPC_64K_PAGES */
542 static void __init
htab_init_page_sizes(void)
546 /* se the invalid penc to -1 */
547 mmu_psize_set_default_penc();
549 /* Default to 4K pages only */
550 memcpy(mmu_psize_defs
, mmu_psize_defaults_old
,
551 sizeof(mmu_psize_defaults_old
));
554 * Try to find the available page sizes in the device-tree
556 rc
= of_scan_flat_dt(htab_dt_scan_page_sizes
, NULL
);
557 if (rc
!= 0) /* Found */
561 * Not in the device-tree, let's fallback on known size
562 * list for 16M capable GP & GR
564 if (mmu_has_feature(MMU_FTR_16M_PAGE
))
565 memcpy(mmu_psize_defs
, mmu_psize_defaults_gp
,
566 sizeof(mmu_psize_defaults_gp
));
568 if (!debug_pagealloc_enabled()) {
570 * Pick a size for the linear mapping. Currently, we only
571 * support 16M, 1M and 4K which is the default
573 if (mmu_psize_defs
[MMU_PAGE_16M
].shift
)
574 mmu_linear_psize
= MMU_PAGE_16M
;
575 else if (mmu_psize_defs
[MMU_PAGE_1M
].shift
)
576 mmu_linear_psize
= MMU_PAGE_1M
;
579 #ifdef CONFIG_PPC_64K_PAGES
581 * Pick a size for the ordinary pages. Default is 4K, we support
582 * 64K for user mappings and vmalloc if supported by the processor.
583 * We only use 64k for ioremap if the processor
584 * (and firmware) support cache-inhibited large pages.
585 * If not, we use 4k and set mmu_ci_restrictions so that
586 * hash_page knows to switch processes that use cache-inhibited
587 * mappings to 4k pages.
589 if (mmu_psize_defs
[MMU_PAGE_64K
].shift
) {
590 mmu_virtual_psize
= MMU_PAGE_64K
;
591 mmu_vmalloc_psize
= MMU_PAGE_64K
;
592 if (mmu_linear_psize
== MMU_PAGE_4K
)
593 mmu_linear_psize
= MMU_PAGE_64K
;
594 if (mmu_has_feature(MMU_FTR_CI_LARGE_PAGE
)) {
596 * When running on pSeries using 64k pages for ioremap
597 * would stop us accessing the HEA ethernet. So if we
598 * have the chance of ever seeing one, stay at 4k.
600 if (!might_have_hea())
601 mmu_io_psize
= MMU_PAGE_64K
;
603 mmu_ci_restrictions
= 1;
605 #endif /* CONFIG_PPC_64K_PAGES */
607 #ifdef CONFIG_SPARSEMEM_VMEMMAP
608 /* We try to use 16M pages for vmemmap if that is supported
609 * and we have at least 1G of RAM at boot
611 if (mmu_psize_defs
[MMU_PAGE_16M
].shift
&&
612 memblock_phys_mem_size() >= 0x40000000)
613 mmu_vmemmap_psize
= MMU_PAGE_16M
;
614 else if (mmu_psize_defs
[MMU_PAGE_64K
].shift
)
615 mmu_vmemmap_psize
= MMU_PAGE_64K
;
617 mmu_vmemmap_psize
= MMU_PAGE_4K
;
618 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
620 printk(KERN_DEBUG
"Page orders: linear mapping = %d, "
621 "virtual = %d, io = %d"
622 #ifdef CONFIG_SPARSEMEM_VMEMMAP
626 mmu_psize_defs
[mmu_linear_psize
].shift
,
627 mmu_psize_defs
[mmu_virtual_psize
].shift
,
628 mmu_psize_defs
[mmu_io_psize
].shift
629 #ifdef CONFIG_SPARSEMEM_VMEMMAP
630 ,mmu_psize_defs
[mmu_vmemmap_psize
].shift
634 #ifdef CONFIG_HUGETLB_PAGE
635 /* Reserve 16G huge page memory sections for huge pages */
636 of_scan_flat_dt(htab_dt_scan_hugepage_blocks
, NULL
);
637 #endif /* CONFIG_HUGETLB_PAGE */
640 static int __init
htab_dt_scan_pftsize(unsigned long node
,
641 const char *uname
, int depth
,
644 const char *type
= of_get_flat_dt_prop(node
, "device_type", NULL
);
647 /* We are scanning "cpu" nodes only */
648 if (type
== NULL
|| strcmp(type
, "cpu") != 0)
651 prop
= of_get_flat_dt_prop(node
, "ibm,pft-size", NULL
);
653 /* pft_size[0] is the NUMA CEC cookie */
654 ppc64_pft_size
= be32_to_cpu(prop
[1]);
660 unsigned htab_shift_for_mem_size(unsigned long mem_size
)
662 unsigned memshift
= __ilog2(mem_size
);
663 unsigned pshift
= mmu_psize_defs
[mmu_virtual_psize
].shift
;
666 /* round mem_size up to next power of 2 */
667 if ((1UL << memshift
) < mem_size
)
670 /* aim for 2 pages / pteg */
671 pteg_shift
= memshift
- (pshift
+ 1);
674 * 2^11 PTEGS of 128 bytes each, ie. 2^18 bytes is the minimum htab
675 * size permitted by the architecture.
677 return max(pteg_shift
+ 7, 18U);
680 static unsigned long __init
htab_get_table_size(void)
682 /* If hash size isn't already provided by the platform, we try to
683 * retrieve it from the device-tree. If it's not there neither, we
684 * calculate it now based on the total RAM size
686 if (ppc64_pft_size
== 0)
687 of_scan_flat_dt(htab_dt_scan_pftsize
, NULL
);
689 return 1UL << ppc64_pft_size
;
691 return 1UL << htab_shift_for_mem_size(memblock_phys_mem_size());
694 #ifdef CONFIG_MEMORY_HOTPLUG
695 int create_section_mapping(unsigned long start
, unsigned long end
)
697 int rc
= htab_bolt_mapping(start
, end
, __pa(start
),
698 pgprot_val(PAGE_KERNEL
), mmu_linear_psize
,
702 int rc2
= htab_remove_mapping(start
, end
, mmu_linear_psize
,
704 BUG_ON(rc2
&& (rc2
!= -ENOENT
));
709 int remove_section_mapping(unsigned long start
, unsigned long end
)
711 int rc
= htab_remove_mapping(start
, end
, mmu_linear_psize
,
716 #endif /* CONFIG_MEMORY_HOTPLUG */
718 static void __init
hash_init_partition_table(phys_addr_t hash_table
,
719 unsigned long htab_size
)
721 unsigned long ps_field
;
722 unsigned long patb_size
= 1UL << PATB_SIZE_SHIFT
;
725 * slb llp encoding for the page size used in VPM real mode.
726 * We can ignore that for lpid 0
729 htab_size
= __ilog2(htab_size
) - 18;
731 BUILD_BUG_ON_MSG((PATB_SIZE_SHIFT
> 24), "Partition table size too large.");
732 partition_tb
= __va(memblock_alloc_base(patb_size
, patb_size
,
733 MEMBLOCK_ALLOC_ANYWHERE
));
735 /* Initialize the Partition Table with no entries */
736 memset((void *)partition_tb
, 0, patb_size
);
737 partition_tb
->patb0
= cpu_to_be64(ps_field
| hash_table
| htab_size
);
739 * FIXME!! This should be done via update_partition table
740 * For now UPRT is 0 for us.
742 partition_tb
->patb1
= 0;
743 pr_info("Partition table %p\n", partition_tb
);
745 * update partition table control register,
748 mtspr(SPRN_PTCR
, __pa(partition_tb
) | (PATB_SIZE_SHIFT
- 12));
752 static void __init
htab_initialize(void)
755 unsigned long pteg_count
;
757 unsigned long base
= 0, size
= 0;
758 struct memblock_region
*reg
;
760 DBG(" -> htab_initialize()\n");
762 /* Initialize segment sizes */
763 htab_init_seg_sizes();
765 /* Initialize page sizes */
766 htab_init_page_sizes();
768 if (mmu_has_feature(MMU_FTR_1T_SEGMENT
)) {
769 mmu_kernel_ssize
= MMU_SEGSIZE_1T
;
770 mmu_highuser_ssize
= MMU_SEGSIZE_1T
;
771 printk(KERN_INFO
"Using 1TB segments\n");
775 * Calculate the required size of the htab. We want the number of
776 * PTEGs to equal one half the number of real pages.
778 htab_size_bytes
= htab_get_table_size();
779 pteg_count
= htab_size_bytes
>> 7;
781 htab_hash_mask
= pteg_count
- 1;
783 if (firmware_has_feature(FW_FEATURE_LPAR
) ||
784 firmware_has_feature(FW_FEATURE_PS3_LV1
)) {
785 /* Using a hypervisor which owns the htab */
788 #ifdef CONFIG_FA_DUMP
790 * If firmware assisted dump is active firmware preserves
791 * the contents of htab along with entire partition memory.
792 * Clear the htab if firmware assisted dump is active so
793 * that we dont end up using old mappings.
795 if (is_fadump_active() && mmu_hash_ops
.hpte_clear_all
)
796 mmu_hash_ops
.hpte_clear_all();
799 unsigned long limit
= MEMBLOCK_ALLOC_ANYWHERE
;
801 #ifdef CONFIG_PPC_CELL
803 * Cell may require the hash table down low when using the
804 * Axon IOMMU in order to fit the dynamic region over it, see
805 * comments in cell/iommu.c
807 if (fdt_subnode_offset(initial_boot_params
, 0, "axon") > 0) {
809 pr_info("Hash table forced below 2G for Axon IOMMU\n");
811 #endif /* CONFIG_PPC_CELL */
813 table
= memblock_alloc_base(htab_size_bytes
, htab_size_bytes
,
816 DBG("Hash table allocated at %lx, size: %lx\n", table
,
819 htab_address
= __va(table
);
821 /* htab absolute addr + encoded htabsize */
822 _SDR1
= table
+ __ilog2(htab_size_bytes
) - 18;
824 /* Initialize the HPT with no entries */
825 memset((void *)table
, 0, htab_size_bytes
);
827 if (!cpu_has_feature(CPU_FTR_ARCH_300
))
829 mtspr(SPRN_SDR1
, _SDR1
);
831 hash_init_partition_table(table
, htab_size_bytes
);
834 prot
= pgprot_val(PAGE_KERNEL
);
836 #ifdef CONFIG_DEBUG_PAGEALLOC
837 if (debug_pagealloc_enabled()) {
838 linear_map_hash_count
= memblock_end_of_DRAM() >> PAGE_SHIFT
;
839 linear_map_hash_slots
= __va(memblock_alloc_base(
840 linear_map_hash_count
, 1, ppc64_rma_size
));
841 memset(linear_map_hash_slots
, 0, linear_map_hash_count
);
843 #endif /* CONFIG_DEBUG_PAGEALLOC */
845 /* On U3 based machines, we need to reserve the DART area and
846 * _NOT_ map it to avoid cache paradoxes as it's remapped non
850 /* create bolted the linear mapping in the hash table */
851 for_each_memblock(memory
, reg
) {
852 base
= (unsigned long)__va(reg
->base
);
855 DBG("creating mapping for region: %lx..%lx (prot: %lx)\n",
858 BUG_ON(htab_bolt_mapping(base
, base
+ size
, __pa(base
),
859 prot
, mmu_linear_psize
, mmu_kernel_ssize
));
861 memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE
);
864 * If we have a memory_limit and we've allocated TCEs then we need to
865 * explicitly map the TCE area at the top of RAM. We also cope with the
866 * case that the TCEs start below memory_limit.
867 * tce_alloc_start/end are 16MB aligned so the mapping should work
868 * for either 4K or 16MB pages.
870 if (tce_alloc_start
) {
871 tce_alloc_start
= (unsigned long)__va(tce_alloc_start
);
872 tce_alloc_end
= (unsigned long)__va(tce_alloc_end
);
874 if (base
+ size
>= tce_alloc_start
)
875 tce_alloc_start
= base
+ size
+ 1;
877 BUG_ON(htab_bolt_mapping(tce_alloc_start
, tce_alloc_end
,
878 __pa(tce_alloc_start
), prot
,
879 mmu_linear_psize
, mmu_kernel_ssize
));
883 DBG(" <- htab_initialize()\n");
888 void __init
hash__early_init_mmu(void)
891 * initialize page table size
893 __pte_frag_nr
= H_PTE_FRAG_NR
;
894 __pte_frag_size_shift
= H_PTE_FRAG_SIZE_SHIFT
;
896 __pte_index_size
= H_PTE_INDEX_SIZE
;
897 __pmd_index_size
= H_PMD_INDEX_SIZE
;
898 __pud_index_size
= H_PUD_INDEX_SIZE
;
899 __pgd_index_size
= H_PGD_INDEX_SIZE
;
900 __pmd_cache_index
= H_PMD_CACHE_INDEX
;
901 __pte_table_size
= H_PTE_TABLE_SIZE
;
902 __pmd_table_size
= H_PMD_TABLE_SIZE
;
903 __pud_table_size
= H_PUD_TABLE_SIZE
;
904 __pgd_table_size
= H_PGD_TABLE_SIZE
;
906 * 4k use hugepd format, so for hash set then to
913 __kernel_virt_start
= H_KERN_VIRT_START
;
914 __kernel_virt_size
= H_KERN_VIRT_SIZE
;
915 __vmalloc_start
= H_VMALLOC_START
;
916 __vmalloc_end
= H_VMALLOC_END
;
917 vmemmap
= (struct page
*)H_VMEMMAP_BASE
;
918 ioremap_bot
= IOREMAP_BASE
;
921 pci_io_base
= ISA_IO_BASE
;
924 /* Select appropriate backend */
925 if (firmware_has_feature(FW_FEATURE_PS3_LV1
))
927 else if (firmware_has_feature(FW_FEATURE_LPAR
))
929 else if (IS_ENABLED(CONFIG_PPC_NATIVE
))
932 if (!mmu_hash_ops
.hpte_insert
)
933 panic("hash__early_init_mmu: No MMU hash ops defined!\n");
935 /* Initialize the MMU Hash table and create the linear mapping
936 * of memory. Has to be done before SLB initialization as this is
937 * currently where the page size encoding is obtained.
941 pr_info("Initializing hash mmu with SLB\n");
942 /* Initialize SLB management */
947 void hash__early_init_mmu_secondary(void)
949 /* Initialize hash table for that CPU */
950 if (!firmware_has_feature(FW_FEATURE_LPAR
)) {
951 if (!cpu_has_feature(CPU_FTR_ARCH_300
))
952 mtspr(SPRN_SDR1
, _SDR1
);
955 __pa(partition_tb
) | (PATB_SIZE_SHIFT
- 12));
960 #endif /* CONFIG_SMP */
963 * Called by asm hashtable.S for doing lazy icache flush
965 unsigned int hash_page_do_lazy_icache(unsigned int pp
, pte_t pte
, int trap
)
969 if (!pfn_valid(pte_pfn(pte
)))
972 page
= pte_page(pte
);
975 if (!test_bit(PG_arch_1
, &page
->flags
) && !PageReserved(page
)) {
977 flush_dcache_icache_page(page
);
978 set_bit(PG_arch_1
, &page
->flags
);
985 #ifdef CONFIG_PPC_MM_SLICES
986 static unsigned int get_paca_psize(unsigned long addr
)
989 unsigned char *hpsizes
;
990 unsigned long index
, mask_index
;
992 if (addr
< SLICE_LOW_TOP
) {
993 lpsizes
= get_paca()->mm_ctx_low_slices_psize
;
994 index
= GET_LOW_SLICE_INDEX(addr
);
995 return (lpsizes
>> (index
* 4)) & 0xF;
997 hpsizes
= get_paca()->mm_ctx_high_slices_psize
;
998 index
= GET_HIGH_SLICE_INDEX(addr
);
999 mask_index
= index
& 0x1;
1000 return (hpsizes
[index
>> 1] >> (mask_index
* 4)) & 0xF;
1004 unsigned int get_paca_psize(unsigned long addr
)
1006 return get_paca()->mm_ctx_user_psize
;
1011 * Demote a segment to using 4k pages.
1012 * For now this makes the whole process use 4k pages.
1014 #ifdef CONFIG_PPC_64K_PAGES
1015 void demote_segment_4k(struct mm_struct
*mm
, unsigned long addr
)
1017 if (get_slice_psize(mm
, addr
) == MMU_PAGE_4K
)
1019 slice_set_range_psize(mm
, addr
, 1, MMU_PAGE_4K
);
1020 copro_flush_all_slbs(mm
);
1021 if ((get_paca_psize(addr
) != MMU_PAGE_4K
) && (current
->mm
== mm
)) {
1023 copy_mm_to_paca(&mm
->context
);
1024 slb_flush_and_rebolt();
1027 #endif /* CONFIG_PPC_64K_PAGES */
1029 #ifdef CONFIG_PPC_SUBPAGE_PROT
1031 * This looks up a 2-bit protection code for a 4k subpage of a 64k page.
1032 * Userspace sets the subpage permissions using the subpage_prot system call.
1034 * Result is 0: full permissions, _PAGE_RW: read-only,
1035 * _PAGE_RWX: no access.
1037 static int subpage_protection(struct mm_struct
*mm
, unsigned long ea
)
1039 struct subpage_prot_table
*spt
= &mm
->context
.spt
;
1043 if (ea
>= spt
->maxaddr
)
1045 if (ea
< 0x100000000UL
) {
1046 /* addresses below 4GB use spt->low_prot */
1047 sbpm
= spt
->low_prot
;
1049 sbpm
= spt
->protptrs
[ea
>> SBP_L3_SHIFT
];
1053 sbpp
= sbpm
[(ea
>> SBP_L2_SHIFT
) & (SBP_L2_COUNT
- 1)];
1056 spp
= sbpp
[(ea
>> PAGE_SHIFT
) & (SBP_L1_COUNT
- 1)];
1058 /* extract 2-bit bitfield for this 4k subpage */
1059 spp
>>= 30 - 2 * ((ea
>> 12) & 0xf);
1062 * 0 -> full premission
1065 * We return the flag that need to be cleared.
1067 spp
= ((spp
& 2) ? _PAGE_RWX
: 0) | ((spp
& 1) ? _PAGE_WRITE
: 0);
1071 #else /* CONFIG_PPC_SUBPAGE_PROT */
1072 static inline int subpage_protection(struct mm_struct
*mm
, unsigned long ea
)
1078 void hash_failure_debug(unsigned long ea
, unsigned long access
,
1079 unsigned long vsid
, unsigned long trap
,
1080 int ssize
, int psize
, int lpsize
, unsigned long pte
)
1082 if (!printk_ratelimit())
1084 pr_info("mm: Hashing failure ! EA=0x%lx access=0x%lx current=%s\n",
1085 ea
, access
, current
->comm
);
1086 pr_info(" trap=0x%lx vsid=0x%lx ssize=%d base psize=%d psize %d pte=0x%lx\n",
1087 trap
, vsid
, ssize
, psize
, lpsize
, pte
);
1090 static void check_paca_psize(unsigned long ea
, struct mm_struct
*mm
,
1091 int psize
, bool user_region
)
1094 if (psize
!= get_paca_psize(ea
)) {
1095 copy_mm_to_paca(&mm
->context
);
1096 slb_flush_and_rebolt();
1098 } else if (get_paca()->vmalloc_sllp
!=
1099 mmu_psize_defs
[mmu_vmalloc_psize
].sllp
) {
1100 get_paca()->vmalloc_sllp
=
1101 mmu_psize_defs
[mmu_vmalloc_psize
].sllp
;
1102 slb_vmalloc_update();
1108 * 1 - normal page fault
1109 * -1 - critical hash insertion error
1110 * -2 - access not permitted by subpage protection mechanism
1112 int hash_page_mm(struct mm_struct
*mm
, unsigned long ea
,
1113 unsigned long access
, unsigned long trap
,
1114 unsigned long flags
)
1117 enum ctx_state prev_state
= exception_enter();
1122 const struct cpumask
*tmp
;
1123 int rc
, user_region
= 0;
1126 DBG_LOW("hash_page(ea=%016lx, access=%lx, trap=%lx\n",
1128 trace_hash_fault(ea
, access
, trap
);
1130 /* Get region & vsid */
1131 switch (REGION_ID(ea
)) {
1132 case USER_REGION_ID
:
1135 DBG_LOW(" user region with no mm !\n");
1139 psize
= get_slice_psize(mm
, ea
);
1140 ssize
= user_segment_size(ea
);
1141 vsid
= get_vsid(mm
->context
.id
, ea
, ssize
);
1143 case VMALLOC_REGION_ID
:
1144 vsid
= get_kernel_vsid(ea
, mmu_kernel_ssize
);
1145 if (ea
< VMALLOC_END
)
1146 psize
= mmu_vmalloc_psize
;
1148 psize
= mmu_io_psize
;
1149 ssize
= mmu_kernel_ssize
;
1152 /* Not a valid range
1153 * Send the problem up to do_page_fault
1158 DBG_LOW(" mm=%p, mm->pgdir=%p, vsid=%016lx\n", mm
, mm
->pgd
, vsid
);
1162 DBG_LOW("Bad address!\n");
1168 if (pgdir
== NULL
) {
1173 /* Check CPU locality */
1174 tmp
= cpumask_of(smp_processor_id());
1175 if (user_region
&& cpumask_equal(mm_cpumask(mm
), tmp
))
1176 flags
|= HPTE_LOCAL_UPDATE
;
1178 #ifndef CONFIG_PPC_64K_PAGES
1179 /* If we use 4K pages and our psize is not 4K, then we might
1180 * be hitting a special driver mapping, and need to align the
1181 * address before we fetch the PTE.
1183 * It could also be a hugepage mapping, in which case this is
1184 * not necessary, but it's not harmful, either.
1186 if (psize
!= MMU_PAGE_4K
)
1187 ea
&= ~((1ul << mmu_psize_defs
[psize
].shift
) - 1);
1188 #endif /* CONFIG_PPC_64K_PAGES */
1190 /* Get PTE and page size from page tables */
1191 ptep
= __find_linux_pte_or_hugepte(pgdir
, ea
, &is_thp
, &hugeshift
);
1192 if (ptep
== NULL
|| !pte_present(*ptep
)) {
1193 DBG_LOW(" no PTE !\n");
1198 /* Add _PAGE_PRESENT to the required access perm */
1199 access
|= _PAGE_PRESENT
;
1201 /* Pre-check access permissions (will be re-checked atomically
1202 * in __hash_page_XX but this pre-check is a fast path
1204 if (!check_pte_access(access
, pte_val(*ptep
))) {
1205 DBG_LOW(" no access !\n");
1212 rc
= __hash_page_thp(ea
, access
, vsid
, (pmd_t
*)ptep
,
1213 trap
, flags
, ssize
, psize
);
1214 #ifdef CONFIG_HUGETLB_PAGE
1216 rc
= __hash_page_huge(ea
, access
, vsid
, ptep
, trap
,
1217 flags
, ssize
, hugeshift
, psize
);
1221 * if we have hugeshift, and is not transhuge with
1222 * hugetlb disabled, something is really wrong.
1228 if (current
->mm
== mm
)
1229 check_paca_psize(ea
, mm
, psize
, user_region
);
1234 #ifndef CONFIG_PPC_64K_PAGES
1235 DBG_LOW(" i-pte: %016lx\n", pte_val(*ptep
));
1237 DBG_LOW(" i-pte: %016lx %016lx\n", pte_val(*ptep
),
1238 pte_val(*(ptep
+ PTRS_PER_PTE
)));
1240 /* Do actual hashing */
1241 #ifdef CONFIG_PPC_64K_PAGES
1242 /* If H_PAGE_4K_PFN is set, make sure this is a 4k segment */
1243 if ((pte_val(*ptep
) & H_PAGE_4K_PFN
) && psize
== MMU_PAGE_64K
) {
1244 demote_segment_4k(mm
, ea
);
1245 psize
= MMU_PAGE_4K
;
1248 /* If this PTE is non-cacheable and we have restrictions on
1249 * using non cacheable large pages, then we switch to 4k
1251 if (mmu_ci_restrictions
&& psize
== MMU_PAGE_64K
&& pte_ci(*ptep
)) {
1253 demote_segment_4k(mm
, ea
);
1254 psize
= MMU_PAGE_4K
;
1255 } else if (ea
< VMALLOC_END
) {
1257 * some driver did a non-cacheable mapping
1258 * in vmalloc space, so switch vmalloc
1261 printk(KERN_ALERT
"Reducing vmalloc segment "
1262 "to 4kB pages because of "
1263 "non-cacheable mapping\n");
1264 psize
= mmu_vmalloc_psize
= MMU_PAGE_4K
;
1265 copro_flush_all_slbs(mm
);
1269 #endif /* CONFIG_PPC_64K_PAGES */
1271 if (current
->mm
== mm
)
1272 check_paca_psize(ea
, mm
, psize
, user_region
);
1274 #ifdef CONFIG_PPC_64K_PAGES
1275 if (psize
== MMU_PAGE_64K
)
1276 rc
= __hash_page_64K(ea
, access
, vsid
, ptep
, trap
,
1279 #endif /* CONFIG_PPC_64K_PAGES */
1281 int spp
= subpage_protection(mm
, ea
);
1285 rc
= __hash_page_4K(ea
, access
, vsid
, ptep
, trap
,
1289 /* Dump some info in case of hash insertion failure, they should
1290 * never happen so it is really useful to know if/when they do
1293 hash_failure_debug(ea
, access
, vsid
, trap
, ssize
, psize
,
1294 psize
, pte_val(*ptep
));
1295 #ifndef CONFIG_PPC_64K_PAGES
1296 DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep
));
1298 DBG_LOW(" o-pte: %016lx %016lx\n", pte_val(*ptep
),
1299 pte_val(*(ptep
+ PTRS_PER_PTE
)));
1301 DBG_LOW(" -> rc=%d\n", rc
);
1304 exception_exit(prev_state
);
1307 EXPORT_SYMBOL_GPL(hash_page_mm
);
1309 int hash_page(unsigned long ea
, unsigned long access
, unsigned long trap
,
1310 unsigned long dsisr
)
1312 unsigned long flags
= 0;
1313 struct mm_struct
*mm
= current
->mm
;
1315 if (REGION_ID(ea
) == VMALLOC_REGION_ID
)
1318 if (dsisr
& DSISR_NOHPTE
)
1319 flags
|= HPTE_NOHPTE_UPDATE
;
1321 return hash_page_mm(mm
, ea
, access
, trap
, flags
);
1323 EXPORT_SYMBOL_GPL(hash_page
);
1325 int __hash_page(unsigned long ea
, unsigned long msr
, unsigned long trap
,
1326 unsigned long dsisr
)
1328 unsigned long access
= _PAGE_PRESENT
| _PAGE_READ
;
1329 unsigned long flags
= 0;
1330 struct mm_struct
*mm
= current
->mm
;
1332 if (REGION_ID(ea
) == VMALLOC_REGION_ID
)
1335 if (dsisr
& DSISR_NOHPTE
)
1336 flags
|= HPTE_NOHPTE_UPDATE
;
1338 if (dsisr
& DSISR_ISSTORE
)
1339 access
|= _PAGE_WRITE
;
1341 * We set _PAGE_PRIVILEGED only when
1342 * kernel mode access kernel space.
1344 * _PAGE_PRIVILEGED is NOT set
1345 * 1) when kernel mode access user space
1346 * 2) user space access kernel space.
1348 access
|= _PAGE_PRIVILEGED
;
1349 if ((msr
& MSR_PR
) || (REGION_ID(ea
) == USER_REGION_ID
))
1350 access
&= ~_PAGE_PRIVILEGED
;
1353 access
|= _PAGE_EXEC
;
1355 return hash_page_mm(mm
, ea
, access
, trap
, flags
);
1358 #ifdef CONFIG_PPC_MM_SLICES
1359 static bool should_hash_preload(struct mm_struct
*mm
, unsigned long ea
)
1361 int psize
= get_slice_psize(mm
, ea
);
1363 /* We only prefault standard pages for now */
1364 if (unlikely(psize
!= mm
->context
.user_psize
))
1368 * Don't prefault if subpage protection is enabled for the EA.
1370 if (unlikely((psize
== MMU_PAGE_4K
) && subpage_protection(mm
, ea
)))
1376 static bool should_hash_preload(struct mm_struct
*mm
, unsigned long ea
)
1382 void hash_preload(struct mm_struct
*mm
, unsigned long ea
,
1383 unsigned long access
, unsigned long trap
)
1389 unsigned long flags
;
1390 int rc
, ssize
, update_flags
= 0;
1392 BUG_ON(REGION_ID(ea
) != USER_REGION_ID
);
1394 if (!should_hash_preload(mm
, ea
))
1397 DBG_LOW("hash_preload(mm=%p, mm->pgdir=%p, ea=%016lx, access=%lx,"
1398 " trap=%lx\n", mm
, mm
->pgd
, ea
, access
, trap
);
1400 /* Get Linux PTE if available */
1406 ssize
= user_segment_size(ea
);
1407 vsid
= get_vsid(mm
->context
.id
, ea
, ssize
);
1411 * Hash doesn't like irqs. Walking linux page table with irq disabled
1412 * saves us from holding multiple locks.
1414 local_irq_save(flags
);
1417 * THP pages use update_mmu_cache_pmd. We don't do
1418 * hash preload there. Hence can ignore THP here
1420 ptep
= find_linux_pte_or_hugepte(pgdir
, ea
, NULL
, &hugepage_shift
);
1424 WARN_ON(hugepage_shift
);
1425 #ifdef CONFIG_PPC_64K_PAGES
1426 /* If either H_PAGE_4K_PFN or cache inhibited is set (and we are on
1427 * a 64K kernel), then we don't preload, hash_page() will take
1428 * care of it once we actually try to access the page.
1429 * That way we don't have to duplicate all of the logic for segment
1430 * page size demotion here
1432 if ((pte_val(*ptep
) & H_PAGE_4K_PFN
) || pte_ci(*ptep
))
1434 #endif /* CONFIG_PPC_64K_PAGES */
1436 /* Is that local to this CPU ? */
1437 if (cpumask_equal(mm_cpumask(mm
), cpumask_of(smp_processor_id())))
1438 update_flags
|= HPTE_LOCAL_UPDATE
;
1441 #ifdef CONFIG_PPC_64K_PAGES
1442 if (mm
->context
.user_psize
== MMU_PAGE_64K
)
1443 rc
= __hash_page_64K(ea
, access
, vsid
, ptep
, trap
,
1444 update_flags
, ssize
);
1446 #endif /* CONFIG_PPC_64K_PAGES */
1447 rc
= __hash_page_4K(ea
, access
, vsid
, ptep
, trap
, update_flags
,
1448 ssize
, subpage_protection(mm
, ea
));
1450 /* Dump some info in case of hash insertion failure, they should
1451 * never happen so it is really useful to know if/when they do
1454 hash_failure_debug(ea
, access
, vsid
, trap
, ssize
,
1455 mm
->context
.user_psize
,
1456 mm
->context
.user_psize
,
1459 local_irq_restore(flags
);
1462 /* WARNING: This is called from hash_low_64.S, if you change this prototype,
1463 * do not forget to update the assembly call site !
1465 void flush_hash_page(unsigned long vpn
, real_pte_t pte
, int psize
, int ssize
,
1466 unsigned long flags
)
1468 unsigned long hash
, index
, shift
, hidx
, slot
;
1469 int local
= flags
& HPTE_LOCAL_UPDATE
;
1471 DBG_LOW("flush_hash_page(vpn=%016lx)\n", vpn
);
1472 pte_iterate_hashed_subpages(pte
, psize
, vpn
, index
, shift
) {
1473 hash
= hpt_hash(vpn
, shift
, ssize
);
1474 hidx
= __rpte_to_hidx(pte
, index
);
1475 if (hidx
& _PTEIDX_SECONDARY
)
1477 slot
= (hash
& htab_hash_mask
) * HPTES_PER_GROUP
;
1478 slot
+= hidx
& _PTEIDX_GROUP_IX
;
1479 DBG_LOW(" sub %ld: hash=%lx, hidx=%lx\n", index
, slot
, hidx
);
1481 * We use same base page size and actual psize, because we don't
1482 * use these functions for hugepage
1484 mmu_hash_ops
.hpte_invalidate(slot
, vpn
, psize
, psize
,
1486 } pte_iterate_hashed_end();
1488 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1489 /* Transactions are not aborted by tlbiel, only tlbie.
1490 * Without, syncing a page back to a block device w/ PIO could pick up
1491 * transactional data (bad!) so we force an abort here. Before the
1492 * sync the page will be made read-only, which will flush_hash_page.
1493 * BIG ISSUE here: if the kernel uses a page from userspace without
1494 * unmapping it first, it may see the speculated version.
1496 if (local
&& cpu_has_feature(CPU_FTR_TM
) &&
1497 current
->thread
.regs
&&
1498 MSR_TM_ACTIVE(current
->thread
.regs
->msr
)) {
1500 tm_abort(TM_CAUSE_TLBI
);
1505 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
1506 void flush_hash_hugepage(unsigned long vsid
, unsigned long addr
,
1507 pmd_t
*pmdp
, unsigned int psize
, int ssize
,
1508 unsigned long flags
)
1510 int i
, max_hpte_count
, valid
;
1511 unsigned long s_addr
;
1512 unsigned char *hpte_slot_array
;
1513 unsigned long hidx
, shift
, vpn
, hash
, slot
;
1514 int local
= flags
& HPTE_LOCAL_UPDATE
;
1516 s_addr
= addr
& HPAGE_PMD_MASK
;
1517 hpte_slot_array
= get_hpte_slot_array(pmdp
);
1519 * IF we try to do a HUGE PTE update after a withdraw is done.
1520 * we will find the below NULL. This happens when we do
1521 * split_huge_page_pmd
1523 if (!hpte_slot_array
)
1526 if (mmu_hash_ops
.hugepage_invalidate
) {
1527 mmu_hash_ops
.hugepage_invalidate(vsid
, s_addr
, hpte_slot_array
,
1528 psize
, ssize
, local
);
1532 * No bluk hpte removal support, invalidate each entry
1534 shift
= mmu_psize_defs
[psize
].shift
;
1535 max_hpte_count
= HPAGE_PMD_SIZE
>> shift
;
1536 for (i
= 0; i
< max_hpte_count
; i
++) {
1538 * 8 bits per each hpte entries
1539 * 000| [ secondary group (one bit) | hidx (3 bits) | valid bit]
1541 valid
= hpte_valid(hpte_slot_array
, i
);
1544 hidx
= hpte_hash_index(hpte_slot_array
, i
);
1547 addr
= s_addr
+ (i
* (1ul << shift
));
1548 vpn
= hpt_vpn(addr
, vsid
, ssize
);
1549 hash
= hpt_hash(vpn
, shift
, ssize
);
1550 if (hidx
& _PTEIDX_SECONDARY
)
1553 slot
= (hash
& htab_hash_mask
) * HPTES_PER_GROUP
;
1554 slot
+= hidx
& _PTEIDX_GROUP_IX
;
1555 mmu_hash_ops
.hpte_invalidate(slot
, vpn
, psize
,
1556 MMU_PAGE_16M
, ssize
, local
);
1559 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1560 /* Transactions are not aborted by tlbiel, only tlbie.
1561 * Without, syncing a page back to a block device w/ PIO could pick up
1562 * transactional data (bad!) so we force an abort here. Before the
1563 * sync the page will be made read-only, which will flush_hash_page.
1564 * BIG ISSUE here: if the kernel uses a page from userspace without
1565 * unmapping it first, it may see the speculated version.
1567 if (local
&& cpu_has_feature(CPU_FTR_TM
) &&
1568 current
->thread
.regs
&&
1569 MSR_TM_ACTIVE(current
->thread
.regs
->msr
)) {
1571 tm_abort(TM_CAUSE_TLBI
);
1576 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
1578 void flush_hash_range(unsigned long number
, int local
)
1580 if (mmu_hash_ops
.flush_hash_range
)
1581 mmu_hash_ops
.flush_hash_range(number
, local
);
1584 struct ppc64_tlb_batch
*batch
=
1585 this_cpu_ptr(&ppc64_tlb_batch
);
1587 for (i
= 0; i
< number
; i
++)
1588 flush_hash_page(batch
->vpn
[i
], batch
->pte
[i
],
1589 batch
->psize
, batch
->ssize
, local
);
1594 * low_hash_fault is called when we the low level hash code failed
1595 * to instert a PTE due to an hypervisor error
1597 void low_hash_fault(struct pt_regs
*regs
, unsigned long address
, int rc
)
1599 enum ctx_state prev_state
= exception_enter();
1601 if (user_mode(regs
)) {
1602 #ifdef CONFIG_PPC_SUBPAGE_PROT
1604 _exception(SIGSEGV
, regs
, SEGV_ACCERR
, address
);
1607 _exception(SIGBUS
, regs
, BUS_ADRERR
, address
);
1609 bad_page_fault(regs
, address
, SIGBUS
);
1611 exception_exit(prev_state
);
1614 long hpte_insert_repeating(unsigned long hash
, unsigned long vpn
,
1615 unsigned long pa
, unsigned long rflags
,
1616 unsigned long vflags
, int psize
, int ssize
)
1618 unsigned long hpte_group
;
1622 hpte_group
= ((hash
& htab_hash_mask
) *
1623 HPTES_PER_GROUP
) & ~0x7UL
;
1625 /* Insert into the hash table, primary slot */
1626 slot
= mmu_hash_ops
.hpte_insert(hpte_group
, vpn
, pa
, rflags
, vflags
,
1627 psize
, psize
, ssize
);
1629 /* Primary is full, try the secondary */
1630 if (unlikely(slot
== -1)) {
1631 hpte_group
= ((~hash
& htab_hash_mask
) *
1632 HPTES_PER_GROUP
) & ~0x7UL
;
1633 slot
= mmu_hash_ops
.hpte_insert(hpte_group
, vpn
, pa
, rflags
,
1634 vflags
| HPTE_V_SECONDARY
,
1635 psize
, psize
, ssize
);
1638 hpte_group
= ((hash
& htab_hash_mask
) *
1639 HPTES_PER_GROUP
)&~0x7UL
;
1641 mmu_hash_ops
.hpte_remove(hpte_group
);
1649 #ifdef CONFIG_DEBUG_PAGEALLOC
1650 static void kernel_map_linear_page(unsigned long vaddr
, unsigned long lmi
)
1653 unsigned long vsid
= get_kernel_vsid(vaddr
, mmu_kernel_ssize
);
1654 unsigned long vpn
= hpt_vpn(vaddr
, vsid
, mmu_kernel_ssize
);
1655 unsigned long mode
= htab_convert_pte_flags(pgprot_val(PAGE_KERNEL
));
1658 hash
= hpt_hash(vpn
, PAGE_SHIFT
, mmu_kernel_ssize
);
1660 /* Don't create HPTE entries for bad address */
1664 ret
= hpte_insert_repeating(hash
, vpn
, __pa(vaddr
), mode
,
1666 mmu_linear_psize
, mmu_kernel_ssize
);
1669 spin_lock(&linear_map_hash_lock
);
1670 BUG_ON(linear_map_hash_slots
[lmi
] & 0x80);
1671 linear_map_hash_slots
[lmi
] = ret
| 0x80;
1672 spin_unlock(&linear_map_hash_lock
);
1675 static void kernel_unmap_linear_page(unsigned long vaddr
, unsigned long lmi
)
1677 unsigned long hash
, hidx
, slot
;
1678 unsigned long vsid
= get_kernel_vsid(vaddr
, mmu_kernel_ssize
);
1679 unsigned long vpn
= hpt_vpn(vaddr
, vsid
, mmu_kernel_ssize
);
1681 hash
= hpt_hash(vpn
, PAGE_SHIFT
, mmu_kernel_ssize
);
1682 spin_lock(&linear_map_hash_lock
);
1683 BUG_ON(!(linear_map_hash_slots
[lmi
] & 0x80));
1684 hidx
= linear_map_hash_slots
[lmi
] & 0x7f;
1685 linear_map_hash_slots
[lmi
] = 0;
1686 spin_unlock(&linear_map_hash_lock
);
1687 if (hidx
& _PTEIDX_SECONDARY
)
1689 slot
= (hash
& htab_hash_mask
) * HPTES_PER_GROUP
;
1690 slot
+= hidx
& _PTEIDX_GROUP_IX
;
1691 mmu_hash_ops
.hpte_invalidate(slot
, vpn
, mmu_linear_psize
,
1693 mmu_kernel_ssize
, 0);
1696 void __kernel_map_pages(struct page
*page
, int numpages
, int enable
)
1698 unsigned long flags
, vaddr
, lmi
;
1701 local_irq_save(flags
);
1702 for (i
= 0; i
< numpages
; i
++, page
++) {
1703 vaddr
= (unsigned long)page_address(page
);
1704 lmi
= __pa(vaddr
) >> PAGE_SHIFT
;
1705 if (lmi
>= linear_map_hash_count
)
1708 kernel_map_linear_page(vaddr
, lmi
);
1710 kernel_unmap_linear_page(vaddr
, lmi
);
1712 local_irq_restore(flags
);
1714 #endif /* CONFIG_DEBUG_PAGEALLOC */
1716 void hash__setup_initial_memory_limit(phys_addr_t first_memblock_base
,
1717 phys_addr_t first_memblock_size
)
1719 /* We don't currently support the first MEMBLOCK not mapping 0
1720 * physical on those processors
1722 BUG_ON(first_memblock_base
!= 0);
1724 /* On LPAR systems, the first entry is our RMA region,
1725 * non-LPAR 64-bit hash MMU systems don't have a limitation
1726 * on real mode access, but using the first entry works well
1727 * enough. We also clamp it to 1G to avoid some funky things
1728 * such as RTAS bugs etc...
1730 ppc64_rma_size
= min_t(u64
, first_memblock_size
, 0x40000000);
1732 /* Finally limit subsequent allocations */
1733 memblock_set_current_limit(ppc64_rma_size
);