arch/powerpc/mm/ppc_mmu_32.c

   1 /*
   2  * This file contains the routines for handling the MMU on those
   3  * PowerPC implementations where the MMU substantially follows the
   4  * architecture specification.  This includes the 6xx, 7xx, 7xxx,
   5  * 8260, and POWER3 implementations but excludes the 8xx and 4xx.
   6  *  -- paulus
   7  *
   8  *  Derived from arch/ppc/mm/init.c:
   9  *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
  10  *
  11  *  Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
  12  *  and Cort Dougan (PReP) (cort@cs.nmt.edu)
  13  *    Copyright (C) 1996 Paul Mackerras
  14  *
  15  *  Derived from "arch/i386/mm/init.c"
  16  *    Copyright (C) 1991, 1992, 1993, 1994  Linus Torvalds
  17  *
  18  *  This program is free software; you can redistribute it and/or
  19  *  modify it under the terms of the GNU General Public License
  20  *  as published by the Free Software Foundation; either version
  21  *  2 of the License, or (at your option) any later version.
  22  *
  23  */
  24
  25 #include <linux/kernel.h>
  26 #include <linux/mm.h>
  27 #include <linux/init.h>
  28 #include <linux/highmem.h>
  29 #include <linux/lmb.h>
  30
  31 #include <asm/prom.h>
  32 #include <asm/mmu.h>
  33 #include <asm/machdep.h>
  34
  35 #include "mmu_decl.h"
  36
  37 struct hash_pte *Hash, *Hash_end;
  38 unsigned long Hash_size, Hash_mask;
  39 unsigned long _SDR1;
  40
  41 union ubat {                    /* BAT register values to be loaded */
  42         struct ppc_bat bat;
  43         u32     word[2];
  44 } BATS[8][2];                   /* 8 pairs of IBAT, DBAT */
  45
  46 struct batrange {               /* stores address ranges mapped by BATs */
  47         unsigned long start;
  48         unsigned long limit;
  49         phys_addr_t phys;
  50 } bat_addrs[8];
  51
  52 /*
  53  * Return PA for this VA if it is mapped by a BAT, or 0
  54  */
  55 phys_addr_t v_mapped_by_bats(unsigned long va)
  56 {
  57         int b;
  58         for (b = 0; b < 4; ++b)
  59                 if (va >= bat_addrs[b].start && va < bat_addrs[b].limit)
  60                         return bat_addrs[b].phys + (va - bat_addrs[b].start);
  61         return 0;
  62 }
  63
  64 /*
  65  * Return VA for a given PA or 0 if not mapped
  66  */
  67 unsigned long p_mapped_by_bats(phys_addr_t pa)
  68 {
  69         int b;
  70         for (b = 0; b < 4; ++b)
  71                 if (pa >= bat_addrs[b].phys
  72                     && pa < (bat_addrs[b].limit-bat_addrs[b].start)
  73                               +bat_addrs[b].phys)
  74                         return bat_addrs[b].start+(pa-bat_addrs[b].phys);
  75         return 0;
  76 }
  77
  78 unsigned long __init mmu_mapin_ram(void)
  79 {
  80 #ifdef CONFIG_POWER4
  81         return 0;
  82 #else
  83         unsigned long tot, bl, done;
  84         unsigned long max_size = (256<<20);
  85
  86         if (__map_without_bats) {
  87                 printk(KERN_DEBUG "RAM mapped without BATs\n");
  88                 return 0;
  89         }
  90
  91         /* Set up BAT2 and if necessary BAT3 to cover RAM. */
  92
  93         /* Make sure we don't map a block larger than the
  94            smallest alignment of the physical address. */
  95         tot = total_lowmem;
  96         for (bl = 128<<10; bl < max_size; bl <<= 1) {
  97                 if (bl * 2 > tot)
  98                         break;
  99         }
 100
 101         setbat(2, KERNELBASE, 0, bl, _PAGE_RAM);
 102         done = (unsigned long)bat_addrs[2].limit - KERNELBASE + 1;
 103         if ((done < tot) && !bat_addrs[3].limit) {
 104                 /* use BAT3 to cover a bit more */
 105                 tot -= done;
 106                 for (bl = 128<<10; bl < max_size; bl <<= 1)
 107                         if (bl * 2 > tot)
 108                                 break;
 109                 setbat(3, KERNELBASE+done, done, bl, _PAGE_RAM);
 110                 done = (unsigned long)bat_addrs[3].limit - KERNELBASE + 1;
 111         }
 112
 113         return done;
 114 #endif
 115 }
 116
 117 /*
 118  * Set up one of the I/D BAT (block address translation) register pairs.
 119  * The parameters are not checked; in particular size must be a power
 120  * of 2 between 128k and 256M.
 121  */
 122 void __init setbat(int index, unsigned long virt, phys_addr_t phys,
 123                    unsigned int size, int flags)
 124 {
 125         unsigned int bl;
 126         int wimgxpp;
 127         union ubat *bat = BATS[index];
 128
 129         if (((flags & _PAGE_NO_CACHE) == 0) &&
 130             cpu_has_feature(CPU_FTR_NEED_COHERENT))
 131                 flags |= _PAGE_COHERENT;
 132
 133         bl = (size >> 17) - 1;
 134         if (PVR_VER(mfspr(SPRN_PVR)) != 1) {
 135                 /* 603, 604, etc. */
 136                 /* Do DBAT first */
 137                 wimgxpp = flags & (_PAGE_WRITETHRU | _PAGE_NO_CACHE
 138                                    | _PAGE_COHERENT | _PAGE_GUARDED);
 139                 wimgxpp |= (flags & _PAGE_RW)? BPP_RW: BPP_RX;
 140                 bat[1].word[0] = virt | (bl << 2) | 2; /* Vs=1, Vp=0 */
 141                 bat[1].word[1] = BAT_PHYS_ADDR(phys) | wimgxpp;
 142 #ifndef CONFIG_KGDB /* want user access for breakpoints */
 143                 if (flags & _PAGE_USER)
 144 #endif
 145                         bat[1].bat.batu.vp = 1;
 146                 if (flags & _PAGE_GUARDED) {
 147                         /* G bit must be zero in IBATs */
 148                         bat[0].word[0] = bat[0].word[1] = 0;
 149                 } else {
 150                         /* make IBAT same as DBAT */
 151                         bat[0] = bat[1];
 152                 }
 153         } else {
 154                 /* 601 cpu */
 155                 if (bl > BL_8M)
 156                         bl = BL_8M;
 157                 wimgxpp = flags & (_PAGE_WRITETHRU | _PAGE_NO_CACHE
 158                                    | _PAGE_COHERENT);
 159                 wimgxpp |= (flags & _PAGE_RW)?
 160                         ((flags & _PAGE_USER)? PP_RWRW: PP_RWXX): PP_RXRX;
 161                 bat->word[0] = virt | wimgxpp | 4;      /* Ks=0, Ku=1 */
 162                 bat->word[1] = phys | bl | 0x40;        /* V=1 */
 163         }
 164
 165         bat_addrs[index].start = virt;
 166         bat_addrs[index].limit = virt + ((bl + 1) << 17) - 1;
 167         bat_addrs[index].phys = phys;
 168 }
 169
 170 /*
 171  * Preload a translation in the hash table
 172  */
 173 void hash_preload(struct mm_struct *mm, unsigned long ea,
 174                   unsigned long access, unsigned long trap)
 175 {
 176         pmd_t *pmd;
 177
 178         if (Hash == 0)
 179                 return;
 180         pmd = pmd_offset(pud_offset(pgd_offset(mm, ea), ea), ea);
 181         if (!pmd_none(*pmd))
 182                 add_hash_page(mm->context.id, ea, pmd_val(*pmd));
 183 }
 184
 185 /*
 186  * Initialize the hash table and patch the instructions in hashtable.S.
 187  */
 188 void __init MMU_init_hw(void)
 189 {
 190         unsigned int hmask, mb, mb2;
 191         unsigned int n_hpteg, lg_n_hpteg;
 192
 193         extern unsigned int hash_page_patch_A[];
 194         extern unsigned int hash_page_patch_B[], hash_page_patch_C[];
 195         extern unsigned int hash_page[];
 196         extern unsigned int flush_hash_patch_A[], flush_hash_patch_B[];
 197
 198         if (!cpu_has_feature(CPU_FTR_HPTE_TABLE)) {
 199                 /*
 200                  * Put a blr (procedure return) instruction at the
 201                  * start of hash_page, since we can still get DSI
 202                  * exceptions on a 603.
 203                  */
 204                 hash_page[0] = 0x4e800020;
 205                 flush_icache_range((unsigned long) &hash_page[0],
 206                                    (unsigned long) &hash_page[1]);
 207                 return;
 208         }
 209
 210         if ( ppc_md.progress ) ppc_md.progress("hash:enter", 0x105);
 211
 212 #define LG_HPTEG_SIZE   6               /* 64 bytes per HPTEG */
 213 #define SDR1_LOW_BITS   ((n_hpteg - 1) >> 10)
 214 #define MIN_N_HPTEG     1024            /* min 64kB hash table */
 215
 216         /*
 217          * Allow 1 HPTE (1/8 HPTEG) for each page of memory.
 218          * This is less than the recommended amount, but then
 219          * Linux ain't AIX.
 220          */
 221         n_hpteg = total_memory / (PAGE_SIZE * 8);
 222         if (n_hpteg < MIN_N_HPTEG)
 223                 n_hpteg = MIN_N_HPTEG;
 224         lg_n_hpteg = __ilog2(n_hpteg);
 225         if (n_hpteg & (n_hpteg - 1)) {
 226                 ++lg_n_hpteg;           /* round up if not power of 2 */
 227                 n_hpteg = 1 << lg_n_hpteg;
 228         }
 229         Hash_size = n_hpteg << LG_HPTEG_SIZE;
 230
 231         /*
 232          * Find some memory for the hash table.
 233          */
 234         if ( ppc_md.progress ) ppc_md.progress("hash:find piece", 0x322);
 235         Hash = __va(lmb_alloc_base(Hash_size, Hash_size,
 236                                    __initial_memory_limit_addr));
 237         cacheable_memzero(Hash, Hash_size);
 238         _SDR1 = __pa(Hash) | SDR1_LOW_BITS;
 239
 240         Hash_end = (struct hash_pte *) ((unsigned long)Hash + Hash_size);
 241
 242         printk("Total memory = %ldMB; using %ldkB for hash table (at %p)\n",
 243                total_memory >> 20, Hash_size >> 10, Hash);
 244
 245
 246         /*
 247          * Patch up the instructions in hashtable.S:create_hpte
 248          */
 249         if ( ppc_md.progress ) ppc_md.progress("hash:patch", 0x345);
 250         Hash_mask = n_hpteg - 1;
 251         hmask = Hash_mask >> (16 - LG_HPTEG_SIZE);
 252         mb2 = mb = 32 - LG_HPTEG_SIZE - lg_n_hpteg;
 253         if (lg_n_hpteg > 16)
 254                 mb2 = 16 - LG_HPTEG_SIZE;
 255
 256         hash_page_patch_A[0] = (hash_page_patch_A[0] & ~0xffff)
 257                 | ((unsigned int)(Hash) >> 16);
 258         hash_page_patch_A[1] = (hash_page_patch_A[1] & ~0x7c0) | (mb << 6);
 259         hash_page_patch_A[2] = (hash_page_patch_A[2] & ~0x7c0) | (mb2 << 6);
 260         hash_page_patch_B[0] = (hash_page_patch_B[0] & ~0xffff) | hmask;
 261         hash_page_patch_C[0] = (hash_page_patch_C[0] & ~0xffff) | hmask;
 262
 263         /*
 264          * Ensure that the locations we've patched have been written
 265          * out from the data cache and invalidated in the instruction
 266          * cache, on those machines with split caches.
 267          */
 268         flush_icache_range((unsigned long) &hash_page_patch_A[0],
 269                            (unsigned long) &hash_page_patch_C[1]);
 270
 271         /*
 272          * Patch up the instructions in hashtable.S:flush_hash_page
 273          */
 274         flush_hash_patch_A[0] = (flush_hash_patch_A[0] & ~0xffff)
 275                 | ((unsigned int)(Hash) >> 16);
 276         flush_hash_patch_A[1] = (flush_hash_patch_A[1] & ~0x7c0) | (mb << 6);
 277         flush_hash_patch_A[2] = (flush_hash_patch_A[2] & ~0x7c0) | (mb2 << 6);
 278         flush_hash_patch_B[0] = (flush_hash_patch_B[0] & ~0xffff) | hmask;
 279         flush_icache_range((unsigned long) &flush_hash_patch_A[0],
 280                            (unsigned long) &flush_hash_patch_B[1]);
 281
 282         if ( ppc_md.progress ) ppc_md.progress("hash:done", 0x205);
 283 }