arch/powerpc/mm/slb.c

   1 /*
   2  * PowerPC64 SLB support.
   3  *
   4  * Copyright (C) 2004 David Gibson <dwg@au.ibm.com>, IBM
   5  * Based on earlier code written by:
   6  * Dave Engebretsen and Mike Corrigan {engebret|mikejc}@us.ibm.com
   7  *    Copyright (c) 2001 Dave Engebretsen
   8  * Copyright (C) 2002 Anton Blanchard <anton@au.ibm.com>, IBM
   9  *
  10  *
  11  *      This program is free software; you can redistribute it and/or
  12  *      modify it under the terms of the GNU General Public License
  13  *      as published by the Free Software Foundation; either version
  14  *      2 of the License, or (at your option) any later version.
  15  */
  16
  17 #include <asm/pgtable.h>
  18 #include <asm/mmu.h>
  19 #include <asm/mmu_context.h>
  20 #include <asm/paca.h>
  21 #include <asm/cputable.h>
  22 #include <asm/cacheflush.h>
  23 #include <asm/smp.h>
  24 #include <linux/compiler.h>
  25 #include <asm/udbg.h>
  26 #include <asm/code-patching.h>
  27
  28 enum slb_index {
  29         LINEAR_INDEX    = 0, /* Kernel linear map  (0xc000000000000000) */
  30         VMALLOC_INDEX   = 1, /* Kernel virtual map (0xd000000000000000) */
  31         KSTACK_INDEX    = 2, /* Kernel stack map */
  32 };
  33
  34 extern void slb_allocate_realmode(unsigned long ea);
  35 extern void slb_allocate_user(unsigned long ea);
  36
  37 static void slb_allocate(unsigned long ea)
  38 {
  39         /* Currently, we do real mode for all SLBs including user, but
  40          * that will change if we bring back dynamic VSIDs
  41          */
  42         slb_allocate_realmode(ea);
  43 }
  44
  45 #define slb_esid_mask(ssize)    \
  46         (((ssize) == MMU_SEGSIZE_256M)? ESID_MASK: ESID_MASK_1T)
  47
  48 static inline unsigned long mk_esid_data(unsigned long ea, int ssize,
  49                                          enum slb_index index)
  50 {
  51         return (ea & slb_esid_mask(ssize)) | SLB_ESID_V | index;
  52 }
  53
  54 static inline unsigned long mk_vsid_data(unsigned long ea, int ssize,
  55                                          unsigned long flags)
  56 {
  57         return (get_kernel_vsid(ea, ssize) << slb_vsid_shift(ssize)) | flags |
  58                 ((unsigned long) ssize << SLB_VSID_SSIZE_SHIFT);
  59 }
  60
  61 static inline void slb_shadow_update(unsigned long ea, int ssize,
  62                                      unsigned long flags,
  63                                      enum slb_index index)
  64 {
  65         struct slb_shadow *p = get_slb_shadow();
  66
  67         /*
  68          * Clear the ESID first so the entry is not valid while we are
  69          * updating it.  No write barriers are needed here, provided
  70          * we only update the current CPU's SLB shadow buffer.
  71          */
  72         p->save_area[index].esid = 0;
  73         p->save_area[index].vsid = cpu_to_be64(mk_vsid_data(ea, ssize, flags));
  74         p->save_area[index].esid = cpu_to_be64(mk_esid_data(ea, ssize, index));
  75 }
  76
  77 static inline void slb_shadow_clear(enum slb_index index)
  78 {
  79         get_slb_shadow()->save_area[index].esid = 0;
  80 }
  81
  82 static inline void create_shadowed_slbe(unsigned long ea, int ssize,
  83                                         unsigned long flags,
  84                                         enum slb_index index)
  85 {
  86         /*
  87          * Updating the shadow buffer before writing the SLB ensures
  88          * we don't get a stale entry here if we get preempted by PHYP
  89          * between these two statements.
  90          */
  91         slb_shadow_update(ea, ssize, flags, index);
  92
  93         asm volatile("slbmte  %0,%1" :
  94                      : "r" (mk_vsid_data(ea, ssize, flags)),
  95                        "r" (mk_esid_data(ea, ssize, index))
  96                      : "memory" );
  97 }
  98
  99 static void __slb_flush_and_rebolt(void)
 100 {
 101         /* If you change this make sure you change SLB_NUM_BOLTED
 102          * and PR KVM appropriately too. */
 103         unsigned long linear_llp, vmalloc_llp, lflags, vflags;
 104         unsigned long ksp_esid_data, ksp_vsid_data;
 105
 106         linear_llp = mmu_psize_defs[mmu_linear_psize].sllp;
 107         vmalloc_llp = mmu_psize_defs[mmu_vmalloc_psize].sllp;
 108         lflags = SLB_VSID_KERNEL | linear_llp;
 109         vflags = SLB_VSID_KERNEL | vmalloc_llp;
 110
 111         ksp_esid_data = mk_esid_data(get_paca()->kstack, mmu_kernel_ssize, KSTACK_INDEX);
 112         if ((ksp_esid_data & ~0xfffffffUL) <= PAGE_OFFSET) {
 113                 ksp_esid_data &= ~SLB_ESID_V;
 114                 ksp_vsid_data = 0;
 115                 slb_shadow_clear(KSTACK_INDEX);
 116         } else {
 117                 /* Update stack entry; others don't change */
 118                 slb_shadow_update(get_paca()->kstack, mmu_kernel_ssize, lflags, KSTACK_INDEX);
 119                 ksp_vsid_data =
 120                         be64_to_cpu(get_slb_shadow()->save_area[KSTACK_INDEX].vsid);
 121         }
 122
 123         /* We need to do this all in asm, so we're sure we don't touch
 124          * the stack between the slbia and rebolting it. */
 125         asm volatile("isync\n"
 126                      "slbia\n"
 127                      /* Slot 1 - first VMALLOC segment */
 128                      "slbmte    %0,%1\n"
 129                      /* Slot 2 - kernel stack */
 130                      "slbmte    %2,%3\n"
 131                      "isync"
 132                      :: "r"(mk_vsid_data(VMALLOC_START, mmu_kernel_ssize, vflags)),
 133                         "r"(mk_esid_data(VMALLOC_START, mmu_kernel_ssize, 1)),
 134                         "r"(ksp_vsid_data),
 135                         "r"(ksp_esid_data)
 136                      : "memory");
 137 }
 138
 139 void slb_flush_and_rebolt(void)
 140 {
 141
 142         WARN_ON(!irqs_disabled());
 143
 144         /*
 145          * We can't take a PMU exception in the following code, so hard
 146          * disable interrupts.
 147          */
 148         hard_irq_disable();
 149
 150         __slb_flush_and_rebolt();
 151         get_paca()->slb_cache_ptr = 0;
 152 }
 153
 154 void slb_vmalloc_update(void)
 155 {
 156         unsigned long vflags;
 157
 158         vflags = SLB_VSID_KERNEL | mmu_psize_defs[mmu_vmalloc_psize].sllp;
 159         slb_shadow_update(VMALLOC_START, mmu_kernel_ssize, vflags, VMALLOC_INDEX);
 160         slb_flush_and_rebolt();
 161 }
 162
 163 /* Helper function to compare esids.  There are four cases to handle.
 164  * 1. The system is not 1T segment size capable.  Use the GET_ESID compare.
 165  * 2. The system is 1T capable, both addresses are < 1T, use the GET_ESID compare.
 166  * 3. The system is 1T capable, only one of the two addresses is > 1T.  This is not a match.
 167  * 4. The system is 1T capable, both addresses are > 1T, use the GET_ESID_1T macro to compare.
 168  */
 169 static inline int esids_match(unsigned long addr1, unsigned long addr2)
 170 {
 171         int esid_1t_count;
 172
 173         /* System is not 1T segment size capable. */
 174         if (!mmu_has_feature(MMU_FTR_1T_SEGMENT))
 175                 return (GET_ESID(addr1) == GET_ESID(addr2));
 176
 177         esid_1t_count = (((addr1 >> SID_SHIFT_1T) != 0) +
 178                                 ((addr2 >> SID_SHIFT_1T) != 0));
 179
 180         /* both addresses are < 1T */
 181         if (esid_1t_count == 0)
 182                 return (GET_ESID(addr1) == GET_ESID(addr2));
 183
 184         /* One address < 1T, the other > 1T.  Not a match */
 185         if (esid_1t_count == 1)
 186                 return 0;
 187
 188         /* Both addresses are > 1T. */
 189         return (GET_ESID_1T(addr1) == GET_ESID_1T(addr2));
 190 }
 191
 192 /* Flush all user entries from the segment table of the current processor. */
 193 void switch_slb(struct task_struct *tsk, struct mm_struct *mm)
 194 {
 195         unsigned long offset;
 196         unsigned long slbie_data = 0;
 197         unsigned long pc = KSTK_EIP(tsk);
 198         unsigned long stack = KSTK_ESP(tsk);
 199         unsigned long exec_base;
 200
 201         /*
 202          * We need interrupts hard-disabled here, not just soft-disabled,
 203          * so that a PMU interrupt can't occur, which might try to access
 204          * user memory (to get a stack trace) and possible cause an SLB miss
 205          * which would update the slb_cache/slb_cache_ptr fields in the PACA.
 206          */
 207         hard_irq_disable();
 208         offset = get_paca()->slb_cache_ptr;
 209         if (!mmu_has_feature(MMU_FTR_NO_SLBIE_B) &&
 210             offset <= SLB_CACHE_ENTRIES) {
 211                 int i;
 212                 asm volatile("isync" : : : "memory");
 213                 for (i = 0; i < offset; i++) {
 214                         slbie_data = (unsigned long)get_paca()->slb_cache[i]
 215                                 << SID_SHIFT; /* EA */
 216                         slbie_data |= user_segment_size(slbie_data)
 217                                 << SLBIE_SSIZE_SHIFT;
 218                         slbie_data |= SLBIE_C; /* C set for user addresses */
 219                         asm volatile("slbie %0" : : "r" (slbie_data));
 220                 }
 221                 asm volatile("isync" : : : "memory");
 222         } else {
 223                 __slb_flush_and_rebolt();
 224         }
 225
 226         /* Workaround POWER5 < DD2.1 issue */
 227         if (offset == 1 || offset > SLB_CACHE_ENTRIES)
 228                 asm volatile("slbie %0" : : "r" (slbie_data));
 229
 230         get_paca()->slb_cache_ptr = 0;
 231         copy_mm_to_paca(&mm->context);
 232
 233         /*
 234          * preload some userspace segments into the SLB.
 235          * Almost all 32 and 64bit PowerPC executables are linked at
 236          * 0x10000000 so it makes sense to preload this segment.
 237          */
 238         exec_base = 0x10000000;
 239
 240         if (is_kernel_addr(pc) || is_kernel_addr(stack) ||
 241             is_kernel_addr(exec_base))
 242                 return;
 243
 244         slb_allocate(pc);
 245
 246         if (!esids_match(pc, stack))
 247                 slb_allocate(stack);
 248
 249         if (!esids_match(pc, exec_base) &&
 250             !esids_match(stack, exec_base))
 251                 slb_allocate(exec_base);
 252 }
 253
 254 static inline void patch_slb_encoding(unsigned int *insn_addr,
 255                                       unsigned int immed)
 256 {
 257
 258         /*
 259          * This function patches either an li or a cmpldi instruction with
 260          * a new immediate value. This relies on the fact that both li
 261          * (which is actually addi) and cmpldi both take a 16-bit immediate
 262          * value, and it is situated in the same location in the instruction,
 263          * ie. bits 16-31 (Big endian bit order) or the lower 16 bits.
 264          * The signedness of the immediate operand differs between the two
 265          * instructions however this code is only ever patching a small value,
 266          * much less than 1 << 15, so we can get away with it.
 267          * To patch the value we read the existing instruction, clear the
 268          * immediate value, and or in our new value, then write the instruction
 269          * back.
 270          */
 271         unsigned int insn = (*insn_addr & 0xffff0000) | immed;
 272         patch_instruction(insn_addr, insn);
 273 }
 274
 275 extern u32 slb_miss_kernel_load_linear[];
 276 extern u32 slb_miss_kernel_load_io[];
 277 extern u32 slb_compare_rr_to_size[];
 278 extern u32 slb_miss_kernel_load_vmemmap[];
 279
 280 void slb_set_size(u16 size)
 281 {
 282         if (mmu_slb_size == size)
 283                 return;
 284
 285         mmu_slb_size = size;
 286         patch_slb_encoding(slb_compare_rr_to_size, mmu_slb_size);
 287 }
 288
 289 void slb_initialize(void)
 290 {
 291         unsigned long linear_llp, vmalloc_llp, io_llp;
 292         unsigned long lflags, vflags;
 293         static int slb_encoding_inited;
 294 #ifdef CONFIG_SPARSEMEM_VMEMMAP
 295         unsigned long vmemmap_llp;
 296 #endif
 297
 298         /* Prepare our SLB miss handler based on our page size */
 299         linear_llp = mmu_psize_defs[mmu_linear_psize].sllp;
 300         io_llp = mmu_psize_defs[mmu_io_psize].sllp;
 301         vmalloc_llp = mmu_psize_defs[mmu_vmalloc_psize].sllp;
 302         get_paca()->vmalloc_sllp = SLB_VSID_KERNEL | vmalloc_llp;
 303 #ifdef CONFIG_SPARSEMEM_VMEMMAP
 304         vmemmap_llp = mmu_psize_defs[mmu_vmemmap_psize].sllp;
 305 #endif
 306         if (!slb_encoding_inited) {
 307                 slb_encoding_inited = 1;
 308                 patch_slb_encoding(slb_miss_kernel_load_linear,
 309                                    SLB_VSID_KERNEL | linear_llp);
 310                 patch_slb_encoding(slb_miss_kernel_load_io,
 311                                    SLB_VSID_KERNEL | io_llp);
 312                 patch_slb_encoding(slb_compare_rr_to_size,
 313                                    mmu_slb_size);
 314
 315                 pr_devel("SLB: linear  LLP = %04lx\n", linear_llp);
 316                 pr_devel("SLB: io      LLP = %04lx\n", io_llp);
 317
 318 #ifdef CONFIG_SPARSEMEM_VMEMMAP
 319                 patch_slb_encoding(slb_miss_kernel_load_vmemmap,
 320                                    SLB_VSID_KERNEL | vmemmap_llp);
 321                 pr_devel("SLB: vmemmap LLP = %04lx\n", vmemmap_llp);
 322 #endif
 323         }
 324
 325         get_paca()->stab_rr = SLB_NUM_BOLTED;
 326
 327         lflags = SLB_VSID_KERNEL | linear_llp;
 328         vflags = SLB_VSID_KERNEL | vmalloc_llp;
 329
 330         /* Invalidate the entire SLB (even entry 0) & all the ERATS */
 331         asm volatile("isync":::"memory");
 332         asm volatile("slbmte  %0,%0"::"r" (0) : "memory");
 333         asm volatile("isync; slbia; isync":::"memory");
 334         create_shadowed_slbe(PAGE_OFFSET, mmu_kernel_ssize, lflags, LINEAR_INDEX);
 335         create_shadowed_slbe(VMALLOC_START, mmu_kernel_ssize, vflags, VMALLOC_INDEX);
 336
 337         /* For the boot cpu, we're running on the stack in init_thread_union,
 338          * which is in the first segment of the linear mapping, and also
 339          * get_paca()->kstack hasn't been initialized yet.
 340          * For secondary cpus, we need to bolt the kernel stack entry now.
 341          */
 342         slb_shadow_clear(KSTACK_INDEX);
 343         if (raw_smp_processor_id() != boot_cpuid &&
 344             (get_paca()->kstack & slb_esid_mask(mmu_kernel_ssize)) > PAGE_OFFSET)
 345                 create_shadowed_slbe(get_paca()->kstack,
 346                                      mmu_kernel_ssize, lflags, KSTACK_INDEX);
 347
 348         asm volatile("isync":::"memory");
 349 }