2 * This file contains low-level functions for performing various
3 * types of TLB invalidations on various processors with no hash
6 * This file implements the following functions for all no-hash
7 * processors. Some aren't implemented for some variants. Some
8 * are inline in tlbflush.h
13 * - tlbivax_bcast (not yet)
15 * Code mostly moved over from misc_32.S
17 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
19 * Partially rewritten by Cort Dougan (cort@cs.nmt.edu)
20 * Paul Mackerras, Kumar Gala and Benjamin Herrenschmidt.
22 * This program is free software; you can redistribute it and/or
23 * modify it under the terms of the GNU General Public License
24 * as published by the Free Software Foundation; either version
25 * 2 of the License, or (at your option) any later version.
31 #include <asm/cputable.h>
33 #include <asm/ppc_asm.h>
34 #include <asm/asm-offsets.h>
35 #include <asm/processor.h>
37 #if defined(CONFIG_40x)
40 * 40x implementation needs only tlbil_va
43 /* We run the search with interrupts disabled because we have to change
44 * the PID and I don't want to preempt when that happens.
55 /* There are only 64 TLB entries, so r3 < 64, which means bit 25 is
56 * clear. Since 25 is the V bit in the TLB_TAG, loading this value
57 * will invalidate the TLB entry. */
62 #elif defined(CONFIG_8xx)
65 * Nothing to do for 8xx, everything is inline
68 #elif defined(CONFIG_44x)
71 * 440 implementation uses tlbsx/we for tlbil_va and a full sweep
72 * of the TLB for everything else.
76 rlwimi r5,r4,0,24,31 /* Set TID */
78 /* We have to run the search with interrupts disabled, even critical
79 * and debug interrupts (in fact the only critical exceptions we have
80 * are debug and machine check). Otherwise an interrupt which causes
81 * a TLB miss can clobber the MMUCR between the mtspr and the tlbsx. */
83 lis r6,(MSR_EE|MSR_CE|MSR_ME|MSR_DE)@ha
84 addi r6,r6,(MSR_EE|MSR_CE|MSR_ME|MSR_DE)@l
92 /* There are only 64 TLB entries, so r3 < 64,
93 * which means bit 22, is clear. Since 22 is
94 * the V bit in the TLB_PAGEID, loading this
95 * value will invalidate the TLB entry.
97 tlbwe r3, r3, PPC44x_TLB_PAGEID
106 /* Load high watermark */
107 lis r4,tlb_44x_hwater@ha
108 lwz r5,tlb_44x_hwater@l(r4)
110 1: tlbwe r3,r3,PPC44x_TLB_PAGEID
118 #elif defined(CONFIG_FSL_BOOKE)
120 * FSL BookE implementations. Currently _pid and _all are the
121 * same. This will change when tlbilx is actually supported and
122 * performs invalidate-by-PID. This change will be driven by
123 * mmu_features conditional
127 * Flush MMU TLB on the local processor
131 #define MMUCSR0_TLBFI (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \
132 MMUCSR0_TLB2FI | MMUCSR0_TLB3FI)
133 li r3,(MMUCSR0_TLBFI)@l
134 mtspr SPRN_MMUCSR0, r3
136 mfspr r3,SPRN_MMUCSR0
137 andi. r3,r3,MMUCSR0_TLBFI@l
144 * Flush MMU TLB for a particular address, but only on the local processor
151 mtspr SPRN_MAS6,r4 /* assume AS=0 for now */
153 mfspr r4,SPRN_MAS1 /* check valid */
154 andis. r3,r4,MAS1_VALID@h
164 #error Unsupported processor type !