arch/powerpc/platforms/52xx/mpc52xx_pic.c

   1 /*
   2  *
   3  * Programmable Interrupt Controller functions for the Freescale MPC52xx.
   4  *
   5  * Copyright (C) 2008 Secret Lab Technologies Ltd.
   6  * Copyright (C) 2006 bplan GmbH
   7  * Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com>
   8  * Copyright (C) 2003 Montavista Software, Inc
   9  *
  10  * Based on the code from the 2.4 kernel by
  11  * Dale Farnsworth <dfarnsworth@mvista.com> and Kent Borg.
  12  *
  13  * This file is licensed under the terms of the GNU General Public License
  14  * version 2. This program is licensed "as is" without any warranty of any
  15  * kind, whether express or implied.
  16  *
  17  */
  18
  19 /*
  20  * This is the device driver for the MPC5200 interrupt controller.
  21  *
  22  * hardware overview
  23  * -----------------
  24  * The MPC5200 interrupt controller groups the all interrupt sources into
  25  * three groups called 'critical', 'main', and 'peripheral'.  The critical
  26  * group has 3 irqs, External IRQ0, slice timer 0 irq, and wake from deep
  27  * sleep.  Main group include the other 3 external IRQs, slice timer 1, RTC,
  28  * gpios, and the general purpose timers.  Peripheral group contains the
  29  * remaining irq sources from all of the on-chip peripherals (PSCs, Ethernet,
  30  * USB, DMA, etc).
  31  *
  32  * virqs
  33  * -----
  34  * The Linux IRQ subsystem requires that each irq source be assigned a
  35  * system wide unique IRQ number starting at 1 (0 means no irq).  Since
  36  * systems can have multiple interrupt controllers, the virtual IRQ (virq)
  37  * infrastructure lets each interrupt controller to define a local set
  38  * of IRQ numbers and the virq infrastructure maps those numbers into
  39  * a unique range of the global IRQ# space.
  40  *
  41  * To define a range of virq numbers for this controller, this driver first
  42  * assigns a number to each of the irq groups (called the level 1 or L1
  43  * value).  Within each group individual irq sources are also assigned a
  44  * number, as defined by the MPC5200 user guide, and refers to it as the
  45  * level 2 or L2 value.  The virq number is determined by shifting up the
  46  * L1 value by MPC52xx_IRQ_L1_OFFSET and ORing it with the L2 value.
  47  *
  48  * For example, the TMR0 interrupt is irq 9 in the main group.  The
  49  * virq for TMR0 is calculated by ((1 << MPC52xx_IRQ_L1_OFFSET) | 9).
  50  *
  51  * The observant reader will also notice that this driver defines a 4th
  52  * interrupt group called 'bestcomm'.  The bestcomm group isn't physically
  53  * part of the MPC5200 interrupt controller, but it is used here to assign
  54  * a separate virq number for each bestcomm task (since any of the 16
  55  * bestcomm tasks can cause the bestcomm interrupt to be raised).  When a
  56  * bestcomm interrupt occurs (peripheral group, irq 0) this driver determines
  57  * which task needs servicing and returns the irq number for that task.  This
  58  * allows drivers which use bestcomm to define their own interrupt handlers.
  59  *
  60  * irq_chip structures
  61  * -------------------
  62  * For actually manipulating IRQs (masking, enabling, clearing, etc) this
  63  * driver defines four separate 'irq_chip' structures, one for the main
  64  * group, one for the peripherals group, one for the bestcomm group and one
  65  * for external interrupts.  The irq_chip structures provide the hooks needed
  66  * to manipulate each IRQ source, and since each group is has a separate set
  67  * of registers for controlling the irq, it makes sense to divide up the
  68  * hooks along those lines.
  69  *
  70  * You'll notice that there is not an irq_chip for the critical group and
  71  * you'll also notice that there is an irq_chip defined for external
  72  * interrupts even though there is no external interrupt group.  The reason
  73  * for this is that the four external interrupts are all managed with the same
  74  * register even though one of the external IRQs is in the critical group and
  75  * the other three are in the main group.  For this reason it makes sense for
  76  * the 4 external irqs to be managed using a separate set of hooks.  The
  77  * reason there is no crit irq_chip is that of the 3 irqs in the critical
  78  * group, only external interrupt is actually support at this time by this
  79  * driver and since external interrupt is the only one used, it can just
  80  * be directed to make use of the external irq irq_chip.
  81  *
  82  * device tree bindings
  83  * --------------------
  84  * The device tree bindings for this controller reflect the two level
  85  * organization of irqs in the device.  #interrupt-cells = <3> where the
  86  * first cell is the group number [0..3], the second cell is the irq
  87  * number in the group, and the third cell is the sense type (level/edge).
  88  * For reference, the following is a list of the interrupt property values
  89  * associated with external interrupt sources on the MPC5200 (just because
  90  * it is non-obvious to determine what the interrupts property should be
  91  * when reading the mpc5200 manual and it is a frequently asked question).
  92  *
  93  * External interrupts:
  94  * <0 0 n>      external irq0, n is sense       (n=0: level high,
  95  * <1 1 n>      external irq1, n is sense        n=1: edge rising,
  96  * <1 2 n>      external irq2, n is sense        n=2: edge falling,
  97  * <1 3 n>      external irq3, n is sense        n=3: level low)
  98  */
  99 #undef DEBUG
 100
 101 #include <linux/interrupt.h>
 102 #include <linux/irq.h>
 103 #include <linux/of.h>
 104 #include <asm/io.h>
 105 #include <asm/prom.h>
 106 #include <asm/mpc52xx.h>
 107
 108 /* HW IRQ mapping */
 109 #define MPC52xx_IRQ_L1_CRIT     (0)
 110 #define MPC52xx_IRQ_L1_MAIN     (1)
 111 #define MPC52xx_IRQ_L1_PERP     (2)
 112 #define MPC52xx_IRQ_L1_SDMA     (3)
 113
 114 #define MPC52xx_IRQ_L1_OFFSET   (6)
 115 #define MPC52xx_IRQ_L1_MASK     (0x00c0)
 116 #define MPC52xx_IRQ_L2_MASK     (0x003f)
 117
 118 #define MPC52xx_IRQ_HIGHTESTHWIRQ (0xd0)
 119
 120
 121 /* MPC5200 device tree match tables */
 122 static struct of_device_id mpc52xx_pic_ids[] __initdata = {
 123         { .compatible = "fsl,mpc5200-pic", },
 124         { .compatible = "mpc5200-pic", },
 125         {}
 126 };
 127 static struct of_device_id mpc52xx_sdma_ids[] __initdata = {
 128         { .compatible = "fsl,mpc5200-bestcomm", },
 129         { .compatible = "mpc5200-bestcomm", },
 130         {}
 131 };
 132
 133 static struct mpc52xx_intr __iomem *intr;
 134 static struct mpc52xx_sdma __iomem *sdma;
 135 static struct irq_host *mpc52xx_irqhost = NULL;
 136
 137 static unsigned char mpc52xx_map_senses[4] = {
 138         IRQ_TYPE_LEVEL_HIGH,
 139         IRQ_TYPE_EDGE_RISING,
 140         IRQ_TYPE_EDGE_FALLING,
 141         IRQ_TYPE_LEVEL_LOW,
 142 };
 143
 144 /* Utility functions */
 145 static inline void io_be_setbit(u32 __iomem *addr, int bitno)
 146 {
 147         out_be32(addr, in_be32(addr) | (1 << bitno));
 148 }
 149
 150 static inline void io_be_clrbit(u32 __iomem *addr, int bitno)
 151 {
 152         out_be32(addr, in_be32(addr) & ~(1 << bitno));
 153 }
 154
 155 /*
 156  * IRQ[0-3] interrupt irq_chip
 157  */
 158 static void mpc52xx_extirq_mask(unsigned int virq)
 159 {
 160         int irq;
 161         int l2irq;
 162
 163         irq = irq_map[virq].hwirq;
 164         l2irq = irq & MPC52xx_IRQ_L2_MASK;
 165
 166         io_be_clrbit(&intr->ctrl, 11 - l2irq);
 167 }
 168
 169 static void mpc52xx_extirq_unmask(unsigned int virq)
 170 {
 171         int irq;
 172         int l2irq;
 173
 174         irq = irq_map[virq].hwirq;
 175         l2irq = irq & MPC52xx_IRQ_L2_MASK;
 176
 177         io_be_setbit(&intr->ctrl, 11 - l2irq);
 178 }
 179
 180 static void mpc52xx_extirq_ack(unsigned int virq)
 181 {
 182         int irq;
 183         int l2irq;
 184
 185         irq = irq_map[virq].hwirq;
 186         l2irq = irq & MPC52xx_IRQ_L2_MASK;
 187
 188         io_be_setbit(&intr->ctrl, 27-l2irq);
 189 }
 190
 191 static int mpc52xx_extirq_set_type(unsigned int virq, unsigned int flow_type)
 192 {
 193         struct irq_desc *desc = get_irq_desc(virq);
 194         u32 ctrl_reg, type;
 195         int irq;
 196         int l2irq;
 197
 198         irq = irq_map[virq].hwirq;
 199         l2irq = irq & MPC52xx_IRQ_L2_MASK;
 200
 201         pr_debug("%s: irq=%x. l2=%d flow_type=%d\n", __func__, irq, l2irq, flow_type);
 202
 203         switch (flow_type) {
 204         case IRQF_TRIGGER_HIGH:
 205                 type = 0;
 206                 break;
 207         case IRQF_TRIGGER_RISING:
 208                 type = 1;
 209                 break;
 210         case IRQF_TRIGGER_FALLING:
 211                 type = 2;
 212                 break;
 213         case IRQF_TRIGGER_LOW:
 214                 type = 3;
 215                 break;
 216         default:
 217                 type = 0;
 218         }
 219
 220         desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
 221         desc->status |= flow_type & IRQ_TYPE_SENSE_MASK;
 222         if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
 223                 desc->status |= IRQ_LEVEL;
 224
 225         ctrl_reg = in_be32(&intr->ctrl);
 226         ctrl_reg &= ~(0x3 << (22 - (l2irq * 2)));
 227         ctrl_reg |= (type << (22 - (l2irq * 2)));
 228         out_be32(&intr->ctrl, ctrl_reg);
 229
 230         return 0;
 231 }
 232
 233 static struct irq_chip mpc52xx_extirq_irqchip = {
 234         .typename = "MPC52xx External",
 235         .mask = mpc52xx_extirq_mask,
 236         .unmask = mpc52xx_extirq_unmask,
 237         .ack = mpc52xx_extirq_ack,
 238         .set_type = mpc52xx_extirq_set_type,
 239 };
 240
 241 /*
 242  * Main interrupt irq_chip
 243  */
 244 static void mpc52xx_main_mask(unsigned int virq)
 245 {
 246         int irq;
 247         int l2irq;
 248
 249         irq = irq_map[virq].hwirq;
 250         l2irq = irq & MPC52xx_IRQ_L2_MASK;
 251
 252         io_be_setbit(&intr->main_mask, 16 - l2irq);
 253 }
 254
 255 static void mpc52xx_main_unmask(unsigned int virq)
 256 {
 257         int irq;
 258         int l2irq;
 259
 260         irq = irq_map[virq].hwirq;
 261         l2irq = irq & MPC52xx_IRQ_L2_MASK;
 262
 263         io_be_clrbit(&intr->main_mask, 16 - l2irq);
 264 }
 265
 266 static struct irq_chip mpc52xx_main_irqchip = {
 267         .typename = "MPC52xx Main",
 268         .mask = mpc52xx_main_mask,
 269         .mask_ack = mpc52xx_main_mask,
 270         .unmask = mpc52xx_main_unmask,
 271 };
 272
 273 /*
 274  * Peripherals interrupt irq_chip
 275  */
 276 static void mpc52xx_periph_mask(unsigned int virq)
 277 {
 278         int irq;
 279         int l2irq;
 280
 281         irq = irq_map[virq].hwirq;
 282         l2irq = irq & MPC52xx_IRQ_L2_MASK;
 283
 284         io_be_setbit(&intr->per_mask, 31 - l2irq);
 285 }
 286
 287 static void mpc52xx_periph_unmask(unsigned int virq)
 288 {
 289         int irq;
 290         int l2irq;
 291
 292         irq = irq_map[virq].hwirq;
 293         l2irq = irq & MPC52xx_IRQ_L2_MASK;
 294
 295         io_be_clrbit(&intr->per_mask, 31 - l2irq);
 296 }
 297
 298 static struct irq_chip mpc52xx_periph_irqchip = {
 299         .typename = "MPC52xx Peripherals",
 300         .mask = mpc52xx_periph_mask,
 301         .mask_ack = mpc52xx_periph_mask,
 302         .unmask = mpc52xx_periph_unmask,
 303 };
 304
 305 /*
 306  * SDMA interrupt irq_chip
 307  */
 308 static void mpc52xx_sdma_mask(unsigned int virq)
 309 {
 310         int irq;
 311         int l2irq;
 312
 313         irq = irq_map[virq].hwirq;
 314         l2irq = irq & MPC52xx_IRQ_L2_MASK;
 315
 316         io_be_setbit(&sdma->IntMask, l2irq);
 317 }
 318
 319 static void mpc52xx_sdma_unmask(unsigned int virq)
 320 {
 321         int irq;
 322         int l2irq;
 323
 324         irq = irq_map[virq].hwirq;
 325         l2irq = irq & MPC52xx_IRQ_L2_MASK;
 326
 327         io_be_clrbit(&sdma->IntMask, l2irq);
 328 }
 329
 330 static void mpc52xx_sdma_ack(unsigned int virq)
 331 {
 332         int irq;
 333         int l2irq;
 334
 335         irq = irq_map[virq].hwirq;
 336         l2irq = irq & MPC52xx_IRQ_L2_MASK;
 337
 338         out_be32(&sdma->IntPend, 1 << l2irq);
 339 }
 340
 341 static struct irq_chip mpc52xx_sdma_irqchip = {
 342         .typename = "MPC52xx SDMA",
 343         .mask = mpc52xx_sdma_mask,
 344         .unmask = mpc52xx_sdma_unmask,
 345         .ack = mpc52xx_sdma_ack,
 346 };
 347
 348 /**
 349  * mpc52xx_irqhost_xlate - translate virq# from device tree interrupts property
 350  */
 351 static int mpc52xx_irqhost_xlate(struct irq_host *h, struct device_node *ct,
 352                                  u32 *intspec, unsigned int intsize,
 353                                  irq_hw_number_t *out_hwirq,
 354                                  unsigned int *out_flags)
 355 {
 356         int intrvect_l1;
 357         int intrvect_l2;
 358         int intrvect_type;
 359         int intrvect_linux;
 360
 361         if (intsize != 3)
 362                 return -1;
 363
 364         intrvect_l1 = (int)intspec[0];
 365         intrvect_l2 = (int)intspec[1];
 366         intrvect_type = (int)intspec[2];
 367
 368         intrvect_linux = (intrvect_l1 << MPC52xx_IRQ_L1_OFFSET) &
 369                          MPC52xx_IRQ_L1_MASK;
 370         intrvect_linux |= intrvect_l2 & MPC52xx_IRQ_L2_MASK;
 371
 372         pr_debug("return %x, l1=%d, l2=%d\n", intrvect_linux, intrvect_l1,
 373                  intrvect_l2);
 374
 375         *out_hwirq = intrvect_linux;
 376         *out_flags = mpc52xx_map_senses[intrvect_type];
 377
 378         return 0;
 379 }
 380
 381 /**
 382  * mpc52xx_irqx_gettype - determine the IRQ sense type (level/edge)
 383  *
 384  * Only external IRQs need this.
 385  */
 386 static int mpc52xx_irqx_gettype(int irq)
 387 {
 388         int type;
 389         u32 ctrl_reg;
 390
 391         ctrl_reg = in_be32(&intr->ctrl);
 392         type = (ctrl_reg >> (22 - irq * 2)) & 0x3;
 393
 394         return mpc52xx_map_senses[type];
 395 }
 396
 397 /**
 398  * mpc52xx_irqhost_map - Hook to map from virq to an irq_chip structure
 399  */
 400 static int mpc52xx_irqhost_map(struct irq_host *h, unsigned int virq,
 401                                irq_hw_number_t irq)
 402 {
 403         int l1irq;
 404         int l2irq;
 405         struct irq_chip *good_irqchip;
 406         void *good_handle;
 407         int type;
 408
 409         l1irq = (irq & MPC52xx_IRQ_L1_MASK) >> MPC52xx_IRQ_L1_OFFSET;
 410         l2irq = irq & MPC52xx_IRQ_L2_MASK;
 411
 412         /*
 413          * Most of ours IRQs will be level low
 414          * Only external IRQs on some platform may be others
 415          */
 416         type = IRQ_TYPE_LEVEL_LOW;
 417
 418         switch (l1irq) {
 419         case MPC52xx_IRQ_L1_CRIT:
 420                 pr_debug("%s: Critical. l2=%x\n", __func__, l2irq);
 421
 422                 BUG_ON(l2irq != 0);
 423
 424                 type = mpc52xx_irqx_gettype(l2irq);
 425                 good_irqchip = &mpc52xx_extirq_irqchip;
 426                 break;
 427
 428         case MPC52xx_IRQ_L1_MAIN:
 429                 pr_debug("%s: Main IRQ[1-3] l2=%x\n", __func__, l2irq);
 430
 431                 if ((l2irq >= 1) && (l2irq <= 3)) {
 432                         type = mpc52xx_irqx_gettype(l2irq);
 433                         good_irqchip = &mpc52xx_extirq_irqchip;
 434                 } else {
 435                         good_irqchip = &mpc52xx_main_irqchip;
 436                 }
 437                 break;
 438
 439         case MPC52xx_IRQ_L1_PERP:
 440                 pr_debug("%s: Peripherals. l2=%x\n", __func__, l2irq);
 441                 good_irqchip = &mpc52xx_periph_irqchip;
 442                 break;
 443
 444         case MPC52xx_IRQ_L1_SDMA:
 445                 pr_debug("%s: SDMA. l2=%x\n", __func__, l2irq);
 446                 good_irqchip = &mpc52xx_sdma_irqchip;
 447                 break;
 448
 449         default:
 450                 pr_err("%s: invalid virq requested (0x%x)\n", __func__, virq);
 451                 return -EINVAL;
 452         }
 453
 454         switch (type) {
 455         case IRQ_TYPE_EDGE_FALLING:
 456         case IRQ_TYPE_EDGE_RISING:
 457                 good_handle = handle_edge_irq;
 458                 break;
 459         default:
 460                 good_handle = handle_level_irq;
 461         }
 462
 463         set_irq_chip_and_handler(virq, good_irqchip, good_handle);
 464
 465         pr_debug("%s: virq=%x, hw=%x. type=%x\n", __func__, virq,
 466                  (int)irq, type);
 467
 468         return 0;
 469 }
 470
 471 static struct irq_host_ops mpc52xx_irqhost_ops = {
 472         .xlate = mpc52xx_irqhost_xlate,
 473         .map = mpc52xx_irqhost_map,
 474 };
 475
 476 /**
 477  * mpc52xx_init_irq - Initialize and register with the virq subsystem
 478  *
 479  * Hook for setting up IRQs on an mpc5200 system.  A pointer to this function
 480  * is to be put into the machine definition structure.
 481  *
 482  * This function searches the device tree for an MPC5200 interrupt controller,
 483  * initializes it, and registers it with the virq subsystem.
 484  */
 485 void __init mpc52xx_init_irq(void)
 486 {
 487         u32 intr_ctrl;
 488         struct device_node *picnode;
 489         struct device_node *np;
 490
 491         /* Remap the necessary zones */
 492         picnode = of_find_matching_node(NULL, mpc52xx_pic_ids);
 493         intr = of_iomap(picnode, 0);
 494         if (!intr)
 495                 panic(__FILE__  ": find_and_map failed on 'mpc5200-pic'. "
 496                                 "Check node !");
 497
 498         np = of_find_matching_node(NULL, mpc52xx_sdma_ids);
 499         sdma = of_iomap(np, 0);
 500         of_node_put(np);
 501         if (!sdma)
 502                 panic(__FILE__  ": find_and_map failed on 'mpc5200-bestcomm'. "
 503                                 "Check node !");
 504
 505         /* Disable all interrupt sources. */
 506         out_be32(&sdma->IntPend, 0xffffffff);   /* 1 means clear pending */
 507         out_be32(&sdma->IntMask, 0xffffffff);   /* 1 means disabled */
 508         out_be32(&intr->per_mask, 0x7ffffc00);  /* 1 means disabled */
 509         out_be32(&intr->main_mask, 0x00010fff); /* 1 means disabled */
 510         intr_ctrl = in_be32(&intr->ctrl);
 511         intr_ctrl &= 0x00ff0000;        /* Keeps IRQ[0-3] config */
 512         intr_ctrl |=    0x0f000000 |    /* clear IRQ 0-3 */
 513                         0x00001000 |    /* MEE master external enable */
 514                         0x00000000 |    /* 0 means disable IRQ 0-3 */
 515                         0x00000001;     /* CEb route critical normally */
 516         out_be32(&intr->ctrl, intr_ctrl);
 517
 518         /* Zero a bunch of the priority settings. */
 519         out_be32(&intr->per_pri1, 0);
 520         out_be32(&intr->per_pri2, 0);
 521         out_be32(&intr->per_pri3, 0);
 522         out_be32(&intr->main_pri1, 0);
 523         out_be32(&intr->main_pri2, 0);
 524
 525         /*
 526          * As last step, add an irq host to translate the real
 527          * hw irq information provided by the ofw to linux virq
 528          */
 529         mpc52xx_irqhost = irq_alloc_host(picnode, IRQ_HOST_MAP_LINEAR,
 530                                          MPC52xx_IRQ_HIGHTESTHWIRQ,
 531                                          &mpc52xx_irqhost_ops, -1);
 532
 533         if (!mpc52xx_irqhost)
 534                 panic(__FILE__ ": Cannot allocate the IRQ host\n");
 535
 536         irq_set_default_host(mpc52xx_irqhost);
 537
 538         pr_info("MPC52xx PIC is up and running!\n");
 539 }
 540
 541 /**
 542  * mpc52xx_get_irq - Get pending interrupt number hook function
 543  *
 544  * Called by the interupt handler to determine what IRQ handler needs to be
 545  * executed.
 546  *
 547  * Status of pending interrupts is determined by reading the encoded status
 548  * register.  The encoded status register has three fields; one for each of the
 549  * types of interrupts defined by the controller - 'critical', 'main' and
 550  * 'peripheral'.  This function reads the status register and returns the IRQ
 551  * number associated with the highest priority pending interrupt.  'Critical'
 552  * interrupts have the highest priority, followed by 'main' interrupts, and
 553  * then 'peripheral'.
 554  *
 555  * The mpc5200 interrupt controller can be configured to boost the priority
 556  * of individual 'peripheral' interrupts.  If this is the case then a special
 557  * value will appear in either the crit or main fields indicating a high
 558  * or medium priority peripheral irq has occurred.
 559  *
 560  * This function checks each of the 3 irq request fields and returns the
 561  * first pending interrupt that it finds.
 562  *
 563  * This function also identifies a 4th type of interrupt; 'bestcomm'.  Each
 564  * bestcomm DMA task can raise the bestcomm peripheral interrupt.  When this
 565  * occurs at task-specific IRQ# is decoded so that each task can have its
 566  * own IRQ handler.
 567  */
 568 unsigned int mpc52xx_get_irq(void)
 569 {
 570         u32 status;
 571         int irq = NO_IRQ_IGNORE;
 572
 573         status = in_be32(&intr->enc_status);
 574         if (status & 0x00000400) {      /* critical */
 575                 irq = (status >> 8) & 0x3;
 576                 if (irq == 2)   /* high priority peripheral */
 577                         goto peripheral;
 578                 irq |= (MPC52xx_IRQ_L1_CRIT << MPC52xx_IRQ_L1_OFFSET);
 579         } else if (status & 0x00200000) {       /* main */
 580                 irq = (status >> 16) & 0x1f;
 581                 if (irq == 4)   /* low priority peripheral */
 582                         goto peripheral;
 583                 irq |= (MPC52xx_IRQ_L1_MAIN << MPC52xx_IRQ_L1_OFFSET);
 584         } else if (status & 0x20000000) {       /* peripheral */
 585               peripheral:
 586                 irq = (status >> 24) & 0x1f;
 587                 if (irq == 0) { /* bestcomm */
 588                         status = in_be32(&sdma->IntPend);
 589                         irq = ffs(status) - 1;
 590                         irq |= (MPC52xx_IRQ_L1_SDMA << MPC52xx_IRQ_L1_OFFSET);
 591                 } else {
 592                         irq |= (MPC52xx_IRQ_L1_PERP << MPC52xx_IRQ_L1_OFFSET);
 593                 }
 594         }
 595
 596         return irq_linear_revmap(mpc52xx_irqhost, irq);
 597 }