2 * Based on MPC8560 ADS and arch/ppc stx_gp3 ports
4 * Maintained by Kumar Gala (see MAINTAINERS for contact information)
6 * Copyright 2008 Freescale Semiconductor Inc.
8 * Dan Malek <dan@embeddededge.com>
9 * Copyright 2004 Embedded Edge, LLC
11 * Copied from mpc8560_ads.c
12 * Copyright 2002, 2003 Motorola Inc.
14 * Ported to 2.6, Matt Porter <mporter@kernel.crashing.org>
15 * Copyright 2004-2005 MontaVista Software, Inc.
17 * This program is free software; you can redistribute it and/or modify it
18 * under the terms of the GNU General Public License as published by the
19 * Free Software Foundation; either version 2 of the License, or (at your
20 * option) any later version.
23 #include <linux/stddef.h>
24 #include <linux/kernel.h>
25 #include <linux/pci.h>
26 #include <linux/kdev_t.h>
27 #include <linux/delay.h>
28 #include <linux/seq_file.h>
29 #include <linux/of_platform.h>
31 #include <asm/system.h>
33 #include <asm/machdep.h>
34 #include <asm/pci-bridge.h>
37 #include <mm/mmu_decl.h>
40 #include <sysdev/fsl_soc.h>
41 #include <sysdev/fsl_pci.h>
47 #endif /* CONFIG_CPM2 */
49 static void __init
stx_gp3_pic_init(void)
53 struct device_node
*np
;
55 np
= of_find_node_by_type(NULL
, "open-pic");
57 printk(KERN_ERR
"Could not find open-pic node\n");
61 if (of_address_to_resource(np
, 0, &r
)) {
62 printk(KERN_ERR
"Could not map mpic register space\n");
67 mpic
= mpic_alloc(np
, r
.start
,
68 MPIC_PRIMARY
| MPIC_WANTS_RESET
| MPIC_BIG_ENDIAN
,
75 mpc85xx_cpm2_pic_init();
79 * Setup the architecture
81 static void __init
stx_gp3_setup_arch(void)
84 struct device_node
*np
;
88 ppc_md
.progress("stx_gp3_setup_arch()", 0);
95 for_each_compatible_node(np
, "pci", "fsl,mpc8540-pci")
96 fsl_add_bridge(np
, 1);
100 static void stx_gp3_show_cpuinfo(struct seq_file
*m
)
102 uint pvid
, svid
, phid1
;
104 pvid
= mfspr(SPRN_PVR
);
105 svid
= mfspr(SPRN_SVR
);
107 seq_printf(m
, "Vendor\t\t: RPC Electronics STx\n");
108 seq_printf(m
, "PVR\t\t: 0x%x\n", pvid
);
109 seq_printf(m
, "SVR\t\t: 0x%x\n", svid
);
111 /* Display cpu Pll setting */
112 phid1
= mfspr(SPRN_HID1
);
113 seq_printf(m
, "PLL setting\t: 0x%x\n", ((phid1
>> 24) & 0x3f));
116 machine_device_initcall(stx_gp3
, mpc85xx_common_publish_devices
);
119 * Called very early, device-tree isn't unflattened
121 static int __init
stx_gp3_probe(void)
123 unsigned long root
= of_get_flat_dt_root();
125 return of_flat_dt_is_compatible(root
, "stx,gp3-8560");
128 define_machine(stx_gp3
) {
130 .probe
= stx_gp3_probe
,
131 .setup_arch
= stx_gp3_setup_arch
,
132 .init_IRQ
= stx_gp3_pic_init
,
133 .show_cpuinfo
= stx_gp3_show_cpuinfo
,
134 .get_irq
= mpic_get_irq
,
135 .restart
= fsl_rstcr_restart
,
136 .calibrate_decr
= generic_calibrate_decr
,
137 .progress
= udbg_progress
,