arch/powerpc/platforms/86xx/gef_ppc9a.c

   1 /*
   2  * GE Fanuc PPC9A board support
   3  *
   4  * Author: Martyn Welch <martyn.welch@gefanuc.com>
   5  *
   6  * Copyright 2008 GE Fanuc Intelligent Platforms Embedded Systems, Inc.
   7  *
   8  * This program is free software; you can redistribute  it and/or modify it
   9  * under  the terms of  the GNU General  Public License as published by the
  10  * Free Software Foundation;  either version 2 of the  License, or (at your
  11  * option) any later version.
  12  *
  13  * Based on: mpc86xx_hpcn.c (MPC86xx HPCN board specific routines)
  14  * Copyright 2006 Freescale Semiconductor Inc.
  15  *
  16  * NEC fixup adapted from arch/mips/pci/fixup-lm2e.c
  17  */
  18
  19 #include <linux/stddef.h>
  20 #include <linux/kernel.h>
  21 #include <linux/pci.h>
  22 #include <linux/kdev_t.h>
  23 #include <linux/delay.h>
  24 #include <linux/seq_file.h>
  25 #include <linux/of_platform.h>
  26
  27 #include <asm/system.h>
  28 #include <asm/time.h>
  29 #include <asm/machdep.h>
  30 #include <asm/pci-bridge.h>
  31 #include <asm/mpc86xx.h>
  32 #include <asm/prom.h>
  33 #include <mm/mmu_decl.h>
  34 #include <asm/udbg.h>
  35
  36 #include <asm/mpic.h>
  37
  38 #include <sysdev/fsl_pci.h>
  39 #include <sysdev/fsl_soc.h>
  40
  41 #include "mpc86xx.h"
  42 #include "gef_pic.h"
  43
  44 #undef DEBUG
  45
  46 #ifdef DEBUG
  47 #define DBG (fmt...) do { printk(KERN_ERR "PPC9A: " fmt); } while (0)
  48 #else
  49 #define DBG (fmt...) do { } while (0)
  50 #endif
  51
  52 void __iomem *ppc9a_regs;
  53
  54 static void __init gef_ppc9a_init_irq(void)
  55 {
  56         struct device_node *cascade_node = NULL;
  57
  58         mpc86xx_init_irq();
  59
  60         /*
  61          * There is a simple interrupt handler in the main FPGA, this needs
  62          * to be cascaded into the MPIC
  63          */
  64         cascade_node = of_find_compatible_node(NULL, NULL, "gef,fpga-pic-1.00");
  65         if (!cascade_node) {
  66                 printk(KERN_WARNING "PPC9A: No FPGA PIC\n");
  67                 return;
  68         }
  69
  70         gef_pic_init(cascade_node);
  71         of_node_put(cascade_node);
  72 }
  73
  74 static void __init gef_ppc9a_setup_arch(void)
  75 {
  76         struct device_node *regs;
  77 #ifdef CONFIG_PCI
  78         struct device_node *np;
  79
  80         for_each_compatible_node(np, "pci", "fsl,mpc8641-pcie") {
  81                 fsl_add_bridge(np, 1);
  82         }
  83 #endif
  84
  85         printk(KERN_INFO "GE Fanuc Intelligent Platforms PPC9A 6U VME SBC\n");
  86
  87 #ifdef CONFIG_SMP
  88         mpc86xx_smp_init();
  89 #endif
  90
  91         /* Remap basic board registers */
  92         regs = of_find_compatible_node(NULL, NULL, "gef,ppc9a-fpga-regs");
  93         if (regs) {
  94                 ppc9a_regs = of_iomap(regs, 0);
  95                 if (ppc9a_regs == NULL)
  96                         printk(KERN_WARNING "Unable to map board registers\n");
  97                 of_node_put(regs);
  98         }
  99 }
 100
 101 /* Return the PCB revision */
 102 static unsigned int gef_ppc9a_get_pcb_rev(void)
 103 {
 104         unsigned int reg;
 105
 106         reg = ioread32(ppc9a_regs);
 107         return (reg >> 8) & 0xff;
 108 }
 109
 110 /* Return the board (software) revision */
 111 static unsigned int gef_ppc9a_get_board_rev(void)
 112 {
 113         unsigned int reg;
 114
 115         reg = ioread32(ppc9a_regs);
 116         return (reg >> 16) & 0xff;
 117 }
 118
 119 /* Return the FPGA revision */
 120 static unsigned int gef_ppc9a_get_fpga_rev(void)
 121 {
 122         unsigned int reg;
 123
 124         reg = ioread32(ppc9a_regs);
 125         return (reg >> 24) & 0xf;
 126 }
 127
 128 static void gef_ppc9a_show_cpuinfo(struct seq_file *m)
 129 {
 130         uint svid = mfspr(SPRN_SVR);
 131
 132         seq_printf(m, "Vendor\t\t: GE Fanuc Intelligent Platforms\n");
 133
 134         seq_printf(m, "Revision\t: %u%c\n", gef_ppc9a_get_pcb_rev(),
 135                 ('A' + gef_ppc9a_get_board_rev() - 1));
 136         seq_printf(m, "FPGA Revision\t: %u\n", gef_ppc9a_get_fpga_rev());
 137
 138         seq_printf(m, "SVR\t\t: 0x%x\n", svid);
 139 }
 140
 141 static void __init gef_ppc9a_nec_fixup(struct pci_dev *pdev)
 142 {
 143         unsigned int val;
 144
 145         /* Do not do the fixup on other platforms! */
 146         if (!machine_is(gef_ppc9a))
 147                 return;
 148
 149         printk(KERN_INFO "Running NEC uPD720101 Fixup\n");
 150
 151         /* Ensure ports 1, 2, 3, 4 & 5 are enabled */
 152         pci_read_config_dword(pdev, 0xe0, &val);
 153         pci_write_config_dword(pdev, 0xe0, (val & ~7) | 0x5);
 154
 155         /* System clock is 48-MHz Oscillator and EHCI Enabled. */
 156         pci_write_config_dword(pdev, 0xe4, 1 << 5);
 157 }
 158 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_USB,
 159         gef_ppc9a_nec_fixup);
 160
 161 /*
 162  * Called very early, device-tree isn't unflattened
 163  *
 164  * This function is called to determine whether the BSP is compatible with the
 165  * supplied device-tree, which is assumed to be the correct one for the actual
 166  * board. It is expected thati, in the future, a kernel may support multiple
 167  * boards.
 168  */
 169 static int __init gef_ppc9a_probe(void)
 170 {
 171         unsigned long root = of_get_flat_dt_root();
 172
 173         if (of_flat_dt_is_compatible(root, "gef,ppc9a"))
 174                 return 1;
 175
 176         return 0;
 177 }
 178
 179 static long __init mpc86xx_time_init(void)
 180 {
 181         unsigned int temp;
 182
 183         /* Set the time base to zero */
 184         mtspr(SPRN_TBWL, 0);
 185         mtspr(SPRN_TBWU, 0);
 186
 187         temp = mfspr(SPRN_HID0);
 188         temp |= HID0_TBEN;
 189         mtspr(SPRN_HID0, temp);
 190         asm volatile("isync");
 191
 192         return 0;
 193 }
 194
 195 static __initdata struct of_device_id of_bus_ids[] = {
 196         { .compatible = "simple-bus", },
 197         { .compatible = "gianfar", },
 198         {},
 199 };
 200
 201 static int __init declare_of_platform_devices(void)
 202 {
 203         printk(KERN_DEBUG "Probe platform devices\n");
 204         of_platform_bus_probe(NULL, of_bus_ids, NULL);
 205
 206         return 0;
 207 }
 208 machine_device_initcall(gef_ppc9a, declare_of_platform_devices);
 209
 210 define_machine(gef_ppc9a) {
 211         .name                   = "GE Fanuc PPC9A",
 212         .probe                  = gef_ppc9a_probe,
 213         .setup_arch             = gef_ppc9a_setup_arch,
 214         .init_IRQ               = gef_ppc9a_init_irq,
 215         .show_cpuinfo           = gef_ppc9a_show_cpuinfo,
 216         .get_irq                = mpic_get_irq,
 217         .restart                = fsl_rstcr_restart,
 218         .time_init              = mpc86xx_time_init,
 219         .calibrate_decr         = generic_calibrate_decr,
 220         .progress               = udbg_progress,
 221 #ifdef CONFIG_PCI
 222         .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
 223 #endif
 224 };