arch/powerpc/platforms/86xx/mpc8610_hpcd.c

   1 /*
   2  * MPC8610 HPCD board specific routines
   3  *
   4  * Initial author: Xianghua Xiao <x.xiao@freescale.com>
   5  * Recode: Jason Jin <jason.jin@freescale.com>
   6  *         York Sun <yorksun@freescale.com>
   7  *
   8  * Rewrite the interrupt routing. remove the 8259PIC support,
   9  * All the integrated device in ULI use sideband interrupt.
  10  *
  11  * Copyright 2008 Freescale Semiconductor Inc.
  12  *
  13  * This program is free software; you can redistribute  it and/or modify it
  14  * under  the terms of  the GNU General  Public License as published by the
  15  * Free Software Foundation;  either version 2 of the  License, or (at your
  16  * option) any later version.
  17  */
  18
  19 #include <linux/stddef.h>
  20 #include <linux/kernel.h>
  21 #include <linux/pci.h>
  22 #include <linux/kdev_t.h>
  23 #include <linux/delay.h>
  24 #include <linux/seq_file.h>
  25 #include <linux/of.h>
  26
  27 #include <asm/system.h>
  28 #include <asm/time.h>
  29 #include <asm/machdep.h>
  30 #include <asm/pci-bridge.h>
  31 #include <asm/mpc86xx.h>
  32 #include <asm/prom.h>
  33 #include <mm/mmu_decl.h>
  34 #include <asm/udbg.h>
  35
  36 #include <asm/mpic.h>
  37
  38 #include <linux/of_platform.h>
  39 #include <sysdev/fsl_pci.h>
  40 #include <sysdev/fsl_soc.h>
  41
  42 #include "mpc86xx.h"
  43
  44 static unsigned char *pixis_bdcfg0, *pixis_arch;
  45
  46 static struct of_device_id __initdata mpc8610_ids[] = {
  47         { .compatible = "fsl,mpc8610-immr", },
  48         { .compatible = "simple-bus", },
  49         { .compatible = "gianfar", },
  50         {}
  51 };
  52
  53 static int __init mpc8610_declare_of_platform_devices(void)
  54 {
  55         /* Without this call, the SSI device driver won't get probed. */
  56         of_platform_bus_probe(NULL, mpc8610_ids, NULL);
  57
  58         return 0;
  59 }
  60 machine_device_initcall(mpc86xx_hpcd, mpc8610_declare_of_platform_devices);
  61
  62 #if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
  63
  64 static u32 get_busfreq(void)
  65 {
  66         struct device_node *node;
  67
  68         u32 fs_busfreq = 0;
  69         node = of_find_node_by_type(NULL, "cpu");
  70         if (node) {
  71                 unsigned int size;
  72                 const unsigned int *prop =
  73                         of_get_property(node, "bus-frequency", &size);
  74                 if (prop)
  75                         fs_busfreq = *prop;
  76                 of_node_put(node);
  77         };
  78         return fs_busfreq;
  79 }
  80
  81 unsigned int mpc8610hpcd_get_pixel_format(unsigned int bits_per_pixel,
  82                                                 int monitor_port)
  83 {
  84         static const unsigned long pixelformat[][3] = {
  85                 {0x88882317, 0x88083218, 0x65052119},
  86                 {0x88883316, 0x88082219, 0x65053118},
  87         };
  88         unsigned int pix_fmt, arch_monitor;
  89
  90         arch_monitor = ((*pixis_arch == 0x01) && (monitor_port == 0))? 0 : 1;
  91                 /* DVI port for board version 0x01 */
  92
  93         if (bits_per_pixel == 32)
  94                 pix_fmt = pixelformat[arch_monitor][0];
  95         else if (bits_per_pixel == 24)
  96                 pix_fmt = pixelformat[arch_monitor][1];
  97         else if (bits_per_pixel == 16)
  98                 pix_fmt = pixelformat[arch_monitor][2];
  99         else
 100                 pix_fmt = pixelformat[1][0];
 101
 102         return pix_fmt;
 103 }
 104
 105 void mpc8610hpcd_set_gamma_table(int monitor_port, char *gamma_table_base)
 106 {
 107         int i;
 108         if (monitor_port == 2) {                /* dual link LVDS */
 109                 for (i = 0; i < 256*3; i++)
 110                         gamma_table_base[i] = (gamma_table_base[i] << 2) |
 111                                          ((gamma_table_base[i] >> 6) & 0x03);
 112         }
 113 }
 114
 115 #define PX_BRDCFG0_DVISEL       (1 << 3)
 116 #define PX_BRDCFG0_DLINK        (1 << 4)
 117 #define PX_BRDCFG0_DIU_MASK     (PX_BRDCFG0_DVISEL | PX_BRDCFG0_DLINK)
 118
 119 void mpc8610hpcd_set_monitor_port(int monitor_port)
 120 {
 121         static const u8 bdcfg[] = {
 122                 PX_BRDCFG0_DVISEL | PX_BRDCFG0_DLINK,
 123                 PX_BRDCFG0_DLINK,
 124                 0,
 125         };
 126
 127         if (monitor_port < 3)
 128                 clrsetbits_8(pixis_bdcfg0, PX_BRDCFG0_DIU_MASK,
 129                              bdcfg[monitor_port]);
 130 }
 131
 132 void mpc8610hpcd_set_pixel_clock(unsigned int pixclock)
 133 {
 134         u32 __iomem *clkdvdr;
 135         u32 temp;
 136         /* variables for pixel clock calcs */
 137         ulong  bestval, bestfreq, speed_ccb, minpixclock, maxpixclock;
 138         ulong pixval;
 139         long err;
 140         int i;
 141
 142         clkdvdr = ioremap(get_immrbase() + 0xe0800, sizeof(u32));
 143         if (!clkdvdr) {
 144                 printk(KERN_ERR "Err: can't map clock divider register!\n");
 145                 return;
 146         }
 147
 148         /* Pixel Clock configuration */
 149         pr_debug("DIU: Bus Frequency = %d\n", get_busfreq());
 150         speed_ccb = get_busfreq();
 151
 152         /* Calculate the pixel clock with the smallest error */
 153         /* calculate the following in steps to avoid overflow */
 154         pr_debug("DIU pixclock in ps - %d\n", pixclock);
 155         temp = 1000000000/pixclock;
 156         temp *= 1000;
 157         pixclock = temp;
 158         pr_debug("DIU pixclock freq - %u\n", pixclock);
 159
 160         temp = pixclock * 5 / 100;
 161         pr_debug("deviation = %d\n", temp);
 162         minpixclock = pixclock - temp;
 163         maxpixclock = pixclock + temp;
 164         pr_debug("DIU minpixclock - %lu\n", minpixclock);
 165         pr_debug("DIU maxpixclock - %lu\n", maxpixclock);
 166         pixval = speed_ccb/pixclock;
 167         pr_debug("DIU pixval = %lu\n", pixval);
 168
 169         err = 100000000;
 170         bestval = pixval;
 171         pr_debug("DIU bestval = %lu\n", bestval);
 172
 173         bestfreq = 0;
 174         for (i = -1; i <= 1; i++) {
 175                 temp = speed_ccb / ((pixval+i) + 1);
 176                 pr_debug("DIU test pixval i= %d, pixval=%lu, temp freq. = %u\n",
 177                                                         i, pixval, temp);
 178                 if ((temp < minpixclock) || (temp > maxpixclock))
 179                         pr_debug("DIU exceeds monitor range (%lu to %lu)\n",
 180                                 minpixclock, maxpixclock);
 181                 else if (abs(temp - pixclock) < err) {
 182                   pr_debug("Entered the else if block %d\n", i);
 183                         err = abs(temp - pixclock);
 184                         bestval = pixval+i;
 185                         bestfreq = temp;
 186                 }
 187         }
 188
 189         pr_debug("DIU chose = %lx\n", bestval);
 190         pr_debug("DIU error = %ld\n NomPixClk ", err);
 191         pr_debug("DIU: Best Freq = %lx\n", bestfreq);
 192         /* Modify PXCLK in GUTS CLKDVDR */
 193         pr_debug("DIU: Current value of CLKDVDR = 0x%08x\n", (*clkdvdr));
 194         temp = (*clkdvdr) & 0x2000FFFF;
 195         *clkdvdr = temp;                /* turn off clock */
 196         *clkdvdr = temp | 0x80000000 | (((bestval) & 0x1F) << 16);
 197         pr_debug("DIU: Modified value of CLKDVDR = 0x%08x\n", (*clkdvdr));
 198         iounmap(clkdvdr);
 199 }
 200
 201 ssize_t mpc8610hpcd_show_monitor_port(int monitor_port, char *buf)
 202 {
 203         return snprintf(buf, PAGE_SIZE,
 204                         "%c0 - DVI\n"
 205                         "%c1 - Single link LVDS\n"
 206                         "%c2 - Dual link LVDS\n",
 207                         monitor_port == 0 ? '*' : ' ',
 208                         monitor_port == 1 ? '*' : ' ',
 209                         monitor_port == 2 ? '*' : ' ');
 210 }
 211
 212 int mpc8610hpcd_set_sysfs_monitor_port(int val)
 213 {
 214         return val < 3 ? val : 0;
 215 }
 216
 217 #endif
 218
 219 static void __init mpc86xx_hpcd_setup_arch(void)
 220 {
 221         struct resource r;
 222         struct device_node *np;
 223         unsigned char *pixis;
 224
 225         if (ppc_md.progress)
 226                 ppc_md.progress("mpc86xx_hpcd_setup_arch()", 0);
 227
 228 #ifdef CONFIG_PCI
 229         for_each_node_by_type(np, "pci") {
 230                 if (of_device_is_compatible(np, "fsl,mpc8610-pci")
 231                     || of_device_is_compatible(np, "fsl,mpc8641-pcie")) {
 232                         struct resource rsrc;
 233                         of_address_to_resource(np, 0, &rsrc);
 234                         if ((rsrc.start & 0xfffff) == 0xa000)
 235                                 fsl_add_bridge(np, 1);
 236                         else
 237                                 fsl_add_bridge(np, 0);
 238                 }
 239         }
 240 #endif
 241 #if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
 242         diu_ops.get_pixel_format        = mpc8610hpcd_get_pixel_format;
 243         diu_ops.set_gamma_table         = mpc8610hpcd_set_gamma_table;
 244         diu_ops.set_monitor_port        = mpc8610hpcd_set_monitor_port;
 245         diu_ops.set_pixel_clock         = mpc8610hpcd_set_pixel_clock;
 246         diu_ops.show_monitor_port       = mpc8610hpcd_show_monitor_port;
 247         diu_ops.set_sysfs_monitor_port  = mpc8610hpcd_set_sysfs_monitor_port;
 248 #endif
 249
 250         np = of_find_compatible_node(NULL, NULL, "fsl,fpga-pixis");
 251         if (np) {
 252                 of_address_to_resource(np, 0, &r);
 253                 of_node_put(np);
 254                 pixis = ioremap(r.start, 32);
 255                 if (!pixis) {
 256                         printk(KERN_ERR "Err: can't map FPGA cfg register!\n");
 257                         return;
 258                 }
 259                 pixis_bdcfg0 = pixis + 8;
 260                 pixis_arch = pixis + 1;
 261         } else
 262                 printk(KERN_ERR "Err: "
 263                                 "can't find device node 'fsl,fpga-pixis'\n");
 264
 265         printk("MPC86xx HPCD board from Freescale Semiconductor\n");
 266 }
 267
 268 /*
 269  * Called very early, device-tree isn't unflattened
 270  */
 271 static int __init mpc86xx_hpcd_probe(void)
 272 {
 273         unsigned long root = of_get_flat_dt_root();
 274
 275         if (of_flat_dt_is_compatible(root, "fsl,MPC8610HPCD"))
 276                 return 1;       /* Looks good */
 277
 278         return 0;
 279 }
 280
 281 static long __init mpc86xx_time_init(void)
 282 {
 283         unsigned int temp;
 284
 285         /* Set the time base to zero */
 286         mtspr(SPRN_TBWL, 0);
 287         mtspr(SPRN_TBWU, 0);
 288
 289         temp = mfspr(SPRN_HID0);
 290         temp |= HID0_TBEN;
 291         mtspr(SPRN_HID0, temp);
 292         asm volatile("isync");
 293
 294         return 0;
 295 }
 296
 297 define_machine(mpc86xx_hpcd) {
 298         .name                   = "MPC86xx HPCD",
 299         .probe                  = mpc86xx_hpcd_probe,
 300         .setup_arch             = mpc86xx_hpcd_setup_arch,
 301         .init_IRQ               = mpc86xx_init_irq,
 302         .get_irq                = mpic_get_irq,
 303         .restart                = fsl_rstcr_restart,
 304         .time_init              = mpc86xx_time_init,
 305         .calibrate_decr         = generic_calibrate_decr,
 306         .progress               = udbg_progress,
 307         .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
 308 };