2 * MPC8610 HPCD board specific routines
4 * Initial author: Xianghua Xiao <x.xiao@freescale.com>
5 * Recode: Jason Jin <jason.jin@freescale.com>
6 * York Sun <yorksun@freescale.com>
8 * Rewrite the interrupt routing. remove the 8259PIC support,
9 * All the integrated device in ULI use sideband interrupt.
11 * Copyright 2008 Freescale Semiconductor Inc.
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
19 #include <linux/stddef.h>
20 #include <linux/kernel.h>
21 #include <linux/pci.h>
22 #include <linux/kdev_t.h>
23 #include <linux/delay.h>
24 #include <linux/seq_file.h>
27 #include <asm/system.h>
29 #include <asm/machdep.h>
30 #include <asm/pci-bridge.h>
31 #include <asm/mpc86xx.h>
33 #include <mm/mmu_decl.h>
38 #include <linux/of_platform.h>
39 #include <sysdev/fsl_pci.h>
40 #include <sysdev/fsl_soc.h>
44 static unsigned char *pixis_bdcfg0
, *pixis_arch
;
46 static struct of_device_id __initdata mpc8610_ids
[] = {
47 { .compatible
= "fsl,mpc8610-immr", },
48 { .compatible
= "simple-bus", },
49 { .compatible
= "gianfar", },
53 static int __init
mpc8610_declare_of_platform_devices(void)
55 /* Without this call, the SSI device driver won't get probed. */
56 of_platform_bus_probe(NULL
, mpc8610_ids
, NULL
);
60 machine_device_initcall(mpc86xx_hpcd
, mpc8610_declare_of_platform_devices
);
62 #if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
64 static u32
get_busfreq(void)
66 struct device_node
*node
;
69 node
= of_find_node_by_type(NULL
, "cpu");
72 const unsigned int *prop
=
73 of_get_property(node
, "bus-frequency", &size
);
81 unsigned int mpc8610hpcd_get_pixel_format(unsigned int bits_per_pixel
,
84 static const unsigned long pixelformat
[][3] = {
85 {0x88882317, 0x88083218, 0x65052119},
86 {0x88883316, 0x88082219, 0x65053118},
88 unsigned int pix_fmt
, arch_monitor
;
90 arch_monitor
= ((*pixis_arch
== 0x01) && (monitor_port
== 0))? 0 : 1;
91 /* DVI port for board version 0x01 */
93 if (bits_per_pixel
== 32)
94 pix_fmt
= pixelformat
[arch_monitor
][0];
95 else if (bits_per_pixel
== 24)
96 pix_fmt
= pixelformat
[arch_monitor
][1];
97 else if (bits_per_pixel
== 16)
98 pix_fmt
= pixelformat
[arch_monitor
][2];
100 pix_fmt
= pixelformat
[1][0];
105 void mpc8610hpcd_set_gamma_table(int monitor_port
, char *gamma_table_base
)
108 if (monitor_port
== 2) { /* dual link LVDS */
109 for (i
= 0; i
< 256*3; i
++)
110 gamma_table_base
[i
] = (gamma_table_base
[i
] << 2) |
111 ((gamma_table_base
[i
] >> 6) & 0x03);
115 #define PX_BRDCFG0_DVISEL (1 << 3)
116 #define PX_BRDCFG0_DLINK (1 << 4)
117 #define PX_BRDCFG0_DIU_MASK (PX_BRDCFG0_DVISEL | PX_BRDCFG0_DLINK)
119 void mpc8610hpcd_set_monitor_port(int monitor_port
)
121 static const u8 bdcfg
[] = {
122 PX_BRDCFG0_DVISEL
| PX_BRDCFG0_DLINK
,
127 if (monitor_port
< 3)
128 clrsetbits_8(pixis_bdcfg0
, PX_BRDCFG0_DIU_MASK
,
129 bdcfg
[monitor_port
]);
132 void mpc8610hpcd_set_pixel_clock(unsigned int pixclock
)
134 u32 __iomem
*clkdvdr
;
136 /* variables for pixel clock calcs */
137 ulong bestval
, bestfreq
, speed_ccb
, minpixclock
, maxpixclock
;
142 clkdvdr
= ioremap(get_immrbase() + 0xe0800, sizeof(u32
));
144 printk(KERN_ERR
"Err: can't map clock divider register!\n");
148 /* Pixel Clock configuration */
149 pr_debug("DIU: Bus Frequency = %d\n", get_busfreq());
150 speed_ccb
= get_busfreq();
152 /* Calculate the pixel clock with the smallest error */
153 /* calculate the following in steps to avoid overflow */
154 pr_debug("DIU pixclock in ps - %d\n", pixclock
);
155 temp
= 1000000000/pixclock
;
158 pr_debug("DIU pixclock freq - %u\n", pixclock
);
160 temp
= pixclock
* 5 / 100;
161 pr_debug("deviation = %d\n", temp
);
162 minpixclock
= pixclock
- temp
;
163 maxpixclock
= pixclock
+ temp
;
164 pr_debug("DIU minpixclock - %lu\n", minpixclock
);
165 pr_debug("DIU maxpixclock - %lu\n", maxpixclock
);
166 pixval
= speed_ccb
/pixclock
;
167 pr_debug("DIU pixval = %lu\n", pixval
);
171 pr_debug("DIU bestval = %lu\n", bestval
);
174 for (i
= -1; i
<= 1; i
++) {
175 temp
= speed_ccb
/ ((pixval
+i
) + 1);
176 pr_debug("DIU test pixval i= %d, pixval=%lu, temp freq. = %u\n",
178 if ((temp
< minpixclock
) || (temp
> maxpixclock
))
179 pr_debug("DIU exceeds monitor range (%lu to %lu)\n",
180 minpixclock
, maxpixclock
);
181 else if (abs(temp
- pixclock
) < err
) {
182 pr_debug("Entered the else if block %d\n", i
);
183 err
= abs(temp
- pixclock
);
189 pr_debug("DIU chose = %lx\n", bestval
);
190 pr_debug("DIU error = %ld\n NomPixClk ", err
);
191 pr_debug("DIU: Best Freq = %lx\n", bestfreq
);
192 /* Modify PXCLK in GUTS CLKDVDR */
193 pr_debug("DIU: Current value of CLKDVDR = 0x%08x\n", (*clkdvdr
));
194 temp
= (*clkdvdr
) & 0x2000FFFF;
195 *clkdvdr
= temp
; /* turn off clock */
196 *clkdvdr
= temp
| 0x80000000 | (((bestval
) & 0x1F) << 16);
197 pr_debug("DIU: Modified value of CLKDVDR = 0x%08x\n", (*clkdvdr
));
201 ssize_t
mpc8610hpcd_show_monitor_port(int monitor_port
, char *buf
)
203 return snprintf(buf
, PAGE_SIZE
,
205 "%c1 - Single link LVDS\n"
206 "%c2 - Dual link LVDS\n",
207 monitor_port
== 0 ? '*' : ' ',
208 monitor_port
== 1 ? '*' : ' ',
209 monitor_port
== 2 ? '*' : ' ');
212 int mpc8610hpcd_set_sysfs_monitor_port(int val
)
214 return val
< 3 ? val
: 0;
219 static void __init
mpc86xx_hpcd_setup_arch(void)
222 struct device_node
*np
;
223 unsigned char *pixis
;
226 ppc_md
.progress("mpc86xx_hpcd_setup_arch()", 0);
229 for_each_node_by_type(np
, "pci") {
230 if (of_device_is_compatible(np
, "fsl,mpc8610-pci")
231 || of_device_is_compatible(np
, "fsl,mpc8641-pcie")) {
232 struct resource rsrc
;
233 of_address_to_resource(np
, 0, &rsrc
);
234 if ((rsrc
.start
& 0xfffff) == 0xa000)
235 fsl_add_bridge(np
, 1);
237 fsl_add_bridge(np
, 0);
241 #if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
242 diu_ops
.get_pixel_format
= mpc8610hpcd_get_pixel_format
;
243 diu_ops
.set_gamma_table
= mpc8610hpcd_set_gamma_table
;
244 diu_ops
.set_monitor_port
= mpc8610hpcd_set_monitor_port
;
245 diu_ops
.set_pixel_clock
= mpc8610hpcd_set_pixel_clock
;
246 diu_ops
.show_monitor_port
= mpc8610hpcd_show_monitor_port
;
247 diu_ops
.set_sysfs_monitor_port
= mpc8610hpcd_set_sysfs_monitor_port
;
250 np
= of_find_compatible_node(NULL
, NULL
, "fsl,fpga-pixis");
252 of_address_to_resource(np
, 0, &r
);
254 pixis
= ioremap(r
.start
, 32);
256 printk(KERN_ERR
"Err: can't map FPGA cfg register!\n");
259 pixis_bdcfg0
= pixis
+ 8;
260 pixis_arch
= pixis
+ 1;
262 printk(KERN_ERR
"Err: "
263 "can't find device node 'fsl,fpga-pixis'\n");
265 printk("MPC86xx HPCD board from Freescale Semiconductor\n");
269 * Called very early, device-tree isn't unflattened
271 static int __init
mpc86xx_hpcd_probe(void)
273 unsigned long root
= of_get_flat_dt_root();
275 if (of_flat_dt_is_compatible(root
, "fsl,MPC8610HPCD"))
276 return 1; /* Looks good */
281 static long __init
mpc86xx_time_init(void)
285 /* Set the time base to zero */
289 temp
= mfspr(SPRN_HID0
);
291 mtspr(SPRN_HID0
, temp
);
292 asm volatile("isync");
297 define_machine(mpc86xx_hpcd
) {
298 .name
= "MPC86xx HPCD",
299 .probe
= mpc86xx_hpcd_probe
,
300 .setup_arch
= mpc86xx_hpcd_setup_arch
,
301 .init_IRQ
= mpc86xx_init_irq
,
302 .get_irq
= mpic_get_irq
,
303 .restart
= fsl_rstcr_restart
,
304 .time_init
= mpc86xx_time_init
,
305 .calibrate_decr
= generic_calibrate_decr
,
306 .progress
= udbg_progress
,
307 .pcibios_fixup_bus
= fsl_pcibios_fixup_bus
,