arch/powerpc/platforms/Kconfig

   1 menu "Platform support"
   2
   3 config PPC_MULTIPLATFORM
   4         bool
   5         depends on PPC64 || 6xx
   6         default y
   7
   8 config CLASSIC32
   9         def_bool y
  10         depends on 6xx && PPC_MULTIPLATFORM
  11
  12 source "arch/powerpc/platforms/pseries/Kconfig"
  13 source "arch/powerpc/platforms/iseries/Kconfig"
  14 source "arch/powerpc/platforms/chrp/Kconfig"
  15 source "arch/powerpc/platforms/512x/Kconfig"
  16 source "arch/powerpc/platforms/52xx/Kconfig"
  17 source "arch/powerpc/platforms/powermac/Kconfig"
  18 source "arch/powerpc/platforms/prep/Kconfig"
  19 source "arch/powerpc/platforms/maple/Kconfig"
  20 source "arch/powerpc/platforms/pasemi/Kconfig"
  21 source "arch/powerpc/platforms/ps3/Kconfig"
  22 source "arch/powerpc/platforms/cell/Kconfig"
  23 source "arch/powerpc/platforms/8xx/Kconfig"
  24 source "arch/powerpc/platforms/82xx/Kconfig"
  25 source "arch/powerpc/platforms/83xx/Kconfig"
  26 source "arch/powerpc/platforms/85xx/Kconfig"
  27 source "arch/powerpc/platforms/86xx/Kconfig"
  28 source "arch/powerpc/platforms/embedded6xx/Kconfig"
  29 source "arch/powerpc/platforms/44x/Kconfig"
  30 source "arch/powerpc/platforms/40x/Kconfig"
  31 source "arch/powerpc/platforms/amigaone/Kconfig"
  32
  33 config PPC_NATIVE
  34         bool
  35         depends on PPC_MULTIPLATFORM
  36         help
  37           Support for running natively on the hardware, i.e. without
  38           a hypervisor. This option is not user-selectable but should
  39           be selected by all platforms that need it.
  40
  41 config UDBG_RTAS_CONSOLE
  42         bool "RTAS based debug console"
  43         depends on PPC_RTAS
  44         default n
  45
  46 config PPC_UDBG_BEAT
  47         bool "BEAT based debug console"
  48         depends on PPC_CELLEB
  49         default n
  50
  51 config XICS
  52         depends on PPC_PSERIES
  53         bool
  54         default y
  55
  56 config IPIC
  57         bool
  58         default n
  59
  60 config MPIC
  61         bool
  62         default n
  63
  64 config MPIC_WEIRD
  65         bool
  66         default n
  67
  68 config PPC_I8259
  69         bool
  70         default n
  71
  72 config U3_DART
  73         bool
  74         depends on PPC_MULTIPLATFORM && PPC64
  75         default n
  76
  77 config PPC_RTAS
  78         bool
  79         default n
  80
  81 config RTAS_ERROR_LOGGING
  82         bool
  83         depends on PPC_RTAS
  84         default n
  85
  86 config RTAS_PROC
  87         bool "Proc interface to RTAS"
  88         depends on PPC_RTAS
  89         default y
  90
  91 config RTAS_FLASH
  92         tristate "Firmware flash interface"
  93         depends on PPC64 && RTAS_PROC
  94
  95 config MMIO_NVRAM
  96         bool
  97         default n
  98
  99 config MPIC_U3_HT_IRQS
 100         bool
 101         depends on PPC_MAPLE
 102         default y
 103
 104 config MPIC_BROKEN_REGREAD
 105         bool
 106         depends on MPIC
 107         help
 108           This option enables a MPIC driver workaround for some chips
 109           that have a bug that causes some interrupt source information
 110           to not read back properly. It is safe to use on other chips as
 111           well, but enabling it uses about 8KB of memory to keep copies
 112           of the register contents in software.
 113
 114 config IBMVIO
 115         depends on PPC_PSERIES || PPC_ISERIES
 116         bool
 117         default y
 118
 119 config IBMEBUS
 120         depends on PPC_PSERIES
 121         bool "Support for GX bus based adapters"
 122         help
 123           Bus device driver for GX bus based adapters.
 124
 125 config PPC_MPC106
 126         bool
 127         default n
 128
 129 config PPC_970_NAP
 130         bool
 131         default n
 132
 133 config PPC_INDIRECT_IO
 134         bool
 135         select GENERIC_IOMAP
 136         default n
 137
 138 config GENERIC_IOMAP
 139         bool
 140         default n
 141
 142 source "drivers/cpufreq/Kconfig"
 143
 144 menu "CPU Frequency drivers"
 145         depends on CPU_FREQ
 146
 147 config CPU_FREQ_PMAC
 148         bool "Support for Apple PowerBooks"
 149         depends on ADB_PMU && PPC32
 150         select CPU_FREQ_TABLE
 151         help
 152           This adds support for frequency switching on Apple PowerBooks,
 153           this currently includes some models of iBook & Titanium
 154           PowerBook.
 155
 156 config CPU_FREQ_PMAC64
 157         bool "Support for some Apple G5s"
 158         depends on PPC_PMAC && PPC64
 159         select CPU_FREQ_TABLE
 160         help
 161           This adds support for frequency switching on Apple iMac G5,
 162           and some of the more recent desktop G5 machines as well.
 163
 164 config PPC_PASEMI_CPUFREQ
 165         bool "Support for PA Semi PWRficient"
 166         depends on PPC_PASEMI
 167         default y
 168         select CPU_FREQ_TABLE
 169         help
 170           This adds the support for frequency switching on PA Semi
 171           PWRficient processors.
 172
 173 endmenu
 174
 175 config PPC601_SYNC_FIX
 176         bool "Workarounds for PPC601 bugs"
 177         depends on 6xx && (PPC_PREP || PPC_PMAC)
 178         help
 179           Some versions of the PPC601 (the first PowerPC chip) have bugs which
 180           mean that extra synchronization instructions are required near
 181           certain instructions, typically those that make major changes to the
 182           CPU state.  These extra instructions reduce performance slightly.
 183           If you say N here, these extra instructions will not be included,
 184           resulting in a kernel which will run faster but may not run at all
 185           on some systems with the PPC601 chip.
 186
 187           If in doubt, say Y here.
 188
 189 config TAU
 190         bool "On-chip CPU temperature sensor support"
 191         depends on CLASSIC32
 192         help
 193           G3 and G4 processors have an on-chip temperature sensor called the
 194           'Thermal Assist Unit (TAU)', which, in theory, can measure the on-die
 195           temperature within 2-4 degrees Celsius. This option shows the current
 196           on-die temperature in /proc/cpuinfo if the cpu supports it.
 197
 198           Unfortunately, on some chip revisions, this sensor is very inaccurate
 199           and in many cases, does not work at all, so don't assume the cpu
 200           temp is actually what /proc/cpuinfo says it is.
 201
 202 config TAU_INT
 203         bool "Interrupt driven TAU driver (DANGEROUS)"
 204         depends on TAU
 205         ---help---
 206           The TAU supports an interrupt driven mode which causes an interrupt
 207           whenever the temperature goes out of range. This is the fastest way
 208           to get notified the temp has exceeded a range. With this option off,
 209           a timer is used to re-check the temperature periodically.
 210
 211           However, on some cpus it appears that the TAU interrupt hardware
 212           is buggy and can cause a situation which would lead unexplained hard
 213           lockups.
 214
 215           Unless you are extending the TAU driver, or enjoy kernel/hardware
 216           debugging, leave this option off.
 217
 218 config TAU_AVERAGE
 219         bool "Average high and low temp"
 220         depends on TAU
 221         ---help---
 222           The TAU hardware can compare the temperature to an upper and lower
 223           bound.  The default behavior is to show both the upper and lower
 224           bound in /proc/cpuinfo. If the range is large, the temperature is
 225           either changing a lot, or the TAU hardware is broken (likely on some
 226           G4's). If the range is small (around 4 degrees), the temperature is
 227           relatively stable.  If you say Y here, a single temperature value,
 228           halfway between the upper and lower bounds, will be reported in
 229           /proc/cpuinfo.
 230
 231           If in doubt, say N here.
 232
 233 config QUICC_ENGINE
 234         bool "Freescale QUICC Engine (QE) Support"
 235         depends on FSL_SOC
 236         select PPC_LIB_RHEAP
 237         select CRC32
 238         help
 239           The QUICC Engine (QE) is a new generation of communications
 240           coprocessors on Freescale embedded CPUs (akin to CPM in older chips).
 241           Selecting this option means that you wish to build a kernel
 242           for a machine with a QE coprocessor.
 243
 244 config QE_GPIO
 245         bool "QE GPIO support"
 246         depends on QUICC_ENGINE
 247         select GENERIC_GPIO
 248         select ARCH_REQUIRE_GPIOLIB
 249         help
 250           Say Y here if you're going to use hardware that connects to the
 251           QE GPIOs.
 252
 253 config CPM2
 254         bool "Enable support for the CPM2 (Communications Processor Module)"
 255         depends on MPC85xx || 8260
 256         select CPM
 257         select PPC_LIB_RHEAP
 258         select PPC_PCI_CHOICE
 259         select ARCH_REQUIRE_GPIOLIB
 260         select GENERIC_GPIO
 261         help
 262           The CPM2 (Communications Processor Module) is a coprocessor on
 263           embedded CPUs made by Freescale.  Selecting this option means that
 264           you wish to build a kernel for a machine with a CPM2 coprocessor
 265           on it (826x, 827x, 8560).
 266
 267 config AXON_RAM
 268         tristate "Axon DDR2 memory device driver"
 269         depends on PPC_IBM_CELL_BLADE
 270         default m
 271         help
 272           It registers one block device per Axon's DDR2 memory bank found
 273           on a system. Block devices are called axonram?, their major and
 274           minor numbers are available in /proc/devices, /proc/partitions or
 275           in /sys/block/axonram?/dev.
 276
 277 config FSL_ULI1575
 278         bool
 279         default n
 280         select GENERIC_ISA_DMA
 281         help
 282           Supports for the ULI1575 PCIe south bridge that exists on some
 283           Freescale reference boards. The boards all use the ULI in pretty
 284           much the same way.
 285
 286 config CPM
 287         bool
 288         select PPC_CLOCK
 289
 290 config OF_RTC
 291         bool
 292         help
 293           Uses information from the OF or flattened device tree to instatiate
 294           platform devices for direct mapped RTC chips like the DS1742 or DS1743.
 295
 296 source "arch/powerpc/sysdev/bestcomm/Kconfig"
 297
 298 config MPC8xxx_GPIO
 299         bool "MPC8xxx GPIO support"
 300         depends on PPC_MPC831x || PPC_MPC834x || PPC_MPC837x || PPC_85xx || PPC_86xx
 301         select GENERIC_GPIO
 302         select ARCH_REQUIRE_GPIOLIB
 303         help
 304           Say Y here if you're going to use hardware that connects to the
 305           MPC831x/834x/837x/8572/8610 GPIOs.
 306
 307 config SIMPLE_GPIO
 308         bool "Support for simple, memory-mapped GPIO controllers"
 309         depends on PPC
 310         select GENERIC_GPIO
 311         select ARCH_REQUIRE_GPIOLIB
 312         help
 313           Say Y here to support simple, memory-mapped GPIO controllers.
 314           These are usually BCSRs used to control board's switches, LEDs,
 315           chip-selects, Ethernet/USB PHY's power and various other small
 316           on-board peripherals.
 317
 318 config MCU_MPC8349EMITX
 319         tristate "MPC8349E-mITX MCU driver"
 320         depends on I2C && PPC_83xx
 321         select GENERIC_GPIO
 322         select ARCH_REQUIRE_GPIOLIB
 323         help
 324           Say Y here to enable soft power-off functionality on the Freescale
 325           boards with the MPC8349E-mITX-compatible MCU chips. This driver will
 326           also register MCU GPIOs with the generic GPIO API, so you'll able
 327           to use MCU pins as GPIOs.
 328
 329 endmenu