arch/powerpc/platforms/cell/celleb_scc_epci.c

   1 /*
   2  * Support for SCC external PCI
   3  *
   4  * (C) Copyright 2004-2007 TOSHIBA CORPORATION
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along
  17  * with this program; if not, write to the Free Software Foundation, Inc.,
  18  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  19  */
  20
  21 #undef DEBUG
  22
  23 #include <linux/kernel.h>
  24 #include <linux/threads.h>
  25 #include <linux/pci.h>
  26 #include <linux/init.h>
  27 #include <linux/pci_regs.h>
  28 #include <linux/bootmem.h>
  29
  30 #include <asm/io.h>
  31 #include <asm/irq.h>
  32 #include <asm/prom.h>
  33 #include <asm/pci-bridge.h>
  34 #include <asm/ppc-pci.h>
  35
  36 #include "celleb_scc.h"
  37 #include "celleb_pci.h"
  38
  39 #define MAX_PCI_DEVICES   32
  40 #define MAX_PCI_FUNCTIONS  8
  41
  42 #define iob()  __asm__ __volatile__("eieio; sync":::"memory")
  43
  44 static inline PCI_IO_ADDR celleb_epci_get_epci_base(
  45                                         struct pci_controller *hose)
  46 {
  47         /*
  48          * Note:
  49          * Celleb epci uses cfg_addr as a base address for
  50          * epci control registers.
  51          */
  52
  53         return hose->cfg_addr;
  54 }
  55
  56 static inline PCI_IO_ADDR celleb_epci_get_epci_cfg(
  57                                         struct pci_controller *hose)
  58 {
  59         /*
  60          * Note:
  61          * Celleb epci uses cfg_data as a base address for
  62          * configuration area for epci devices.
  63          */
  64
  65         return hose->cfg_data;
  66 }
  67
  68 static inline void clear_and_disable_master_abort_interrupt(
  69                                         struct pci_controller *hose)
  70 {
  71         PCI_IO_ADDR epci_base;
  72         PCI_IO_ADDR reg;
  73         epci_base = celleb_epci_get_epci_base(hose);
  74         reg = epci_base + PCI_COMMAND;
  75         out_be32(reg, in_be32(reg) | (PCI_STATUS_REC_MASTER_ABORT << 16));
  76 }
  77
  78 static int celleb_epci_check_abort(struct pci_controller *hose,
  79                                    PCI_IO_ADDR addr)
  80 {
  81         PCI_IO_ADDR reg;
  82         PCI_IO_ADDR epci_base;
  83         u32 val;
  84
  85         iob();
  86         epci_base = celleb_epci_get_epci_base(hose);
  87
  88         reg = epci_base + PCI_COMMAND;
  89         val = in_be32(reg);
  90
  91         if (val & (PCI_STATUS_REC_MASTER_ABORT << 16)) {
  92                 out_be32(reg,
  93                          (val & 0xffff) | (PCI_STATUS_REC_MASTER_ABORT << 16));
  94
  95                 /* clear PCI Controller error, FRE, PMFE */
  96                 reg = epci_base + SCC_EPCI_STATUS;
  97                 out_be32(reg, SCC_EPCI_INT_PAI);
  98
  99                 reg = epci_base + SCC_EPCI_VCSR;
 100                 val = in_be32(reg) & 0xffff;
 101                 val |= SCC_EPCI_VCSR_FRE;
 102                 out_be32(reg, val);
 103
 104                 reg = epci_base + SCC_EPCI_VISTAT;
 105                 out_be32(reg, SCC_EPCI_VISTAT_PMFE);
 106                 return PCIBIOS_DEVICE_NOT_FOUND;
 107         }
 108
 109         return PCIBIOS_SUCCESSFUL;
 110 }
 111
 112 static PCI_IO_ADDR celleb_epci_make_config_addr(struct pci_bus *bus,
 113                 struct pci_controller *hose, unsigned int devfn, int where)
 114 {
 115         PCI_IO_ADDR addr;
 116
 117         if (bus != hose->bus)
 118                 addr = celleb_epci_get_epci_cfg(hose) +
 119                        (((bus->number & 0xff) << 16)
 120                         | ((devfn & 0xff) << 8)
 121                         | (where & 0xff)
 122                         | 0x01000000);
 123         else
 124                 addr = celleb_epci_get_epci_cfg(hose) +
 125                        (((devfn & 0xff) << 8) | (where & 0xff));
 126
 127         pr_debug("EPCI: config_addr = 0x%p\n", addr);
 128
 129         return addr;
 130 }
 131
 132 static int celleb_epci_read_config(struct pci_bus *bus,
 133                         unsigned int devfn, int where, int size, u32 *val)
 134 {
 135         PCI_IO_ADDR epci_base;
 136         PCI_IO_ADDR addr;
 137         struct device_node *node;
 138         struct pci_controller *hose;
 139
 140         /* allignment check */
 141         BUG_ON(where % size);
 142
 143         node = (struct device_node *)bus->sysdata;
 144         hose = pci_find_hose_for_OF_device(node);
 145
 146         if (!celleb_epci_get_epci_cfg(hose))
 147                 return PCIBIOS_DEVICE_NOT_FOUND;
 148
 149         if (bus->number == hose->first_busno && devfn == 0) {
 150                 /* EPCI controller self */
 151
 152                 epci_base = celleb_epci_get_epci_base(hose);
 153                 addr = epci_base + where;
 154
 155                 switch (size) {
 156                 case 1:
 157                         *val = in_8(addr);
 158                         break;
 159                 case 2:
 160                         *val = in_be16(addr);
 161                         break;
 162                 case 4:
 163                         *val = in_be32(addr);
 164                         break;
 165                 default:
 166                         return PCIBIOS_DEVICE_NOT_FOUND;
 167                 }
 168
 169         } else {
 170
 171                 clear_and_disable_master_abort_interrupt(hose);
 172                 addr = celleb_epci_make_config_addr(bus, hose, devfn, where);
 173
 174                 switch (size) {
 175                 case 1:
 176                         *val = in_8(addr);
 177                         break;
 178                 case 2:
 179                         *val = in_le16(addr);
 180                         break;
 181                 case 4:
 182                         *val = in_le32(addr);
 183                         break;
 184                 default:
 185                         return PCIBIOS_DEVICE_NOT_FOUND;
 186                 }
 187         }
 188
 189         pr_debug("EPCI: "
 190                  "addr=0x%p, devfn=0x%x, where=0x%x, size=0x%x, val=0x%x\n",
 191                  addr, devfn, where, size, *val);
 192
 193         return celleb_epci_check_abort(hose, NULL);
 194 }
 195
 196 static int celleb_epci_write_config(struct pci_bus *bus,
 197                         unsigned int devfn, int where, int size, u32 val)
 198 {
 199         PCI_IO_ADDR epci_base;
 200         PCI_IO_ADDR addr;
 201         struct device_node *node;
 202         struct pci_controller *hose;
 203
 204         /* allignment check */
 205         BUG_ON(where % size);
 206
 207         node = (struct device_node *)bus->sysdata;
 208         hose = pci_find_hose_for_OF_device(node);
 209
 210
 211         if (!celleb_epci_get_epci_cfg(hose))
 212                 return PCIBIOS_DEVICE_NOT_FOUND;
 213
 214         if (bus->number == hose->first_busno && devfn == 0) {
 215                 /* EPCI controller self */
 216
 217                 epci_base = celleb_epci_get_epci_base(hose);
 218                 addr = epci_base + where;
 219
 220                 switch (size) {
 221                 case 1:
 222                         out_8(addr, val);
 223                         break;
 224                 case 2:
 225                         out_be16(addr, val);
 226                         break;
 227                 case 4:
 228                         out_be32(addr, val);
 229                         break;
 230                 default:
 231                         return PCIBIOS_DEVICE_NOT_FOUND;
 232                 }
 233
 234         } else {
 235
 236                 clear_and_disable_master_abort_interrupt(hose);
 237                 addr = celleb_epci_make_config_addr(bus, hose, devfn, where);
 238
 239                 switch (size) {
 240                 case 1:
 241                         out_8(addr, val);
 242                         break;
 243                 case 2:
 244                         out_le16(addr, val);
 245                         break;
 246                 case 4:
 247                         out_le32(addr, val);
 248                         break;
 249                 default:
 250                         return PCIBIOS_DEVICE_NOT_FOUND;
 251                 }
 252         }
 253
 254         return celleb_epci_check_abort(hose, addr);
 255 }
 256
 257 struct pci_ops celleb_epci_ops = {
 258         .read = celleb_epci_read_config,
 259         .write = celleb_epci_write_config,
 260 };
 261
 262 /* to be moved in FW */
 263 static int __init celleb_epci_init(struct pci_controller *hose)
 264 {
 265         u32 val;
 266         PCI_IO_ADDR reg;
 267         PCI_IO_ADDR epci_base;
 268         int hwres = 0;
 269
 270         epci_base = celleb_epci_get_epci_base(hose);
 271
 272         /* PCI core reset(Internal bus and PCI clock) */
 273         reg = epci_base + SCC_EPCI_CKCTRL;
 274         val = in_be32(reg);
 275         if (val == 0x00030101)
 276                 hwres = 1;
 277         else {
 278                 val &= ~(SCC_EPCI_CKCTRL_CRST0 | SCC_EPCI_CKCTRL_CRST1);
 279                 out_be32(reg, val);
 280
 281                 /* set PCI core clock */
 282                 val = in_be32(reg);
 283                 val |= (SCC_EPCI_CKCTRL_OCLKEN | SCC_EPCI_CKCTRL_LCLKEN);
 284                 out_be32(reg, val);
 285
 286                 /* release PCI core reset (internal bus) */
 287                 val = in_be32(reg);
 288                 val |= SCC_EPCI_CKCTRL_CRST0;
 289                 out_be32(reg, val);
 290
 291                 /* set PCI clock select */
 292                 reg = epci_base + SCC_EPCI_CLKRST;
 293                 val = in_be32(reg);
 294                 val &= ~SCC_EPCI_CLKRST_CKS_MASK;
 295                 val |= SCC_EPCI_CLKRST_CKS_2;
 296                 out_be32(reg, val);
 297
 298                 /* set arbiter */
 299                 reg = epci_base + SCC_EPCI_ABTSET;
 300                 out_be32(reg, 0x0f1f001f);      /* temporary value */
 301
 302                 /* buffer on */
 303                 reg = epci_base + SCC_EPCI_CLKRST;
 304                 val = in_be32(reg);
 305                 val |= SCC_EPCI_CLKRST_BC;
 306                 out_be32(reg, val);
 307
 308                 /* PCI clock enable */
 309                 val = in_be32(reg);
 310                 val |= SCC_EPCI_CLKRST_PCKEN;
 311                 out_be32(reg, val);
 312
 313                 /* release PCI core reset (all) */
 314                 reg = epci_base + SCC_EPCI_CKCTRL;
 315                 val = in_be32(reg);
 316                 val |= (SCC_EPCI_CKCTRL_CRST0 | SCC_EPCI_CKCTRL_CRST1);
 317                 out_be32(reg, val);
 318
 319                 /* set base translation registers. (already set by Beat) */
 320
 321                 /* set base address masks. (already set by Beat) */
 322         }
 323
 324         /* release interrupt masks and clear all interrupts */
 325         reg = epci_base + SCC_EPCI_INTSET;
 326         out_be32(reg, 0x013f011f);      /* all interrupts enable */
 327         reg = epci_base + SCC_EPCI_VIENAB;
 328         val = SCC_EPCI_VIENAB_PMPEE | SCC_EPCI_VIENAB_PMFEE;
 329         out_be32(reg, val);
 330         reg = epci_base + SCC_EPCI_STATUS;
 331         out_be32(reg, 0xffffffff);
 332         reg = epci_base + SCC_EPCI_VISTAT;
 333         out_be32(reg, 0xffffffff);
 334
 335         /* disable PCI->IB address translation */
 336         reg = epci_base + SCC_EPCI_VCSR;
 337         val = in_be32(reg);
 338         val &= ~(SCC_EPCI_VCSR_DR | SCC_EPCI_VCSR_AT);
 339         out_be32(reg, val);
 340
 341         /* set base addresses. (no need to set?) */
 342
 343         /* memory space, bus master enable */
 344         reg = epci_base + PCI_COMMAND;
 345         val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
 346         out_be32(reg, val);
 347
 348         /* endian mode setup */
 349         reg = epci_base + SCC_EPCI_ECMODE;
 350         val = 0x00550155;
 351         out_be32(reg, val);
 352
 353         /* set control option */
 354         reg = epci_base + SCC_EPCI_CNTOPT;
 355         val = in_be32(reg);
 356         val |= SCC_EPCI_CNTOPT_O2PMB;
 357         out_be32(reg, val);
 358
 359         /* XXX: temporay: set registers for address conversion setup */
 360         reg = epci_base + SCC_EPCI_CNF10_REG;
 361         out_be32(reg, 0x80000008);
 362         reg = epci_base + SCC_EPCI_CNF14_REG;
 363         out_be32(reg, 0x40000008);
 364
 365         reg = epci_base + SCC_EPCI_BAM0;
 366         out_be32(reg, 0x80000000);
 367         reg = epci_base + SCC_EPCI_BAM1;
 368         out_be32(reg, 0xe0000000);
 369
 370         reg = epci_base + SCC_EPCI_PVBAT;
 371         out_be32(reg, 0x80000000);
 372
 373         if (!hwres) {
 374                 /* release external PCI reset */
 375                 reg = epci_base + SCC_EPCI_CLKRST;
 376                 val = in_be32(reg);
 377                 val |= SCC_EPCI_CLKRST_PCIRST;
 378                 out_be32(reg, val);
 379         }
 380
 381         return 0;
 382 }
 383
 384 static int __init celleb_setup_epci(struct device_node *node,
 385                                     struct pci_controller *hose)
 386 {
 387         struct resource r;
 388
 389         pr_debug("PCI: celleb_setup_epci()\n");
 390
 391         /*
 392          * Note:
 393          * Celleb epci uses cfg_addr and cfg_data member of
 394          * pci_controller structure in irregular way.
 395          *
 396          * cfg_addr is used to map for control registers of
 397          * celleb epci.
 398          *
 399          * cfg_data is used for configuration area of devices
 400          * on Celleb epci buses.
 401          */
 402
 403         if (of_address_to_resource(node, 0, &r))
 404                 goto error;
 405         hose->cfg_addr = ioremap(r.start, (r.end - r.start + 1));
 406         if (!hose->cfg_addr)
 407                 goto error;
 408         pr_debug("EPCI: cfg_addr map 0x%016llx->0x%016lx + 0x%016llx\n",
 409                  r.start, (unsigned long)hose->cfg_addr, (r.end - r.start + 1));
 410
 411         if (of_address_to_resource(node, 2, &r))
 412                 goto error;
 413         hose->cfg_data = ioremap(r.start, (r.end - r.start + 1));
 414         if (!hose->cfg_data)
 415                 goto error;
 416         pr_debug("EPCI: cfg_data map 0x%016llx->0x%016lx + 0x%016llx\n",
 417                  r.start, (unsigned long)hose->cfg_data, (r.end - r.start + 1));
 418
 419         hose->ops = &celleb_epci_ops;
 420         celleb_epci_init(hose);
 421
 422         return 0;
 423
 424 error:
 425         if (hose->cfg_addr)
 426                 iounmap(hose->cfg_addr);
 427
 428         if (hose->cfg_data)
 429                 iounmap(hose->cfg_data);
 430         return 1;
 431 }
 432
 433 struct celleb_phb_spec celleb_epci_spec __initdata = {
 434         .setup = celleb_setup_epci,
 435         .ops = &spiderpci_ops,
 436         .iowa_init = &spiderpci_iowa_init,
 437         .iowa_data = (void *)0,
 438 };