2 * Cell Internal Interrupt Controller
4 * Copyright (C) 2006 Benjamin Herrenschmidt (benh@kernel.crashing.org)
7 * (C) Copyright IBM Deutschland Entwicklung GmbH 2005
9 * Author: Arnd Bergmann <arndb@de.ibm.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 * - Fix various assumptions related to HW CPU numbers vs. linux CPU numbers
27 * vs node numbers in the setup code
28 * - Implement proper handling of maxcpus=1/2 (that is, routing of irqs from
29 * a non-active node to the active node)
32 #include <linux/interrupt.h>
33 #include <linux/irq.h>
34 #include <linux/module.h>
35 #include <linux/percpu.h>
36 #include <linux/types.h>
37 #include <linux/ioport.h>
38 #include <linux/kernel_stat.h>
41 #include <asm/pgtable.h>
43 #include <asm/ptrace.h>
44 #include <asm/machdep.h>
45 #include <asm/cell-regs.h>
47 #include "interrupt.h"
50 struct cbe_iic_thread_regs __iomem
*regs
;
54 struct device_node
*node
;
57 static DEFINE_PER_CPU(struct iic
, cpu_iic
);
58 #define IIC_NODE_COUNT 2
59 static struct irq_host
*iic_host
;
61 /* Convert between "pending" bits and hw irq number */
62 static irq_hw_number_t
iic_pending_to_hwnum(struct cbe_iic_pending_bits bits
)
64 unsigned char unit
= bits
.source
& 0xf;
65 unsigned char node
= bits
.source
>> 4;
66 unsigned char class = bits
.class & 3;
69 if (bits
.flags
& CBE_IIC_IRQ_IPI
)
70 return IIC_IRQ_TYPE_IPI
| (bits
.prio
>> 4);
72 return (node
<< IIC_IRQ_NODE_SHIFT
) | (class << 4) | unit
;
75 static void iic_mask(struct irq_data
*d
)
79 static void iic_unmask(struct irq_data
*d
)
83 static void iic_eoi(struct irq_data
*d
)
85 struct iic
*iic
= &__get_cpu_var(cpu_iic
);
86 out_be64(&iic
->regs
->prio
, iic
->eoi_stack
[--iic
->eoi_ptr
]);
87 BUG_ON(iic
->eoi_ptr
< 0);
90 static struct irq_chip iic_chip
= {
93 .irq_unmask
= iic_unmask
,
98 static void iic_ioexc_eoi(struct irq_data
*d
)
102 static void iic_ioexc_cascade(unsigned int irq
, struct irq_desc
*desc
)
104 struct irq_chip
*chip
= get_irq_desc_chip(desc
);
105 struct cbe_iic_regs __iomem
*node_iic
=
106 (void __iomem
*)get_irq_desc_data(desc
);
107 unsigned int base
= (irq
& 0xffffff00) | IIC_IRQ_TYPE_IOEXC
;
108 unsigned long bits
, ack
;
112 bits
= in_be64(&node_iic
->iic_is
);
115 /* pre-ack edge interrupts */
116 ack
= bits
& IIC_ISR_EDGE_MASK
;
118 out_be64(&node_iic
->iic_is
, ack
);
120 for (cascade
= 63; cascade
>= 0; cascade
--)
121 if (bits
& (0x8000000000000000UL
>> cascade
)) {
123 irq_linear_revmap(iic_host
,
126 generic_handle_irq(cirq
);
128 /* post-ack level interrupts */
129 ack
= bits
& ~IIC_ISR_EDGE_MASK
;
131 out_be64(&node_iic
->iic_is
, ack
);
133 chip
->irq_eoi(&desc
->irq_data
);
137 static struct irq_chip iic_ioexc_chip
= {
139 .irq_mask
= iic_mask
,
140 .irq_unmask
= iic_unmask
,
141 .irq_eoi
= iic_ioexc_eoi
,
144 /* Get an IRQ number from the pending state register of the IIC */
145 static unsigned int iic_get_irq(void)
147 struct cbe_iic_pending_bits pending
;
151 iic
= &__get_cpu_var(cpu_iic
);
152 *(unsigned long *) &pending
=
153 in_be64((u64 __iomem
*) &iic
->regs
->pending_destr
);
154 if (!(pending
.flags
& CBE_IIC_IRQ_VALID
))
156 virq
= irq_linear_revmap(iic_host
, iic_pending_to_hwnum(pending
));
159 iic
->eoi_stack
[++iic
->eoi_ptr
] = pending
.prio
;
160 BUG_ON(iic
->eoi_ptr
> 15);
164 void iic_setup_cpu(void)
166 out_be64(&__get_cpu_var(cpu_iic
).regs
->prio
, 0xff);
169 u8
iic_get_target_id(int cpu
)
171 return per_cpu(cpu_iic
, cpu
).target_id
;
174 EXPORT_SYMBOL_GPL(iic_get_target_id
);
178 /* Use the highest interrupt priorities for IPI */
179 static inline int iic_ipi_to_irq(int ipi
)
181 return IIC_IRQ_TYPE_IPI
+ 0xf - ipi
;
184 void iic_cause_IPI(int cpu
, int mesg
)
186 out_be64(&per_cpu(cpu_iic
, cpu
).regs
->generate
, (0xf - mesg
) << 4);
189 struct irq_host
*iic_get_irq_host(int node
)
193 EXPORT_SYMBOL_GPL(iic_get_irq_host
);
195 static irqreturn_t
iic_ipi_action(int irq
, void *dev_id
)
197 int ipi
= (int)(long)dev_id
;
199 smp_message_recv(ipi
);
203 static void iic_request_ipi(int ipi
, const char *name
)
207 virq
= irq_create_mapping(iic_host
, iic_ipi_to_irq(ipi
));
208 if (virq
== NO_IRQ
) {
210 "iic: failed to map IPI %s\n", name
);
213 if (request_irq(virq
, iic_ipi_action
, IRQF_DISABLED
, name
,
216 "iic: failed to request IPI %s\n", name
);
219 void iic_request_IPIs(void)
221 iic_request_ipi(PPC_MSG_CALL_FUNCTION
, "IPI-call");
222 iic_request_ipi(PPC_MSG_RESCHEDULE
, "IPI-resched");
223 iic_request_ipi(PPC_MSG_CALL_FUNC_SINGLE
, "IPI-call-single");
224 #ifdef CONFIG_DEBUGGER
225 iic_request_ipi(PPC_MSG_DEBUGGER_BREAK
, "IPI-debug");
226 #endif /* CONFIG_DEBUGGER */
229 #endif /* CONFIG_SMP */
232 static int iic_host_match(struct irq_host
*h
, struct device_node
*node
)
234 return of_device_is_compatible(node
,
235 "IBM,CBEA-Internal-Interrupt-Controller");
238 static int iic_host_map(struct irq_host
*h
, unsigned int virq
,
241 switch (hw
& IIC_IRQ_TYPE_MASK
) {
242 case IIC_IRQ_TYPE_IPI
:
243 set_irq_chip_and_handler(virq
, &iic_chip
, handle_percpu_irq
);
245 case IIC_IRQ_TYPE_IOEXC
:
246 set_irq_chip_and_handler(virq
, &iic_ioexc_chip
,
250 set_irq_chip_and_handler(virq
, &iic_chip
, handle_edge_eoi_irq
);
255 static int iic_host_xlate(struct irq_host
*h
, struct device_node
*ct
,
256 const u32
*intspec
, unsigned int intsize
,
257 irq_hw_number_t
*out_hwirq
, unsigned int *out_flags
)
260 unsigned int node
, ext
, unit
, class;
263 if (!of_device_is_compatible(ct
,
264 "IBM,CBEA-Internal-Interrupt-Controller"))
268 val
= of_get_property(ct
, "#interrupt-cells", NULL
);
269 if (val
== NULL
|| *val
!= 1)
272 node
= intspec
[0] >> 24;
273 ext
= (intspec
[0] >> 16) & 0xff;
274 class = (intspec
[0] >> 8) & 0xff;
275 unit
= intspec
[0] & 0xff;
277 /* Check if node is in supported range */
281 /* Build up interrupt number, special case for IO exceptions */
282 *out_hwirq
= (node
<< IIC_IRQ_NODE_SHIFT
);
283 if (unit
== IIC_UNIT_IIC
&& class == 1)
284 *out_hwirq
|= IIC_IRQ_TYPE_IOEXC
| ext
;
286 *out_hwirq
|= IIC_IRQ_TYPE_NORMAL
|
287 (class << IIC_IRQ_CLASS_SHIFT
) | unit
;
289 /* Dummy flags, ignored by iic code */
290 *out_flags
= IRQ_TYPE_EDGE_RISING
;
295 static struct irq_host_ops iic_host_ops
= {
296 .match
= iic_host_match
,
298 .xlate
= iic_host_xlate
,
301 static void __init
init_one_iic(unsigned int hw_cpu
, unsigned long addr
,
302 struct device_node
*node
)
304 /* XXX FIXME: should locate the linux CPU number from the HW cpu
305 * number properly. We are lucky for now
307 struct iic
*iic
= &per_cpu(cpu_iic
, hw_cpu
);
309 iic
->regs
= ioremap(addr
, sizeof(struct cbe_iic_thread_regs
));
310 BUG_ON(iic
->regs
== NULL
);
312 iic
->target_id
= ((hw_cpu
& 2) << 3) | ((hw_cpu
& 1) ? 0xf : 0xe);
313 iic
->eoi_stack
[0] = 0xff;
314 iic
->node
= of_node_get(node
);
315 out_be64(&iic
->regs
->prio
, 0);
317 printk(KERN_INFO
"IIC for CPU %d target id 0x%x : %s\n",
318 hw_cpu
, iic
->target_id
, node
->full_name
);
321 static int __init
setup_iic(void)
323 struct device_node
*dn
;
324 struct resource r0
, r1
;
325 unsigned int node
, cascade
, found
= 0;
326 struct cbe_iic_regs __iomem
*node_iic
;
330 (dn
= of_find_node_by_name(dn
,"interrupt-controller")) != NULL
;) {
331 if (!of_device_is_compatible(dn
,
332 "IBM,CBEA-Internal-Interrupt-Controller"))
334 np
= of_get_property(dn
, "ibm,interrupt-server-ranges", NULL
);
336 printk(KERN_WARNING
"IIC: CPU association not found\n");
340 if (of_address_to_resource(dn
, 0, &r0
) ||
341 of_address_to_resource(dn
, 1, &r1
)) {
342 printk(KERN_WARNING
"IIC: Can't resolve addresses\n");
347 init_one_iic(np
[0], r0
.start
, dn
);
348 init_one_iic(np
[1], r1
.start
, dn
);
350 /* Setup cascade for IO exceptions. XXX cleanup tricks to get
352 * Note that we configure the IIC_IRR here with a hard coded
353 * priority of 1. We might want to improve that later.
356 node_iic
= cbe_get_cpu_iic_regs(np
[0]);
357 cascade
= node
<< IIC_IRQ_NODE_SHIFT
;
358 cascade
|= 1 << IIC_IRQ_CLASS_SHIFT
;
359 cascade
|= IIC_UNIT_IIC
;
360 cascade
= irq_create_mapping(iic_host
, cascade
);
361 if (cascade
== NO_IRQ
)
364 * irq_data is a generic pointer that gets passed back
365 * to us later, so the forced cast is fine.
367 set_irq_data(cascade
, (void __force
*)node_iic
);
368 set_irq_chained_handler(cascade
, iic_ioexc_cascade
);
369 out_be64(&node_iic
->iic_ir
,
370 (1 << 12) /* priority */ |
371 (node
<< 4) /* dest node */ |
372 IIC_UNIT_THREAD_0
/* route them to thread 0 */);
373 /* Flush pending (make sure it triggers if there is
376 out_be64(&node_iic
->iic_is
, 0xfffffffffffffffful
);
385 void __init
iic_init_IRQ(void)
387 /* Setup an irq host data structure */
388 iic_host
= irq_alloc_host(NULL
, IRQ_HOST_MAP_LINEAR
, IIC_SOURCE_COUNT
,
389 &iic_host_ops
, IIC_IRQ_INVALID
);
390 BUG_ON(iic_host
== NULL
);
391 irq_set_default_host(iic_host
);
393 /* Discover and initialize iics */
395 panic("IIC: Failed to initialize !\n");
397 /* Set master interrupt handling function */
398 ppc_md
.get_irq
= iic_get_irq
;
400 /* Enable on current CPU */
404 void iic_set_interrupt_routing(int cpu
, int thread
, int priority
)
406 struct cbe_iic_regs __iomem
*iic_regs
= cbe_get_cpu_iic_regs(cpu
);
410 /* Set which node and thread will handle the next interrupt */
411 iic_ir
|= CBE_IIC_IR_PRIO(priority
) |
412 CBE_IIC_IR_DEST_NODE(node
);
414 iic_ir
|= CBE_IIC_IR_DEST_UNIT(CBE_IIC_IR_PT_0
);
416 iic_ir
|= CBE_IIC_IR_DEST_UNIT(CBE_IIC_IR_PT_1
);
417 out_be64(&iic_regs
->iic_ir
, iic_ir
);