arch/powerpc/platforms/celleb/scc_uhc.c

   1 /*
   2  * SCC (Super Companion Chip) UHC setup
   3  *
   4  * (C) Copyright 2006-2007 TOSHIBA CORPORATION
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along
  17  * with this program; if not, write to the Free Software Foundation, Inc.,
  18  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  19  */
  20
  21 #include <linux/kernel.h>
  22 #include <linux/pci.h>
  23
  24 #include <asm/delay.h>
  25 #include <asm/io.h>
  26 #include <asm/machdep.h>
  27
  28 #include "scc.h"
  29
  30 #define UHC_RESET_WAIT_MAX 10000
  31
  32 static inline int uhc_clkctrl_ready(u32 val)
  33 {
  34         const u32 mask = SCC_UHC_USBCEN | SCC_UHC_USBCEN;
  35         return((val & mask) == mask);
  36 }
  37
  38 /*
  39  * UHC(usb host controler) enable function.
  40  * affect to both of OHCI and EHCI core module.
  41  */
  42 static void enable_scc_uhc(struct pci_dev *dev)
  43 {
  44         void __iomem *uhc_base;
  45         u32 __iomem *uhc_clkctrl;
  46         u32 __iomem *uhc_ecmode;
  47         u32 val = 0;
  48         int i;
  49
  50         if (!machine_is(celleb))
  51                 return;
  52
  53         uhc_base = ioremap(pci_resource_start(dev, 0),
  54                            pci_resource_len(dev, 0));
  55         if (!uhc_base) {
  56                 printk(KERN_ERR "failed to map UHC register base.\n");
  57                 return;
  58         }
  59         uhc_clkctrl = uhc_base + SCC_UHC_CKRCTRL;
  60         uhc_ecmode  = uhc_base + SCC_UHC_ECMODE;
  61
  62         /* setup for normal mode */
  63         val |= SCC_UHC_F48MCKLEN;
  64         out_be32(uhc_clkctrl, val);
  65         val |= SCC_UHC_PHY_SUSPEND_SEL;
  66         out_be32(uhc_clkctrl, val);
  67         udelay(10);
  68         val |= SCC_UHC_PHYEN;
  69         out_be32(uhc_clkctrl, val);
  70         udelay(50);
  71
  72         /* disable reset */
  73         val |= SCC_UHC_HCLKEN;
  74         out_be32(uhc_clkctrl, val);
  75         val |= (SCC_UHC_USBCEN | SCC_UHC_USBEN);
  76         out_be32(uhc_clkctrl, val);
  77         i = 0;
  78         while (!uhc_clkctrl_ready(in_be32(uhc_clkctrl))) {
  79                 udelay(10);
  80                 if (i++ > UHC_RESET_WAIT_MAX) {
  81                         printk(KERN_ERR "Failed to disable UHC reset %x\n",
  82                                in_be32(uhc_clkctrl));
  83                         break;
  84                 }
  85         }
  86
  87         /* Endian Conversion Mode for Master ALL area */
  88         out_be32(uhc_ecmode, SCC_UHC_ECMODE_BY_BYTE);
  89
  90         iounmap(uhc_base);
  91 }
  92
  93 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
  94                  PCI_DEVICE_ID_TOSHIBA_SCC_USB, enable_scc_uhc);