arch/powerpc/platforms/celleb/setup.c

   1 /*
   2  * Celleb setup code
   3  *
   4  * (C) Copyright 2006-2007 TOSHIBA CORPORATION
   5  *
   6  * This code is based on arch/powerpc/platforms/cell/setup.c:
   7  *  Copyright (C) 1995  Linus Torvalds
   8  *  Adapted from 'alpha' version by Gary Thomas
   9  *  Modified by Cort Dougan (cort@cs.nmt.edu)
  10  *  Modified by PPC64 Team, IBM Corp
  11  *  Modified by Cell Team, IBM Deutschland Entwicklung GmbH
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of the GNU General Public License as published by
  15  * the Free Software Foundation; either version 2 of the License, or
  16  * (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License along
  24  * with this program; if not, write to the Free Software Foundation, Inc.,
  25  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  26  */
  27
  28 #undef DEBUG
  29
  30 #include <linux/cpu.h>
  31 #include <linux/sched.h>
  32 #include <linux/kernel.h>
  33 #include <linux/mm.h>
  34 #include <linux/stddef.h>
  35 #include <linux/unistd.h>
  36 #include <linux/reboot.h>
  37 #include <linux/init.h>
  38 #include <linux/delay.h>
  39 #include <linux/irq.h>
  40 #include <linux/seq_file.h>
  41 #include <linux/root_dev.h>
  42 #include <linux/console.h>
  43
  44 #include <asm/mmu.h>
  45 #include <asm/processor.h>
  46 #include <asm/io.h>
  47 #include <asm/kexec.h>
  48 #include <asm/prom.h>
  49 #include <asm/machdep.h>
  50 #include <asm/cputable.h>
  51 #include <asm/irq.h>
  52 #include <asm/time.h>
  53 #include <asm/spu_priv1.h>
  54 #include <asm/firmware.h>
  55 #include <asm/of_platform.h>
  56 #include <asm/rtas.h>
  57 #include <asm/cell-regs.h>
  58
  59 #include "interrupt.h"
  60 #include "beat_wrapper.h"
  61 #include "beat.h"
  62 #include "pci.h"
  63 #include "../cell/interrupt.h"
  64 #include "../cell/pervasive.h"
  65 #include "../cell/ras.h"
  66
  67 static char celleb_machine_type[128] = "Celleb";
  68
  69 static void celleb_show_cpuinfo(struct seq_file *m)
  70 {
  71         struct device_node *root;
  72         const char *model = "";
  73
  74         root = of_find_node_by_path("/");
  75         if (root)
  76                 model = of_get_property(root, "model", NULL);
  77         /* using "CHRP" is to trick anaconda into installing FCx into Celleb */
  78         seq_printf(m, "machine\t\t: %s %s\n", celleb_machine_type, model);
  79         of_node_put(root);
  80 }
  81
  82 static int __init celleb_machine_type_hack(char *ptr)
  83 {
  84         strncpy(celleb_machine_type, ptr, sizeof(celleb_machine_type));
  85         celleb_machine_type[sizeof(celleb_machine_type)-1] = 0;
  86         return 0;
  87 }
  88
  89 __setup("celleb_machine_type_hack=", celleb_machine_type_hack);
  90
  91 static void celleb_progress(char *s, unsigned short hex)
  92 {
  93         printk("*** %04x : %s\n", hex, s ? s : "");
  94 }
  95
  96 static void __init celleb_init_IRQ_native(void)
  97 {
  98         iic_init_IRQ();
  99         spider_init_IRQ();
 100 }
 101
 102 static void __init celleb_setup_arch_beat(void)
 103 {
 104         ppc_md.restart          = beat_restart;
 105         ppc_md.power_off        = beat_power_off;
 106         ppc_md.halt             = beat_halt;
 107         ppc_md.get_rtc_time     = beat_get_rtc_time;
 108         ppc_md.set_rtc_time     = beat_set_rtc_time;
 109         ppc_md.power_save       = beat_power_save;
 110         ppc_md.nvram_size       = beat_nvram_get_size;
 111         ppc_md.nvram_read       = beat_nvram_read;
 112         ppc_md.nvram_write      = beat_nvram_write;
 113         ppc_md.set_dabr         = beat_set_xdabr;
 114         ppc_md.init_IRQ         = beatic_init_IRQ;
 115         ppc_md.get_irq          = beatic_get_irq;
 116 #ifdef CONFIG_KEXEC
 117         ppc_md.kexec_cpu_down   = beat_kexec_cpu_down;
 118 #endif
 119
 120 #ifdef CONFIG_SPU_BASE
 121         spu_priv1_ops           = &spu_priv1_beat_ops;
 122         spu_management_ops      = &spu_management_of_ops;
 123 #endif
 124
 125 #ifdef CONFIG_SMP
 126         smp_init_celleb();
 127 #endif
 128 }
 129
 130 static void __init celleb_setup_arch_native(void)
 131 {
 132         ppc_md.restart          = rtas_restart;
 133         ppc_md.power_off        = rtas_power_off;
 134         ppc_md.halt             = rtas_halt;
 135         ppc_md.get_boot_time    = rtas_get_boot_time;
 136         ppc_md.get_rtc_time     = rtas_get_rtc_time;
 137         ppc_md.set_rtc_time     = rtas_set_rtc_time;
 138         ppc_md.init_IRQ         = celleb_init_IRQ_native;
 139
 140 #ifdef CONFIG_SPU_BASE
 141         spu_priv1_ops           = &spu_priv1_mmio_ops;
 142         spu_management_ops      = &spu_management_of_ops;
 143 #endif
 144
 145         cbe_regs_init();
 146
 147 #ifdef CONFIG_CBE_RAS
 148         cbe_ras_init();
 149 #endif
 150
 151 #ifdef CONFIG_SMP
 152         smp_init_cell();
 153 #endif
 154
 155         cbe_pervasive_init();
 156 }
 157
 158 static void __init celleb_setup_arch(void)
 159 {
 160         if (firmware_has_feature(FW_FEATURE_BEAT))
 161                 celleb_setup_arch_beat();
 162         else
 163                 celleb_setup_arch_native();
 164
 165         /* init to some ~sane value until calibrate_delay() runs */
 166         loops_per_jiffy = 50000000;
 167
 168 #ifdef CONFIG_DUMMY_CONSOLE
 169         conswitchp = &dummy_con;
 170 #endif
 171 }
 172
 173 static int __init celleb_probe(void)
 174 {
 175         unsigned long root = of_get_flat_dt_root();
 176
 177         if (of_flat_dt_is_compatible(root, "Beat")) {
 178                 powerpc_firmware_features |= FW_FEATURE_CELLEB_ALWAYS
 179                         | FW_FEATURE_BEAT | FW_FEATURE_LPAR;
 180                 hpte_init_beat_v3();
 181                 return 1;
 182         }
 183         if (of_flat_dt_is_compatible(root, "TOSHIBA,Celleb")) {
 184                 powerpc_firmware_features |= FW_FEATURE_CELLEB_ALWAYS;
 185                 hpte_init_native();
 186                 return 1;
 187         }
 188
 189         return 0;
 190 }
 191
 192 static struct of_device_id celleb_bus_ids[] __initdata = {
 193         { .type = "scc", },
 194         { .type = "ioif", },    /* old style */
 195         {},
 196 };
 197
 198 static int __init celleb_publish_devices(void)
 199 {
 200         if (!machine_is(celleb))
 201                 return 0;
 202
 203         /* Publish OF platform devices for southbridge IOs */
 204         of_platform_bus_probe(NULL, celleb_bus_ids, NULL);
 205
 206         celleb_pci_workaround_init();
 207
 208         return 0;
 209 }
 210 device_initcall(celleb_publish_devices);
 211
 212 define_machine(celleb) {
 213         .name                   = "Cell Reference Set",
 214         .probe                  = celleb_probe,
 215         .setup_arch             = celleb_setup_arch,
 216         .show_cpuinfo           = celleb_show_cpuinfo,
 217         .calibrate_decr         = generic_calibrate_decr,
 218         .progress               = celleb_progress,
 219         .pci_probe_mode         = celleb_pci_probe_mode,
 220         .pci_setup_phb          = celleb_setup_phb,
 221 #ifdef CONFIG_KEXEC
 222         .machine_kexec          = default_machine_kexec,
 223         .machine_kexec_prepare  = default_machine_kexec_prepare,
 224         .machine_crash_shutdown = default_machine_crash_shutdown,
 225 #endif
 226 };