arch/powerpc/platforms/iseries/lpardata.c

   1 /*
   2  * Copyright 2001 Mike Corrigan, IBM Corp
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * as published by the Free Software Foundation; either version
   7  * 2 of the License, or (at your option) any later version.
   8  */
   9 #include <linux/types.h>
  10 #include <linux/threads.h>
  11 #include <linux/module.h>
  12 #include <linux/bitops.h>
  13 #include <asm/processor.h>
  14 #include <asm/ptrace.h>
  15 #include <asm/abs_addr.h>
  16 #include <asm/iseries/it_lp_naca.h>
  17 #include <asm/lppaca.h>
  18 #include <asm/iseries/it_lp_reg_save.h>
  19 #include <asm/paca.h>
  20 #include <asm/iseries/lpar_map.h>
  21 #include <asm/iseries/it_exp_vpd_panel.h>
  22 #include <asm/iseries/it_lp_queue.h>
  23
  24 #include "naca.h"
  25 #include "vpd_areas.h"
  26 #include "spcomm_area.h"
  27 #include "ipl_parms.h"
  28 #include "processor_vpd.h"
  29 #include "release_data.h"
  30
  31 /* The HvReleaseData is the root of the information shared between
  32  * the hypervisor and Linux.
  33  */
  34 struct HvReleaseData hvReleaseData = {
  35         .xDesc = 0xc8a5d9c4,    /* "HvRD" ebcdic */
  36         .xSize = sizeof(struct HvReleaseData),
  37         .xVpdAreasPtrOffset = offsetof(struct naca_struct, xItVpdAreas),
  38         .xSlicNacaAddr = &naca,         /* 64-bit Naca address */
  39         .xMsNucDataOffset = LPARMAP_PHYS,
  40         .xFlags = HVREL_TAGSINACTIVE    /* tags inactive       */
  41                                         /* 64 bit              */
  42                                         /* shared processors   */
  43                                         /* HMT allowed         */
  44                   | 6,                  /* TEMP: This allows non-GA driver */
  45         .xVrmIndex = 4,                 /* We are v5r2m0               */
  46         .xMinSupportedPlicVrmIndex = 3,         /* v5r1m0 */
  47         .xMinCompatablePlicVrmIndex = 3,        /* v5r1m0 */
  48         .xVrmName = { 0xd3, 0x89, 0x95, 0xa4,   /* "Linux 2.4.64" ebcdic */
  49                 0xa7, 0x40, 0xf2, 0x4b,
  50                 0xf4, 0x4b, 0xf6, 0xf4 },
  51 };
  52
  53 /*
  54  * The NACA.  The first dword of the naca is required by the iSeries
  55  * hypervisor to point to itVpdAreas.  The hypervisor finds the NACA
  56  * through the pointer in hvReleaseData.
  57  */
  58 struct naca_struct naca = {
  59         .xItVpdAreas = &itVpdAreas,
  60         .xRamDisk = 0,
  61         .xRamDiskSize = 0,
  62 };
  63
  64 extern void system_reset_iSeries(void);
  65 extern void machine_check_iSeries(void);
  66 extern void data_access_iSeries(void);
  67 extern void instruction_access_iSeries(void);
  68 extern void hardware_interrupt_iSeries(void);
  69 extern void alignment_iSeries(void);
  70 extern void program_check_iSeries(void);
  71 extern void fp_unavailable_iSeries(void);
  72 extern void decrementer_iSeries(void);
  73 extern void trap_0a_iSeries(void);
  74 extern void trap_0b_iSeries(void);
  75 extern void system_call_iSeries(void);
  76 extern void single_step_iSeries(void);
  77 extern void trap_0e_iSeries(void);
  78 extern void performance_monitor_iSeries(void);
  79 extern void data_access_slb_iSeries(void);
  80 extern void instruction_access_slb_iSeries(void);
  81
  82 struct ItLpNaca itLpNaca = {
  83         .xDesc = 0xd397d581,            /* "LpNa" ebcdic */
  84         .xSize = 0x0400,                /* size of ItLpNaca */
  85         .xIntHdlrOffset = 0x0300,       /* offset to int array */
  86         .xMaxIntHdlrEntries = 19,       /* # ents */
  87         .xPrimaryLpIndex = 0,           /* Part # of primary */
  88         .xServiceLpIndex = 0,           /* Part # of serv */
  89         .xLpIndex = 0,                  /* Part # of me */
  90         .xMaxLpQueues = 0,              /* # of LP queues */
  91         .xLpQueueOffset = 0x100,        /* offset of start of LP queues */
  92         .xPirEnvironMode = 0,           /* Piranha stuff */
  93         .xPirConsoleMode = 0,
  94         .xPirDasdMode = 0,
  95         .flags = 0,
  96         .xSpVpdFormat = 0,
  97         .xIntProcRatio = 0,
  98         .xPlicVrmIndex = 0,             /* VRM index of PLIC */
  99         .xMinSupportedSlicVrmInd = 0,   /* min supported SLIC */
 100         .xMinCompatableSlicVrmInd = 0,  /* min compat SLIC */
 101         .xLoadAreaAddr = 0,             /* 64-bit addr of load area */
 102         .xLoadAreaChunks = 0,           /* chunks for load area */
 103         .xPaseSysCallCRMask = 0,        /* PASE mask */
 104         .xSlicSegmentTablePtr = 0,      /* seg table */
 105         .xOldLpQueue = { 0 },           /* Old LP Queue */
 106         .xInterruptHdlr = {
 107                 (u64)system_reset_iSeries,      /* 0x100 System Reset */
 108                 (u64)machine_check_iSeries,     /* 0x200 Machine Check */
 109                 (u64)data_access_iSeries,       /* 0x300 Data Access */
 110                 (u64)instruction_access_iSeries, /* 0x400 Instruction Access */
 111                 (u64)hardware_interrupt_iSeries, /* 0x500 External */
 112                 (u64)alignment_iSeries,         /* 0x600 Alignment */
 113                 (u64)program_check_iSeries,     /* 0x700 Program Check */
 114                 (u64)fp_unavailable_iSeries,    /* 0x800 FP Unavailable */
 115                 (u64)decrementer_iSeries,       /* 0x900 Decrementer */
 116                 (u64)trap_0a_iSeries,           /* 0xa00 Trap 0A */
 117                 (u64)trap_0b_iSeries,           /* 0xb00 Trap 0B */
 118                 (u64)system_call_iSeries,       /* 0xc00 System Call */
 119                 (u64)single_step_iSeries,       /* 0xd00 Single Step */
 120                 (u64)trap_0e_iSeries,           /* 0xe00 Trap 0E */
 121                 (u64)performance_monitor_iSeries,/* 0xf00 Performance Monitor */
 122                 0,                              /* int 0x1000 */
 123                 0,                              /* int 0x1010 */
 124                 0,                              /* int 0x1020 CPU ctls */
 125                 (u64)hardware_interrupt_iSeries, /* SC Ret Hdlr */
 126                 (u64)data_access_slb_iSeries,   /* 0x380 D-SLB */
 127                 (u64)instruction_access_slb_iSeries /* 0x480 I-SLB */
 128         }
 129 };
 130 EXPORT_SYMBOL(itLpNaca);
 131
 132 /* May be filled in by the hypervisor so cannot end up in the BSS */
 133 struct ItIplParmsReal xItIplParmsReal __attribute__((__section__(".data")));
 134
 135 /* May be filled in by the hypervisor so cannot end up in the BSS */
 136 struct ItExtVpdPanel xItExtVpdPanel __attribute__((__section__(".data")));
 137 EXPORT_SYMBOL(xItExtVpdPanel);
 138
 139 #define maxPhysicalProcessors 32
 140
 141 struct IoHriProcessorVpd xIoHriProcessorVpd[maxPhysicalProcessors] = {
 142         {
 143                 .xInstCacheOperandSize = 32,
 144                 .xDataCacheOperandSize = 32,
 145                 .xProcFreq     = 50000000,
 146                 .xTimeBaseFreq = 50000000,
 147                 .xPVR = 0x3600
 148         }
 149 };
 150
 151 /* Space for Main Store Vpd 27,200 bytes */
 152 /* May be filled in by the hypervisor so cannot end up in the BSS */
 153 u64    xMsVpd[3400] __attribute__((__section__(".data")));
 154
 155 /* Space for Recovery Log Buffer */
 156 /* May be filled in by the hypervisor so cannot end up in the BSS */
 157 u64    xRecoveryLogBuffer[32] __attribute__((__section__(".data")));
 158
 159 struct SpCommArea xSpCommArea = {
 160         .xDesc = 0xE2D7C3C2,
 161         .xFormat = 1,
 162 };
 163
 164 /* The LparMap data is now located at offset 0x6000 in head.S
 165  * It was put there so that the HvReleaseData could address it
 166  * with a 32-bit offset as required by the iSeries hypervisor
 167  *
 168  * The Naca has a pointer to the ItVpdAreas.  The hypervisor finds
 169  * the Naca via the HvReleaseData area.  The HvReleaseData has the
 170  * offset into the Naca of the pointer to the ItVpdAreas.
 171  */
 172 struct ItVpdAreas itVpdAreas = {
 173         .xSlicDesc = 0xc9a3e5c1,                /* "ItVA" */
 174         .xSlicSize = sizeof(struct ItVpdAreas),
 175         .xSlicVpdEntries = ItVpdMaxEntries,     /* # VPD array entries */
 176         .xSlicDmaEntries = ItDmaMaxEntries,     /* # DMA array entries */
 177         .xSlicMaxLogicalProcs = NR_CPUS * 2,    /* Max logical procs */
 178         .xSlicMaxPhysicalProcs = maxPhysicalProcessors, /* Max physical procs */
 179         .xSlicDmaToksOffset = offsetof(struct ItVpdAreas, xPlicDmaToks),
 180         .xSlicVpdAdrsOffset = offsetof(struct ItVpdAreas, xSlicVpdAdrs),
 181         .xSlicDmaLensOffset = offsetof(struct ItVpdAreas, xPlicDmaLens),
 182         .xSlicVpdLensOffset = offsetof(struct ItVpdAreas, xSlicVpdLens),
 183         .xSlicMaxSlotLabels = 0,                /* max slot labels */
 184         .xSlicMaxLpQueues = 1,                  /* max LP queues */
 185         .xPlicDmaLens = { 0 },                  /* DMA lengths */
 186         .xPlicDmaToks = { 0 },                  /* DMA tokens */
 187         .xSlicVpdLens = {                       /* VPD lengths */
 188                 0,0,0,                  /*  0 - 2 */
 189                 sizeof(xItExtVpdPanel), /*       3 Extended VPD   */
 190                 sizeof(struct paca_struct),     /*       4 length of Paca  */
 191                 0,                      /*       5 */
 192                 sizeof(struct ItIplParmsReal),/* 6 length of IPL parms */
 193                 26992,                  /*       7 length of MS VPD */
 194                 0,                      /*       8 */
 195                 sizeof(struct ItLpNaca),/*       9 length of LP Naca */
 196                 0,                      /*      10 */
 197                 256,                    /*      11 length of Recovery Log Buf */
 198                 sizeof(struct SpCommArea), /*   12 length of SP Comm Area */
 199                 0,0,0,                  /* 13 - 15 */
 200                 sizeof(struct IoHriProcessorVpd),/* 16 length of Proc Vpd */
 201                 0,0,0,0,0,0,            /* 17 - 22  */
 202                 sizeof(struct hvlpevent_queue), /* 23 length of Lp Queue */
 203                 0,0                     /* 24 - 25 */
 204                 },
 205         .xSlicVpdAdrs = {                       /* VPD addresses */
 206                 0,0,0,                  /*       0 -  2 */
 207                 &xItExtVpdPanel,        /*       3 Extended VPD */
 208                 &paca[0],               /*       4 first Paca */
 209                 0,                      /*       5 */
 210                 &xItIplParmsReal,       /*       6 IPL parms */
 211                 &xMsVpd,                /*       7 MS Vpd */
 212                 0,                      /*       8 */
 213                 &itLpNaca,              /*       9 LpNaca */
 214                 0,                      /*      10 */
 215                 &xRecoveryLogBuffer,    /*      11 Recovery Log Buffer */
 216                 &xSpCommArea,           /*      12 SP Comm Area */
 217                 0,0,0,                  /* 13 - 15 */
 218                 &xIoHriProcessorVpd,    /*      16 Proc Vpd */
 219                 0,0,0,0,0,0,            /* 17 - 22 */
 220                 &hvlpevent_queue,       /*      23 Lp Queue */
 221                 0,0
 222         }
 223 };
 224
 225 struct ItLpRegSave iseries_reg_save[] = {
 226         [0 ... (NR_CPUS-1)] = {
 227                 .xDesc = 0xd397d9e2,    /* "LpRS" */
 228                 .xSize = sizeof(struct ItLpRegSave),
 229         },
 230 };