arch/powerpc/platforms/iseries/pci.c

   1 /*
   2  * Copyright (C) 2001 Allan Trautman, IBM Corporation
   3  *
   4  * iSeries specific routines for PCI.
   5  *
   6  * Based on code from pci.c and iSeries_pci.c 32bit
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  21  */
  22 #include <linux/kernel.h>
  23 #include <linux/list.h>
  24 #include <linux/string.h>
  25 #include <linux/init.h>
  26 #include <linux/module.h>
  27 #include <linux/pci.h>
  28
  29 #include <asm/io.h>
  30 #include <asm/irq.h>
  31 #include <asm/prom.h>
  32 #include <asm/machdep.h>
  33 #include <asm/pci-bridge.h>
  34 #include <asm/iommu.h>
  35 #include <asm/abs_addr.h>
  36 #include <asm/firmware.h>
  37
  38 #include <asm/iseries/hv_call_xm.h>
  39 #include <asm/iseries/mf.h>
  40 #include <asm/iseries/iommu.h>
  41
  42 #include <asm/ppc-pci.h>
  43
  44 #include "irq.h"
  45 #include "pci.h"
  46 #include "call_pci.h"
  47
  48 #define PCI_RETRY_MAX   3
  49 static int limit_pci_retries = 1;       /* Set Retry Error on. */
  50
  51 /*
  52  * Table defines
  53  * Each Entry size is 4 MB * 1024 Entries = 4GB I/O address space.
  54  */
  55 #define IOMM_TABLE_MAX_ENTRIES  1024
  56 #define IOMM_TABLE_ENTRY_SIZE   0x0000000000400000UL
  57 #define BASE_IO_MEMORY          0xE000000000000000UL
  58
  59 static unsigned long max_io_memory = BASE_IO_MEMORY;
  60 static long current_iomm_table_entry;
  61
  62 /*
  63  * Lookup Tables.
  64  */
  65 static struct device_node *iomm_table[IOMM_TABLE_MAX_ENTRIES];
  66 static u8 iobar_table[IOMM_TABLE_MAX_ENTRIES];
  67
  68 static const char pci_io_text[] = "iSeries PCI I/O";
  69 static DEFINE_SPINLOCK(iomm_table_lock);
  70
  71 /*
  72  * iomm_table_allocate_entry
  73  *
  74  * Adds pci_dev entry in address translation table
  75  *
  76  * - Allocates the number of entries required in table base on BAR
  77  *   size.
  78  * - Allocates starting at BASE_IO_MEMORY and increases.
  79  * - The size is round up to be a multiple of entry size.
  80  * - CurrentIndex is incremented to keep track of the last entry.
  81  * - Builds the resource entry for allocated BARs.
  82  */
  83 static void __init iomm_table_allocate_entry(struct pci_dev *dev, int bar_num)
  84 {
  85         struct resource *bar_res = &dev->resource[bar_num];
  86         long bar_size = pci_resource_len(dev, bar_num);
  87
  88         /*
  89          * No space to allocate, quick exit, skip Allocation.
  90          */
  91         if (bar_size == 0)
  92                 return;
  93         /*
  94          * Set Resource values.
  95          */
  96         spin_lock(&iomm_table_lock);
  97         bar_res->name = pci_io_text;
  98         bar_res->start = BASE_IO_MEMORY +
  99                 IOMM_TABLE_ENTRY_SIZE * current_iomm_table_entry;
 100         bar_res->end = bar_res->start + bar_size - 1;
 101         /*
 102          * Allocate the number of table entries needed for BAR.
 103          */
 104         while (bar_size > 0 ) {
 105                 iomm_table[current_iomm_table_entry] = dev->sysdata;
 106                 iobar_table[current_iomm_table_entry] = bar_num;
 107                 bar_size -= IOMM_TABLE_ENTRY_SIZE;
 108                 ++current_iomm_table_entry;
 109         }
 110         max_io_memory = BASE_IO_MEMORY +
 111                 IOMM_TABLE_ENTRY_SIZE * current_iomm_table_entry;
 112         spin_unlock(&iomm_table_lock);
 113 }
 114
 115 /*
 116  * allocate_device_bars
 117  *
 118  * - Allocates ALL pci_dev BAR's and updates the resources with the
 119  *   BAR value.  BARS with zero length will have the resources
 120  *   The HvCallPci_getBarParms is used to get the size of the BAR
 121  *   space.  It calls iomm_table_allocate_entry to allocate
 122  *   each entry.
 123  * - Loops through The Bar resources(0 - 5) including the ROM
 124  *   is resource(6).
 125  */
 126 static void __init allocate_device_bars(struct pci_dev *dev)
 127 {
 128         int bar_num;
 129
 130         for (bar_num = 0; bar_num <= PCI_ROM_RESOURCE; ++bar_num)
 131                 iomm_table_allocate_entry(dev, bar_num);
 132 }
 133
 134 /*
 135  * Log error information to system console.
 136  * Filter out the device not there errors.
 137  * PCI: EADs Connect Failed 0x18.58.10 Rc: 0x00xx
 138  * PCI: Read Vendor Failed 0x18.58.10 Rc: 0x00xx
 139  * PCI: Connect Bus Unit Failed 0x18.58.10 Rc: 0x00xx
 140  */
 141 static void pci_log_error(char *error, int bus, int subbus,
 142                 int agent, int hv_res)
 143 {
 144         if (hv_res == 0x0302)
 145                 return;
 146         printk(KERN_ERR "PCI: %s Failed: 0x%02X.%02X.%02X Rc: 0x%04X",
 147                error, bus, subbus, agent, hv_res);
 148 }
 149
 150 /*
 151  * Look down the chain to find the matching Device Device
 152  */
 153 static struct device_node *find_device_node(int bus, int devfn)
 154 {
 155         struct device_node *node;
 156
 157         for (node = NULL; (node = of_find_all_nodes(node)); ) {
 158                 struct pci_dn *pdn = PCI_DN(node);
 159
 160                 if (pdn && (bus == pdn->busno) && (devfn == pdn->devfn))
 161                         return node;
 162         }
 163         return NULL;
 164 }
 165
 166 /*
 167  * iSeries_pci_final_fixup(void)
 168  */
 169 void __init iSeries_pci_final_fixup(void)
 170 {
 171         struct pci_dev *pdev = NULL;
 172         struct device_node *node;
 173         int num_dev = 0;
 174
 175         /* Fix up at the device node and pci_dev relationship */
 176         mf_display_src(0xC9000100);
 177
 178         printk("pcibios_final_fixup\n");
 179         for_each_pci_dev(pdev) {
 180                 struct pci_dn *pdn;
 181                 const u32 *agent;
 182
 183                 node = find_device_node(pdev->bus->number, pdev->devfn);
 184                 printk("pci dev %p (%x.%x), node %p\n", pdev,
 185                        pdev->bus->number, pdev->devfn, node);
 186                 if (!node) {
 187                         printk("PCI: Device Tree not found for 0x%016lX\n",
 188                                         (unsigned long)pdev);
 189                         continue;
 190                 }
 191
 192                 pdn = PCI_DN(node);
 193                 agent = of_get_property(node, "linux,agent-id", NULL);
 194                 if (pdn && agent) {
 195                         u8 irq = iSeries_allocate_IRQ(pdn->busno, 0,
 196                                         pdn->bussubno);
 197                         int err;
 198
 199                         err = HvCallXm_connectBusUnit(pdn->busno, pdn->bussubno,
 200                                         *agent, irq);
 201                         if (err)
 202                                 pci_log_error("Connect Bus Unit",
 203                                         pdn->busno, pdn->bussubno, *agent, err);
 204                         else {
 205                                 err = HvCallPci_configStore8(pdn->busno,
 206                                         pdn->bussubno, *agent,
 207                                         PCI_INTERRUPT_LINE, irq);
 208                                 if (err)
 209                                         pci_log_error("PciCfgStore Irq Failed!",
 210                                                 pdn->busno, pdn->bussubno,
 211                                                 *agent, err);
 212                                 else
 213                                         pdev->irq = irq;
 214                         }
 215                 }
 216
 217                 num_dev++;
 218                 pdev->sysdata = node;
 219                 PCI_DN(node)->pcidev = pdev;
 220                 allocate_device_bars(pdev);
 221                 iSeries_Device_Information(pdev, num_dev, pdn->busno,
 222                                 pdn->bussubno);
 223                 iommu_devnode_init_iSeries(pdev, node);
 224         }
 225         iSeries_activate_IRQs();
 226         mf_display_src(0xC9000200);
 227 }
 228
 229 /*
 230  * Config space read and write functions.
 231  * For now at least, we look for the device node for the bus and devfn
 232  * that we are asked to access.  It may be possible to translate the devfn
 233  * to a subbus and deviceid more directly.
 234  */
 235 static u64 hv_cfg_read_func[4]  = {
 236         HvCallPciConfigLoad8, HvCallPciConfigLoad16,
 237         HvCallPciConfigLoad32, HvCallPciConfigLoad32
 238 };
 239
 240 static u64 hv_cfg_write_func[4] = {
 241         HvCallPciConfigStore8, HvCallPciConfigStore16,
 242         HvCallPciConfigStore32, HvCallPciConfigStore32
 243 };
 244
 245 /*
 246  * Read PCI config space
 247  */
 248 static int iSeries_pci_read_config(struct pci_bus *bus, unsigned int devfn,
 249                 int offset, int size, u32 *val)
 250 {
 251         struct device_node *node = find_device_node(bus->number, devfn);
 252         u64 fn;
 253         struct HvCallPci_LoadReturn ret;
 254
 255         if (node == NULL)
 256                 return PCIBIOS_DEVICE_NOT_FOUND;
 257         if (offset > 255) {
 258                 *val = ~0;
 259                 return PCIBIOS_BAD_REGISTER_NUMBER;
 260         }
 261
 262         fn = hv_cfg_read_func[(size - 1) & 3];
 263         HvCall3Ret16(fn, &ret, iseries_ds_addr(node), offset, 0);
 264
 265         if (ret.rc != 0) {
 266                 *val = ~0;
 267                 return PCIBIOS_DEVICE_NOT_FOUND;        /* or something */
 268         }
 269
 270         *val = ret.value;
 271         return 0;
 272 }
 273
 274 /*
 275  * Write PCI config space
 276  */
 277
 278 static int iSeries_pci_write_config(struct pci_bus *bus, unsigned int devfn,
 279                 int offset, int size, u32 val)
 280 {
 281         struct device_node *node = find_device_node(bus->number, devfn);
 282         u64 fn;
 283         u64 ret;
 284
 285         if (node == NULL)
 286                 return PCIBIOS_DEVICE_NOT_FOUND;
 287         if (offset > 255)
 288                 return PCIBIOS_BAD_REGISTER_NUMBER;
 289
 290         fn = hv_cfg_write_func[(size - 1) & 3];
 291         ret = HvCall4(fn, iseries_ds_addr(node), offset, val, 0);
 292
 293         if (ret != 0)
 294                 return PCIBIOS_DEVICE_NOT_FOUND;
 295
 296         return 0;
 297 }
 298
 299 static struct pci_ops iSeries_pci_ops = {
 300         .read = iSeries_pci_read_config,
 301         .write = iSeries_pci_write_config
 302 };
 303
 304 /*
 305  * Check Return Code
 306  * -> On Failure, print and log information.
 307  *    Increment Retry Count, if exceeds max, panic partition.
 308  *
 309  * PCI: Device 23.90 ReadL I/O Error( 0): 0x1234
 310  * PCI: Device 23.90 ReadL Retry( 1)
 311  * PCI: Device 23.90 ReadL Retry Successful(1)
 312  */
 313 static int check_return_code(char *type, struct device_node *dn,
 314                 int *retry, u64 ret)
 315 {
 316         if (ret != 0)  {
 317                 struct pci_dn *pdn = PCI_DN(dn);
 318
 319                 (*retry)++;
 320                 printk("PCI: %s: Device 0x%04X:%02X  I/O Error(%2d): 0x%04X\n",
 321                                 type, pdn->busno, pdn->devfn,
 322                                 *retry, (int)ret);
 323                 /*
 324                  * Bump the retry and check for retry count exceeded.
 325                  * If, Exceeded, panic the system.
 326                  */
 327                 if (((*retry) > PCI_RETRY_MAX) &&
 328                                 (limit_pci_retries > 0)) {
 329                         mf_display_src(0xB6000103);
 330                         panic_timeout = 0;
 331                         panic("PCI: Hardware I/O Error, SRC B6000103, "
 332                                         "Automatic Reboot Disabled.\n");
 333                 }
 334                 return -1;      /* Retry Try */
 335         }
 336         return 0;
 337 }
 338
 339 /*
 340  * Translate the I/O Address into a device node, bar, and bar offset.
 341  * Note: Make sure the passed variable end up on the stack to avoid
 342  * the exposure of being device global.
 343  */
 344 static inline struct device_node *xlate_iomm_address(
 345                 const volatile void __iomem *addr,
 346                 u64 *dsaptr, u64 *bar_offset, const char *func)
 347 {
 348         unsigned long orig_addr;
 349         unsigned long base_addr;
 350         unsigned long ind;
 351         struct device_node *dn;
 352
 353         orig_addr = (unsigned long __force)addr;
 354         if ((orig_addr < BASE_IO_MEMORY) || (orig_addr >= max_io_memory)) {
 355                 static unsigned long last_jiffies;
 356                 static int num_printed;
 357
 358                 if ((jiffies - last_jiffies) > 60 * HZ) {
 359                         last_jiffies = jiffies;
 360                         num_printed = 0;
 361                 }
 362                 if (num_printed++ < 10)
 363                         printk(KERN_ERR
 364                                 "iSeries_%s: invalid access at IO address %p\n",
 365                                 func, addr);
 366                 return NULL;
 367         }
 368         base_addr = orig_addr - BASE_IO_MEMORY;
 369         ind = base_addr / IOMM_TABLE_ENTRY_SIZE;
 370         dn = iomm_table[ind];
 371
 372         if (dn != NULL) {
 373                 int barnum = iobar_table[ind];
 374                 *dsaptr = iseries_ds_addr(dn) | (barnum << 24);
 375                 *bar_offset = base_addr % IOMM_TABLE_ENTRY_SIZE;
 376         } else
 377                 panic("PCI: Invalid PCI IO address detected!\n");
 378         return dn;
 379 }
 380
 381 /*
 382  * Read MM I/O Instructions for the iSeries
 383  * On MM I/O error, all ones are returned and iSeries_pci_IoError is cal
 384  * else, data is returned in Big Endian format.
 385  */
 386 static u8 iseries_readb(const volatile void __iomem *addr)
 387 {
 388         u64 bar_offset;
 389         u64 dsa;
 390         int retry = 0;
 391         struct HvCallPci_LoadReturn ret;
 392         struct device_node *dn =
 393                 xlate_iomm_address(addr, &dsa, &bar_offset, "read_byte");
 394
 395         if (dn == NULL)
 396                 return 0xff;
 397         do {
 398                 HvCall3Ret16(HvCallPciBarLoad8, &ret, dsa, bar_offset, 0);
 399         } while (check_return_code("RDB", dn, &retry, ret.rc) != 0);
 400
 401         return ret.value;
 402 }
 403
 404 static u16 iseries_readw_be(const volatile void __iomem *addr)
 405 {
 406         u64 bar_offset;
 407         u64 dsa;
 408         int retry = 0;
 409         struct HvCallPci_LoadReturn ret;
 410         struct device_node *dn =
 411                 xlate_iomm_address(addr, &dsa, &bar_offset, "read_word");
 412
 413         if (dn == NULL)
 414                 return 0xffff;
 415         do {
 416                 HvCall3Ret16(HvCallPciBarLoad16, &ret, dsa,
 417                                 bar_offset, 0);
 418         } while (check_return_code("RDW", dn, &retry, ret.rc) != 0);
 419
 420         return ret.value;
 421 }
 422
 423 static u32 iseries_readl_be(const volatile void __iomem *addr)
 424 {
 425         u64 bar_offset;
 426         u64 dsa;
 427         int retry = 0;
 428         struct HvCallPci_LoadReturn ret;
 429         struct device_node *dn =
 430                 xlate_iomm_address(addr, &dsa, &bar_offset, "read_long");
 431
 432         if (dn == NULL)
 433                 return 0xffffffff;
 434         do {
 435                 HvCall3Ret16(HvCallPciBarLoad32, &ret, dsa,
 436                                 bar_offset, 0);
 437         } while (check_return_code("RDL", dn, &retry, ret.rc) != 0);
 438
 439         return ret.value;
 440 }
 441
 442 /*
 443  * Write MM I/O Instructions for the iSeries
 444  *
 445  */
 446 static void iseries_writeb(u8 data, volatile void __iomem *addr)
 447 {
 448         u64 bar_offset;
 449         u64 dsa;
 450         int retry = 0;
 451         u64 rc;
 452         struct device_node *dn =
 453                 xlate_iomm_address(addr, &dsa, &bar_offset, "write_byte");
 454
 455         if (dn == NULL)
 456                 return;
 457         do {
 458                 rc = HvCall4(HvCallPciBarStore8, dsa, bar_offset, data, 0);
 459         } while (check_return_code("WWB", dn, &retry, rc) != 0);
 460 }
 461
 462 static void iseries_writew_be(u16 data, volatile void __iomem *addr)
 463 {
 464         u64 bar_offset;
 465         u64 dsa;
 466         int retry = 0;
 467         u64 rc;
 468         struct device_node *dn =
 469                 xlate_iomm_address(addr, &dsa, &bar_offset, "write_word");
 470
 471         if (dn == NULL)
 472                 return;
 473         do {
 474                 rc = HvCall4(HvCallPciBarStore16, dsa, bar_offset, data, 0);
 475         } while (check_return_code("WWW", dn, &retry, rc) != 0);
 476 }
 477
 478 static void iseries_writel_be(u32 data, volatile void __iomem *addr)
 479 {
 480         u64 bar_offset;
 481         u64 dsa;
 482         int retry = 0;
 483         u64 rc;
 484         struct device_node *dn =
 485                 xlate_iomm_address(addr, &dsa, &bar_offset, "write_long");
 486
 487         if (dn == NULL)
 488                 return;
 489         do {
 490                 rc = HvCall4(HvCallPciBarStore32, dsa, bar_offset, data, 0);
 491         } while (check_return_code("WWL", dn, &retry, rc) != 0);
 492 }
 493
 494 static u16 iseries_readw(const volatile void __iomem *addr)
 495 {
 496         return le16_to_cpu(iseries_readw_be(addr));
 497 }
 498
 499 static u32 iseries_readl(const volatile void __iomem *addr)
 500 {
 501         return le32_to_cpu(iseries_readl_be(addr));
 502 }
 503
 504 static void iseries_writew(u16 data, volatile void __iomem *addr)
 505 {
 506         iseries_writew_be(cpu_to_le16(data), addr);
 507 }
 508
 509 static void iseries_writel(u32 data, volatile void __iomem *addr)
 510 {
 511         iseries_writel(cpu_to_le32(data), addr);
 512 }
 513
 514 static void iseries_readsb(const volatile void __iomem *addr, void *buf,
 515                            unsigned long count)
 516 {
 517         u8 *dst = buf;
 518         while(count-- > 0)
 519                 *(dst++) = iseries_readb(addr);
 520 }
 521
 522 static void iseries_readsw(const volatile void __iomem *addr, void *buf,
 523                            unsigned long count)
 524 {
 525         u16 *dst = buf;
 526         while(count-- > 0)
 527                 *(dst++) = iseries_readw_be(addr);
 528 }
 529
 530 static void iseries_readsl(const volatile void __iomem *addr, void *buf,
 531                            unsigned long count)
 532 {
 533         u32 *dst = buf;
 534         while(count-- > 0)
 535                 *(dst++) = iseries_readl_be(addr);
 536 }
 537
 538 static void iseries_writesb(volatile void __iomem *addr, const void *buf,
 539                             unsigned long count)
 540 {
 541         const u8 *src = buf;
 542         while(count-- > 0)
 543                 iseries_writeb(*(src++), addr);
 544 }
 545
 546 static void iseries_writesw(volatile void __iomem *addr, const void *buf,
 547                             unsigned long count)
 548 {
 549         const u16 *src = buf;
 550         while(count-- > 0)
 551                 iseries_writew_be(*(src++), addr);
 552 }
 553
 554 static void iseries_writesl(volatile void __iomem *addr, const void *buf,
 555                             unsigned long count)
 556 {
 557         const u32 *src = buf;
 558         while(count-- > 0)
 559                 iseries_writel_be(*(src++), addr);
 560 }
 561
 562 static void iseries_memset_io(volatile void __iomem *addr, int c,
 563                               unsigned long n)
 564 {
 565         volatile char __iomem *d = addr;
 566
 567         while (n-- > 0)
 568                 iseries_writeb(c, d++);
 569 }
 570
 571 static void iseries_memcpy_fromio(void *dest, const volatile void __iomem *src,
 572                                   unsigned long n)
 573 {
 574         char *d = dest;
 575         const volatile char __iomem *s = src;
 576
 577         while (n-- > 0)
 578                 *d++ = iseries_readb(s++);
 579 }
 580
 581 static void iseries_memcpy_toio(volatile void __iomem *dest, const void *src,
 582                                 unsigned long n)
 583 {
 584         const char *s = src;
 585         volatile char __iomem *d = dest;
 586
 587         while (n-- > 0)
 588                 iseries_writeb(*s++, d++);
 589 }
 590
 591 /* We only set MMIO ops. The default PIO ops will be default
 592  * to the MMIO ops + pci_io_base which is 0 on iSeries as
 593  * expected so both should work.
 594  *
 595  * Note that we don't implement the readq/writeq versions as
 596  * I don't know of an HV call for doing so. Thus, the default
 597  * operation will be used instead, which will fault a the value
 598  * return by iSeries for MMIO addresses always hits a non mapped
 599  * area. This is as good as the BUG() we used to have there.
 600  */
 601 static struct ppc_pci_io __initdata iseries_pci_io = {
 602         .readb = iseries_readb,
 603         .readw = iseries_readw,
 604         .readl = iseries_readl,
 605         .readw_be = iseries_readw_be,
 606         .readl_be = iseries_readl_be,
 607         .writeb = iseries_writeb,
 608         .writew = iseries_writew,
 609         .writel = iseries_writel,
 610         .writew_be = iseries_writew_be,
 611         .writel_be = iseries_writel_be,
 612         .readsb = iseries_readsb,
 613         .readsw = iseries_readsw,
 614         .readsl = iseries_readsl,
 615         .writesb = iseries_writesb,
 616         .writesw = iseries_writesw,
 617         .writesl = iseries_writesl,
 618         .memset_io = iseries_memset_io,
 619         .memcpy_fromio = iseries_memcpy_fromio,
 620         .memcpy_toio = iseries_memcpy_toio,
 621 };
 622
 623 /*
 624  * iSeries_pcibios_init
 625  *
 626  * Description:
 627  *   This function checks for all possible system PCI host bridges that connect
 628  *   PCI buses.  The system hypervisor is queried as to the guest partition
 629  *   ownership status.  A pci_controller is built for any bus which is partially
 630  *   owned or fully owned by this guest partition.
 631  */
 632 void __init iSeries_pcibios_init(void)
 633 {
 634         struct pci_controller *phb;
 635         struct device_node *root = of_find_node_by_path("/");
 636         struct device_node *node = NULL;
 637
 638         /* Install IO hooks */
 639         ppc_pci_io = iseries_pci_io;
 640
 641         /* iSeries has no IO space in the common sense, it needs to set
 642          * the IO base to 0
 643          */
 644         pci_io_base = 0;
 645
 646         if (root == NULL) {
 647                 printk(KERN_CRIT "iSeries_pcibios_init: can't find root "
 648                                 "of device tree\n");
 649                 return;
 650         }
 651         while ((node = of_get_next_child(root, node)) != NULL) {
 652                 HvBusNumber bus;
 653                 const u32 *busp;
 654
 655                 if ((node->type == NULL) || (strcmp(node->type, "pci") != 0))
 656                         continue;
 657
 658                 busp = of_get_property(node, "bus-range", NULL);
 659                 if (busp == NULL)
 660                         continue;
 661                 bus = *busp;
 662                 printk("bus %d appears to exist\n", bus);
 663                 phb = pcibios_alloc_controller(node);
 664                 if (phb == NULL)
 665                         continue;
 666
 667                 phb->pci_mem_offset = bus;
 668                 phb->first_busno = bus;
 669                 phb->last_busno = bus;
 670                 phb->ops = &iSeries_pci_ops;
 671         }
 672
 673         of_node_put(root);
 674
 675         pci_devs_phb_init();
 676 }
 677