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[PATCH] powerpc: Experimental support for new G5 Macs (#2)
[deliverable/linux.git] / arch / powerpc / platforms / powermac / feature.c
1 /*
2 * arch/ppc/platforms/pmac_feature.c
3 *
4 * Copyright (C) 1996-2001 Paul Mackerras (paulus@cs.anu.edu.au)
5 * Ben. Herrenschmidt (benh@kernel.crashing.org)
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 *
12 * TODO:
13 *
14 * - Replace mdelay with some schedule loop if possible
15 * - Shorten some obfuscated delays on some routines (like modem
16 * power)
17 * - Refcount some clocks (see darwin)
18 * - Split split split...
19 *
20 */
21 #include <linux/config.h>
22 #include <linux/types.h>
23 #include <linux/init.h>
24 #include <linux/delay.h>
25 #include <linux/kernel.h>
26 #include <linux/sched.h>
27 #include <linux/spinlock.h>
28 #include <linux/adb.h>
29 #include <linux/pmu.h>
30 #include <linux/ioport.h>
31 #include <linux/pci.h>
32 #include <asm/sections.h>
33 #include <asm/errno.h>
34 #include <asm/ohare.h>
35 #include <asm/heathrow.h>
36 #include <asm/keylargo.h>
37 #include <asm/uninorth.h>
38 #include <asm/io.h>
39 #include <asm/prom.h>
40 #include <asm/machdep.h>
41 #include <asm/pmac_feature.h>
42 #include <asm/dbdma.h>
43 #include <asm/pci-bridge.h>
44 #include <asm/pmac_low_i2c.h>
45
46 #undef DEBUG_FEATURE
47
48 #ifdef DEBUG_FEATURE
49 #define DBG(fmt...) printk(KERN_DEBUG fmt)
50 #else
51 #define DBG(fmt...)
52 #endif
53
54 #ifdef CONFIG_6xx
55 extern int powersave_lowspeed;
56 #endif
57
58 extern int powersave_nap;
59 extern struct device_node *k2_skiplist[2];
60
61
62 /*
63 * We use a single global lock to protect accesses. Each driver has
64 * to take care of its own locking
65 */
66 static DEFINE_SPINLOCK(feature_lock);
67
68 #define LOCK(flags) spin_lock_irqsave(&feature_lock, flags);
69 #define UNLOCK(flags) spin_unlock_irqrestore(&feature_lock, flags);
70
71
72 /*
73 * Instance of some macio stuffs
74 */
75 struct macio_chip macio_chips[MAX_MACIO_CHIPS];
76
77 struct macio_chip *macio_find(struct device_node *child, int type)
78 {
79 while(child) {
80 int i;
81
82 for (i=0; i < MAX_MACIO_CHIPS && macio_chips[i].of_node; i++)
83 if (child == macio_chips[i].of_node &&
84 (!type || macio_chips[i].type == type))
85 return &macio_chips[i];
86 child = child->parent;
87 }
88 return NULL;
89 }
90 EXPORT_SYMBOL_GPL(macio_find);
91
92 static const char *macio_names[] =
93 {
94 "Unknown",
95 "Grand Central",
96 "OHare",
97 "OHareII",
98 "Heathrow",
99 "Gatwick",
100 "Paddington",
101 "Keylargo",
102 "Pangea",
103 "Intrepid",
104 "K2",
105 "Shasta",
106 };
107
108
109
110 /*
111 * Uninorth reg. access. Note that Uni-N regs are big endian
112 */
113
114 #define UN_REG(r) (uninorth_base + ((r) >> 2))
115 #define UN_IN(r) (in_be32(UN_REG(r)))
116 #define UN_OUT(r,v) (out_be32(UN_REG(r), (v)))
117 #define UN_BIS(r,v) (UN_OUT((r), UN_IN(r) | (v)))
118 #define UN_BIC(r,v) (UN_OUT((r), UN_IN(r) & ~(v)))
119
120 static struct device_node *uninorth_node;
121 static u32 __iomem *uninorth_base;
122 static u32 uninorth_rev;
123 static int uninorth_maj;
124 static void __iomem *u3_ht;
125
126 /*
127 * For each motherboard family, we have a table of functions pointers
128 * that handle the various features.
129 */
130
131 typedef long (*feature_call)(struct device_node *node, long param, long value);
132
133 struct feature_table_entry {
134 unsigned int selector;
135 feature_call function;
136 };
137
138 struct pmac_mb_def
139 {
140 const char* model_string;
141 const char* model_name;
142 int model_id;
143 struct feature_table_entry* features;
144 unsigned long board_flags;
145 };
146 static struct pmac_mb_def pmac_mb;
147
148 /*
149 * Here are the chip specific feature functions
150 */
151
152 static inline int simple_feature_tweak(struct device_node *node, int type,
153 int reg, u32 mask, int value)
154 {
155 struct macio_chip* macio;
156 unsigned long flags;
157
158 macio = macio_find(node, type);
159 if (!macio)
160 return -ENODEV;
161 LOCK(flags);
162 if (value)
163 MACIO_BIS(reg, mask);
164 else
165 MACIO_BIC(reg, mask);
166 (void)MACIO_IN32(reg);
167 UNLOCK(flags);
168
169 return 0;
170 }
171
172 #ifndef CONFIG_POWER4
173
174 static long ohare_htw_scc_enable(struct device_node *node, long param,
175 long value)
176 {
177 struct macio_chip* macio;
178 unsigned long chan_mask;
179 unsigned long fcr;
180 unsigned long flags;
181 int htw, trans;
182 unsigned long rmask;
183
184 macio = macio_find(node, 0);
185 if (!macio)
186 return -ENODEV;
187 if (!strcmp(node->name, "ch-a"))
188 chan_mask = MACIO_FLAG_SCCA_ON;
189 else if (!strcmp(node->name, "ch-b"))
190 chan_mask = MACIO_FLAG_SCCB_ON;
191 else
192 return -ENODEV;
193
194 htw = (macio->type == macio_heathrow || macio->type == macio_paddington
195 || macio->type == macio_gatwick);
196 /* On these machines, the HRW_SCC_TRANS_EN_N bit mustn't be touched */
197 trans = (pmac_mb.model_id != PMAC_TYPE_YOSEMITE &&
198 pmac_mb.model_id != PMAC_TYPE_YIKES);
199 if (value) {
200 #ifdef CONFIG_ADB_PMU
201 if ((param & 0xfff) == PMAC_SCC_IRDA)
202 pmu_enable_irled(1);
203 #endif /* CONFIG_ADB_PMU */
204 LOCK(flags);
205 fcr = MACIO_IN32(OHARE_FCR);
206 /* Check if scc cell need enabling */
207 if (!(fcr & OH_SCC_ENABLE)) {
208 fcr |= OH_SCC_ENABLE;
209 if (htw) {
210 /* Side effect: this will also power up the
211 * modem, but it's too messy to figure out on which
212 * ports this controls the tranceiver and on which
213 * it controls the modem
214 */
215 if (trans)
216 fcr &= ~HRW_SCC_TRANS_EN_N;
217 MACIO_OUT32(OHARE_FCR, fcr);
218 fcr |= (rmask = HRW_RESET_SCC);
219 MACIO_OUT32(OHARE_FCR, fcr);
220 } else {
221 fcr |= (rmask = OH_SCC_RESET);
222 MACIO_OUT32(OHARE_FCR, fcr);
223 }
224 UNLOCK(flags);
225 (void)MACIO_IN32(OHARE_FCR);
226 mdelay(15);
227 LOCK(flags);
228 fcr &= ~rmask;
229 MACIO_OUT32(OHARE_FCR, fcr);
230 }
231 if (chan_mask & MACIO_FLAG_SCCA_ON)
232 fcr |= OH_SCCA_IO;
233 if (chan_mask & MACIO_FLAG_SCCB_ON)
234 fcr |= OH_SCCB_IO;
235 MACIO_OUT32(OHARE_FCR, fcr);
236 macio->flags |= chan_mask;
237 UNLOCK(flags);
238 if (param & PMAC_SCC_FLAG_XMON)
239 macio->flags |= MACIO_FLAG_SCC_LOCKED;
240 } else {
241 if (macio->flags & MACIO_FLAG_SCC_LOCKED)
242 return -EPERM;
243 LOCK(flags);
244 fcr = MACIO_IN32(OHARE_FCR);
245 if (chan_mask & MACIO_FLAG_SCCA_ON)
246 fcr &= ~OH_SCCA_IO;
247 if (chan_mask & MACIO_FLAG_SCCB_ON)
248 fcr &= ~OH_SCCB_IO;
249 MACIO_OUT32(OHARE_FCR, fcr);
250 if ((fcr & (OH_SCCA_IO | OH_SCCB_IO)) == 0) {
251 fcr &= ~OH_SCC_ENABLE;
252 if (htw && trans)
253 fcr |= HRW_SCC_TRANS_EN_N;
254 MACIO_OUT32(OHARE_FCR, fcr);
255 }
256 macio->flags &= ~(chan_mask);
257 UNLOCK(flags);
258 mdelay(10);
259 #ifdef CONFIG_ADB_PMU
260 if ((param & 0xfff) == PMAC_SCC_IRDA)
261 pmu_enable_irled(0);
262 #endif /* CONFIG_ADB_PMU */
263 }
264 return 0;
265 }
266
267 static long ohare_floppy_enable(struct device_node *node, long param,
268 long value)
269 {
270 return simple_feature_tweak(node, macio_ohare,
271 OHARE_FCR, OH_FLOPPY_ENABLE, value);
272 }
273
274 static long ohare_mesh_enable(struct device_node *node, long param, long value)
275 {
276 return simple_feature_tweak(node, macio_ohare,
277 OHARE_FCR, OH_MESH_ENABLE, value);
278 }
279
280 static long ohare_ide_enable(struct device_node *node, long param, long value)
281 {
282 switch(param) {
283 case 0:
284 /* For some reason, setting the bit in set_initial_features()
285 * doesn't stick. I'm still investigating... --BenH.
286 */
287 if (value)
288 simple_feature_tweak(node, macio_ohare,
289 OHARE_FCR, OH_IOBUS_ENABLE, 1);
290 return simple_feature_tweak(node, macio_ohare,
291 OHARE_FCR, OH_IDE0_ENABLE, value);
292 case 1:
293 return simple_feature_tweak(node, macio_ohare,
294 OHARE_FCR, OH_BAY_IDE_ENABLE, value);
295 default:
296 return -ENODEV;
297 }
298 }
299
300 static long ohare_ide_reset(struct device_node *node, long param, long value)
301 {
302 switch(param) {
303 case 0:
304 return simple_feature_tweak(node, macio_ohare,
305 OHARE_FCR, OH_IDE0_RESET_N, !value);
306 case 1:
307 return simple_feature_tweak(node, macio_ohare,
308 OHARE_FCR, OH_IDE1_RESET_N, !value);
309 default:
310 return -ENODEV;
311 }
312 }
313
314 static long ohare_sleep_state(struct device_node *node, long param, long value)
315 {
316 struct macio_chip* macio = &macio_chips[0];
317
318 if ((pmac_mb.board_flags & PMAC_MB_CAN_SLEEP) == 0)
319 return -EPERM;
320 if (value == 1) {
321 MACIO_BIC(OHARE_FCR, OH_IOBUS_ENABLE);
322 } else if (value == 0) {
323 MACIO_BIS(OHARE_FCR, OH_IOBUS_ENABLE);
324 }
325
326 return 0;
327 }
328
329 static long heathrow_modem_enable(struct device_node *node, long param,
330 long value)
331 {
332 struct macio_chip* macio;
333 u8 gpio;
334 unsigned long flags;
335
336 macio = macio_find(node, macio_unknown);
337 if (!macio)
338 return -ENODEV;
339 gpio = MACIO_IN8(HRW_GPIO_MODEM_RESET) & ~1;
340 if (!value) {
341 LOCK(flags);
342 MACIO_OUT8(HRW_GPIO_MODEM_RESET, gpio);
343 UNLOCK(flags);
344 (void)MACIO_IN8(HRW_GPIO_MODEM_RESET);
345 mdelay(250);
346 }
347 if (pmac_mb.model_id != PMAC_TYPE_YOSEMITE &&
348 pmac_mb.model_id != PMAC_TYPE_YIKES) {
349 LOCK(flags);
350 if (value)
351 MACIO_BIC(HEATHROW_FCR, HRW_SCC_TRANS_EN_N);
352 else
353 MACIO_BIS(HEATHROW_FCR, HRW_SCC_TRANS_EN_N);
354 UNLOCK(flags);
355 (void)MACIO_IN32(HEATHROW_FCR);
356 mdelay(250);
357 }
358 if (value) {
359 LOCK(flags);
360 MACIO_OUT8(HRW_GPIO_MODEM_RESET, gpio | 1);
361 (void)MACIO_IN8(HRW_GPIO_MODEM_RESET);
362 UNLOCK(flags); mdelay(250); LOCK(flags);
363 MACIO_OUT8(HRW_GPIO_MODEM_RESET, gpio);
364 (void)MACIO_IN8(HRW_GPIO_MODEM_RESET);
365 UNLOCK(flags); mdelay(250); LOCK(flags);
366 MACIO_OUT8(HRW_GPIO_MODEM_RESET, gpio | 1);
367 (void)MACIO_IN8(HRW_GPIO_MODEM_RESET);
368 UNLOCK(flags); mdelay(250);
369 }
370 return 0;
371 }
372
373 static long heathrow_floppy_enable(struct device_node *node, long param,
374 long value)
375 {
376 return simple_feature_tweak(node, macio_unknown,
377 HEATHROW_FCR,
378 HRW_SWIM_ENABLE|HRW_BAY_FLOPPY_ENABLE,
379 value);
380 }
381
382 static long heathrow_mesh_enable(struct device_node *node, long param,
383 long value)
384 {
385 struct macio_chip* macio;
386 unsigned long flags;
387
388 macio = macio_find(node, macio_unknown);
389 if (!macio)
390 return -ENODEV;
391 LOCK(flags);
392 /* Set clear mesh cell enable */
393 if (value)
394 MACIO_BIS(HEATHROW_FCR, HRW_MESH_ENABLE);
395 else
396 MACIO_BIC(HEATHROW_FCR, HRW_MESH_ENABLE);
397 (void)MACIO_IN32(HEATHROW_FCR);
398 udelay(10);
399 /* Set/Clear termination power */
400 if (value)
401 MACIO_BIC(HEATHROW_MBCR, 0x04000000);
402 else
403 MACIO_BIS(HEATHROW_MBCR, 0x04000000);
404 (void)MACIO_IN32(HEATHROW_MBCR);
405 udelay(10);
406 UNLOCK(flags);
407
408 return 0;
409 }
410
411 static long heathrow_ide_enable(struct device_node *node, long param,
412 long value)
413 {
414 switch(param) {
415 case 0:
416 return simple_feature_tweak(node, macio_unknown,
417 HEATHROW_FCR, HRW_IDE0_ENABLE, value);
418 case 1:
419 return simple_feature_tweak(node, macio_unknown,
420 HEATHROW_FCR, HRW_BAY_IDE_ENABLE, value);
421 default:
422 return -ENODEV;
423 }
424 }
425
426 static long heathrow_ide_reset(struct device_node *node, long param,
427 long value)
428 {
429 switch(param) {
430 case 0:
431 return simple_feature_tweak(node, macio_unknown,
432 HEATHROW_FCR, HRW_IDE0_RESET_N, !value);
433 case 1:
434 return simple_feature_tweak(node, macio_unknown,
435 HEATHROW_FCR, HRW_IDE1_RESET_N, !value);
436 default:
437 return -ENODEV;
438 }
439 }
440
441 static long heathrow_bmac_enable(struct device_node *node, long param,
442 long value)
443 {
444 struct macio_chip* macio;
445 unsigned long flags;
446
447 macio = macio_find(node, 0);
448 if (!macio)
449 return -ENODEV;
450 if (value) {
451 LOCK(flags);
452 MACIO_BIS(HEATHROW_FCR, HRW_BMAC_IO_ENABLE);
453 MACIO_BIS(HEATHROW_FCR, HRW_BMAC_RESET);
454 UNLOCK(flags);
455 (void)MACIO_IN32(HEATHROW_FCR);
456 mdelay(10);
457 LOCK(flags);
458 MACIO_BIC(HEATHROW_FCR, HRW_BMAC_RESET);
459 UNLOCK(flags);
460 (void)MACIO_IN32(HEATHROW_FCR);
461 mdelay(10);
462 } else {
463 LOCK(flags);
464 MACIO_BIC(HEATHROW_FCR, HRW_BMAC_IO_ENABLE);
465 UNLOCK(flags);
466 }
467 return 0;
468 }
469
470 static long heathrow_sound_enable(struct device_node *node, long param,
471 long value)
472 {
473 struct macio_chip* macio;
474 unsigned long flags;
475
476 /* B&W G3 and Yikes don't support that properly (the
477 * sound appear to never come back after beeing shut down).
478 */
479 if (pmac_mb.model_id == PMAC_TYPE_YOSEMITE ||
480 pmac_mb.model_id == PMAC_TYPE_YIKES)
481 return 0;
482
483 macio = macio_find(node, 0);
484 if (!macio)
485 return -ENODEV;
486 if (value) {
487 LOCK(flags);
488 MACIO_BIS(HEATHROW_FCR, HRW_SOUND_CLK_ENABLE);
489 MACIO_BIC(HEATHROW_FCR, HRW_SOUND_POWER_N);
490 UNLOCK(flags);
491 (void)MACIO_IN32(HEATHROW_FCR);
492 } else {
493 LOCK(flags);
494 MACIO_BIS(HEATHROW_FCR, HRW_SOUND_POWER_N);
495 MACIO_BIC(HEATHROW_FCR, HRW_SOUND_CLK_ENABLE);
496 UNLOCK(flags);
497 }
498 return 0;
499 }
500
501 static u32 save_fcr[6];
502 static u32 save_mbcr;
503 static u32 save_gpio_levels[2];
504 static u8 save_gpio_extint[KEYLARGO_GPIO_EXTINT_CNT];
505 static u8 save_gpio_normal[KEYLARGO_GPIO_CNT];
506 static u32 save_unin_clock_ctl;
507 static struct dbdma_regs save_dbdma[13];
508 static struct dbdma_regs save_alt_dbdma[13];
509
510 static void dbdma_save(struct macio_chip *macio, struct dbdma_regs *save)
511 {
512 int i;
513
514 /* Save state & config of DBDMA channels */
515 for (i = 0; i < 13; i++) {
516 volatile struct dbdma_regs __iomem * chan = (void __iomem *)
517 (macio->base + ((0x8000+i*0x100)>>2));
518 save[i].cmdptr_hi = in_le32(&chan->cmdptr_hi);
519 save[i].cmdptr = in_le32(&chan->cmdptr);
520 save[i].intr_sel = in_le32(&chan->intr_sel);
521 save[i].br_sel = in_le32(&chan->br_sel);
522 save[i].wait_sel = in_le32(&chan->wait_sel);
523 }
524 }
525
526 static void dbdma_restore(struct macio_chip *macio, struct dbdma_regs *save)
527 {
528 int i;
529
530 /* Save state & config of DBDMA channels */
531 for (i = 0; i < 13; i++) {
532 volatile struct dbdma_regs __iomem * chan = (void __iomem *)
533 (macio->base + ((0x8000+i*0x100)>>2));
534 out_le32(&chan->control, (ACTIVE|DEAD|WAKE|FLUSH|PAUSE|RUN)<<16);
535 while (in_le32(&chan->status) & ACTIVE)
536 mb();
537 out_le32(&chan->cmdptr_hi, save[i].cmdptr_hi);
538 out_le32(&chan->cmdptr, save[i].cmdptr);
539 out_le32(&chan->intr_sel, save[i].intr_sel);
540 out_le32(&chan->br_sel, save[i].br_sel);
541 out_le32(&chan->wait_sel, save[i].wait_sel);
542 }
543 }
544
545 static void heathrow_sleep(struct macio_chip *macio, int secondary)
546 {
547 if (secondary) {
548 dbdma_save(macio, save_alt_dbdma);
549 save_fcr[2] = MACIO_IN32(0x38);
550 save_fcr[3] = MACIO_IN32(0x3c);
551 } else {
552 dbdma_save(macio, save_dbdma);
553 save_fcr[0] = MACIO_IN32(0x38);
554 save_fcr[1] = MACIO_IN32(0x3c);
555 save_mbcr = MACIO_IN32(0x34);
556 /* Make sure sound is shut down */
557 MACIO_BIS(HEATHROW_FCR, HRW_SOUND_POWER_N);
558 MACIO_BIC(HEATHROW_FCR, HRW_SOUND_CLK_ENABLE);
559 /* This seems to be necessary as well or the fan
560 * keeps coming up and battery drains fast */
561 MACIO_BIC(HEATHROW_FCR, HRW_IOBUS_ENABLE);
562 MACIO_BIC(HEATHROW_FCR, HRW_IDE0_RESET_N);
563 /* Make sure eth is down even if module or sleep
564 * won't work properly */
565 MACIO_BIC(HEATHROW_FCR, HRW_BMAC_IO_ENABLE | HRW_BMAC_RESET);
566 }
567 /* Make sure modem is shut down */
568 MACIO_OUT8(HRW_GPIO_MODEM_RESET,
569 MACIO_IN8(HRW_GPIO_MODEM_RESET) & ~1);
570 MACIO_BIS(HEATHROW_FCR, HRW_SCC_TRANS_EN_N);
571 MACIO_BIC(HEATHROW_FCR, OH_SCCA_IO|OH_SCCB_IO|HRW_SCC_ENABLE);
572
573 /* Let things settle */
574 (void)MACIO_IN32(HEATHROW_FCR);
575 }
576
577 static void heathrow_wakeup(struct macio_chip *macio, int secondary)
578 {
579 if (secondary) {
580 MACIO_OUT32(0x38, save_fcr[2]);
581 (void)MACIO_IN32(0x38);
582 mdelay(1);
583 MACIO_OUT32(0x3c, save_fcr[3]);
584 (void)MACIO_IN32(0x38);
585 mdelay(10);
586 dbdma_restore(macio, save_alt_dbdma);
587 } else {
588 MACIO_OUT32(0x38, save_fcr[0] | HRW_IOBUS_ENABLE);
589 (void)MACIO_IN32(0x38);
590 mdelay(1);
591 MACIO_OUT32(0x3c, save_fcr[1]);
592 (void)MACIO_IN32(0x38);
593 mdelay(1);
594 MACIO_OUT32(0x34, save_mbcr);
595 (void)MACIO_IN32(0x38);
596 mdelay(10);
597 dbdma_restore(macio, save_dbdma);
598 }
599 }
600
601 static long heathrow_sleep_state(struct device_node *node, long param,
602 long value)
603 {
604 if ((pmac_mb.board_flags & PMAC_MB_CAN_SLEEP) == 0)
605 return -EPERM;
606 if (value == 1) {
607 if (macio_chips[1].type == macio_gatwick)
608 heathrow_sleep(&macio_chips[0], 1);
609 heathrow_sleep(&macio_chips[0], 0);
610 } else if (value == 0) {
611 heathrow_wakeup(&macio_chips[0], 0);
612 if (macio_chips[1].type == macio_gatwick)
613 heathrow_wakeup(&macio_chips[0], 1);
614 }
615 return 0;
616 }
617
618 static long core99_scc_enable(struct device_node *node, long param, long value)
619 {
620 struct macio_chip* macio;
621 unsigned long flags;
622 unsigned long chan_mask;
623 u32 fcr;
624
625 macio = macio_find(node, 0);
626 if (!macio)
627 return -ENODEV;
628 if (!strcmp(node->name, "ch-a"))
629 chan_mask = MACIO_FLAG_SCCA_ON;
630 else if (!strcmp(node->name, "ch-b"))
631 chan_mask = MACIO_FLAG_SCCB_ON;
632 else
633 return -ENODEV;
634
635 if (value) {
636 int need_reset_scc = 0;
637 int need_reset_irda = 0;
638
639 LOCK(flags);
640 fcr = MACIO_IN32(KEYLARGO_FCR0);
641 /* Check if scc cell need enabling */
642 if (!(fcr & KL0_SCC_CELL_ENABLE)) {
643 fcr |= KL0_SCC_CELL_ENABLE;
644 need_reset_scc = 1;
645 }
646 if (chan_mask & MACIO_FLAG_SCCA_ON) {
647 fcr |= KL0_SCCA_ENABLE;
648 /* Don't enable line drivers for I2S modem */
649 if ((param & 0xfff) == PMAC_SCC_I2S1)
650 fcr &= ~KL0_SCC_A_INTF_ENABLE;
651 else
652 fcr |= KL0_SCC_A_INTF_ENABLE;
653 }
654 if (chan_mask & MACIO_FLAG_SCCB_ON) {
655 fcr |= KL0_SCCB_ENABLE;
656 /* Perform irda specific inits */
657 if ((param & 0xfff) == PMAC_SCC_IRDA) {
658 fcr &= ~KL0_SCC_B_INTF_ENABLE;
659 fcr |= KL0_IRDA_ENABLE;
660 fcr |= KL0_IRDA_CLK32_ENABLE | KL0_IRDA_CLK19_ENABLE;
661 fcr |= KL0_IRDA_SOURCE1_SEL;
662 fcr &= ~(KL0_IRDA_FAST_CONNECT|KL0_IRDA_DEFAULT1|KL0_IRDA_DEFAULT0);
663 fcr &= ~(KL0_IRDA_SOURCE2_SEL|KL0_IRDA_HIGH_BAND);
664 need_reset_irda = 1;
665 } else
666 fcr |= KL0_SCC_B_INTF_ENABLE;
667 }
668 MACIO_OUT32(KEYLARGO_FCR0, fcr);
669 macio->flags |= chan_mask;
670 if (need_reset_scc) {
671 MACIO_BIS(KEYLARGO_FCR0, KL0_SCC_RESET);
672 (void)MACIO_IN32(KEYLARGO_FCR0);
673 UNLOCK(flags);
674 mdelay(15);
675 LOCK(flags);
676 MACIO_BIC(KEYLARGO_FCR0, KL0_SCC_RESET);
677 }
678 if (need_reset_irda) {
679 MACIO_BIS(KEYLARGO_FCR0, KL0_IRDA_RESET);
680 (void)MACIO_IN32(KEYLARGO_FCR0);
681 UNLOCK(flags);
682 mdelay(15);
683 LOCK(flags);
684 MACIO_BIC(KEYLARGO_FCR0, KL0_IRDA_RESET);
685 }
686 UNLOCK(flags);
687 if (param & PMAC_SCC_FLAG_XMON)
688 macio->flags |= MACIO_FLAG_SCC_LOCKED;
689 } else {
690 if (macio->flags & MACIO_FLAG_SCC_LOCKED)
691 return -EPERM;
692 LOCK(flags);
693 fcr = MACIO_IN32(KEYLARGO_FCR0);
694 if (chan_mask & MACIO_FLAG_SCCA_ON)
695 fcr &= ~KL0_SCCA_ENABLE;
696 if (chan_mask & MACIO_FLAG_SCCB_ON) {
697 fcr &= ~KL0_SCCB_ENABLE;
698 /* Perform irda specific clears */
699 if ((param & 0xfff) == PMAC_SCC_IRDA) {
700 fcr &= ~KL0_IRDA_ENABLE;
701 fcr &= ~(KL0_IRDA_CLK32_ENABLE | KL0_IRDA_CLK19_ENABLE);
702 fcr &= ~(KL0_IRDA_FAST_CONNECT|KL0_IRDA_DEFAULT1|KL0_IRDA_DEFAULT0);
703 fcr &= ~(KL0_IRDA_SOURCE1_SEL|KL0_IRDA_SOURCE2_SEL|KL0_IRDA_HIGH_BAND);
704 }
705 }
706 MACIO_OUT32(KEYLARGO_FCR0, fcr);
707 if ((fcr & (KL0_SCCA_ENABLE | KL0_SCCB_ENABLE)) == 0) {
708 fcr &= ~KL0_SCC_CELL_ENABLE;
709 MACIO_OUT32(KEYLARGO_FCR0, fcr);
710 }
711 macio->flags &= ~(chan_mask);
712 UNLOCK(flags);
713 mdelay(10);
714 }
715 return 0;
716 }
717
718 static long
719 core99_modem_enable(struct device_node *node, long param, long value)
720 {
721 struct macio_chip* macio;
722 u8 gpio;
723 unsigned long flags;
724
725 /* Hack for internal USB modem */
726 if (node == NULL) {
727 if (macio_chips[0].type != macio_keylargo)
728 return -ENODEV;
729 node = macio_chips[0].of_node;
730 }
731 macio = macio_find(node, 0);
732 if (!macio)
733 return -ENODEV;
734 gpio = MACIO_IN8(KL_GPIO_MODEM_RESET);
735 gpio |= KEYLARGO_GPIO_OUTPUT_ENABLE;
736 gpio &= ~KEYLARGO_GPIO_OUTOUT_DATA;
737
738 if (!value) {
739 LOCK(flags);
740 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio);
741 UNLOCK(flags);
742 (void)MACIO_IN8(KL_GPIO_MODEM_RESET);
743 mdelay(250);
744 }
745 LOCK(flags);
746 if (value) {
747 MACIO_BIC(KEYLARGO_FCR2, KL2_ALT_DATA_OUT);
748 UNLOCK(flags);
749 (void)MACIO_IN32(KEYLARGO_FCR2);
750 mdelay(250);
751 } else {
752 MACIO_BIS(KEYLARGO_FCR2, KL2_ALT_DATA_OUT);
753 UNLOCK(flags);
754 }
755 if (value) {
756 LOCK(flags);
757 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio | KEYLARGO_GPIO_OUTOUT_DATA);
758 (void)MACIO_IN8(KL_GPIO_MODEM_RESET);
759 UNLOCK(flags); mdelay(250); LOCK(flags);
760 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio);
761 (void)MACIO_IN8(KL_GPIO_MODEM_RESET);
762 UNLOCK(flags); mdelay(250); LOCK(flags);
763 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio | KEYLARGO_GPIO_OUTOUT_DATA);
764 (void)MACIO_IN8(KL_GPIO_MODEM_RESET);
765 UNLOCK(flags); mdelay(250);
766 }
767 return 0;
768 }
769
770 static long
771 pangea_modem_enable(struct device_node *node, long param, long value)
772 {
773 struct macio_chip* macio;
774 u8 gpio;
775 unsigned long flags;
776
777 /* Hack for internal USB modem */
778 if (node == NULL) {
779 if (macio_chips[0].type != macio_pangea &&
780 macio_chips[0].type != macio_intrepid)
781 return -ENODEV;
782 node = macio_chips[0].of_node;
783 }
784 macio = macio_find(node, 0);
785 if (!macio)
786 return -ENODEV;
787 gpio = MACIO_IN8(KL_GPIO_MODEM_RESET);
788 gpio |= KEYLARGO_GPIO_OUTPUT_ENABLE;
789 gpio &= ~KEYLARGO_GPIO_OUTOUT_DATA;
790
791 if (!value) {
792 LOCK(flags);
793 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio);
794 UNLOCK(flags);
795 (void)MACIO_IN8(KL_GPIO_MODEM_RESET);
796 mdelay(250);
797 }
798 LOCK(flags);
799 if (value) {
800 MACIO_OUT8(KL_GPIO_MODEM_POWER,
801 KEYLARGO_GPIO_OUTPUT_ENABLE);
802 UNLOCK(flags);
803 (void)MACIO_IN32(KEYLARGO_FCR2);
804 mdelay(250);
805 } else {
806 MACIO_OUT8(KL_GPIO_MODEM_POWER,
807 KEYLARGO_GPIO_OUTPUT_ENABLE | KEYLARGO_GPIO_OUTOUT_DATA);
808 UNLOCK(flags);
809 }
810 if (value) {
811 LOCK(flags);
812 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio | KEYLARGO_GPIO_OUTOUT_DATA);
813 (void)MACIO_IN8(KL_GPIO_MODEM_RESET);
814 UNLOCK(flags); mdelay(250); LOCK(flags);
815 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio);
816 (void)MACIO_IN8(KL_GPIO_MODEM_RESET);
817 UNLOCK(flags); mdelay(250); LOCK(flags);
818 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio | KEYLARGO_GPIO_OUTOUT_DATA);
819 (void)MACIO_IN8(KL_GPIO_MODEM_RESET);
820 UNLOCK(flags); mdelay(250);
821 }
822 return 0;
823 }
824
825 static long
826 core99_ata100_enable(struct device_node *node, long value)
827 {
828 unsigned long flags;
829 struct pci_dev *pdev = NULL;
830 u8 pbus, pid;
831
832 if (uninorth_rev < 0x24)
833 return -ENODEV;
834
835 LOCK(flags);
836 if (value)
837 UN_BIS(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_ATA100);
838 else
839 UN_BIC(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_ATA100);
840 (void)UN_IN(UNI_N_CLOCK_CNTL);
841 UNLOCK(flags);
842 udelay(20);
843
844 if (value) {
845 if (pci_device_from_OF_node(node, &pbus, &pid) == 0)
846 pdev = pci_find_slot(pbus, pid);
847 if (pdev == NULL)
848 return 0;
849 pci_enable_device(pdev);
850 pci_set_master(pdev);
851 }
852 return 0;
853 }
854
855 static long
856 core99_ide_enable(struct device_node *node, long param, long value)
857 {
858 /* Bus ID 0 to 2 are KeyLargo based IDE, busID 3 is U2
859 * based ata-100
860 */
861 switch(param) {
862 case 0:
863 return simple_feature_tweak(node, macio_unknown,
864 KEYLARGO_FCR1, KL1_EIDE0_ENABLE, value);
865 case 1:
866 return simple_feature_tweak(node, macio_unknown,
867 KEYLARGO_FCR1, KL1_EIDE1_ENABLE, value);
868 case 2:
869 return simple_feature_tweak(node, macio_unknown,
870 KEYLARGO_FCR1, KL1_UIDE_ENABLE, value);
871 case 3:
872 return core99_ata100_enable(node, value);
873 default:
874 return -ENODEV;
875 }
876 }
877
878 static long
879 core99_ide_reset(struct device_node *node, long param, long value)
880 {
881 switch(param) {
882 case 0:
883 return simple_feature_tweak(node, macio_unknown,
884 KEYLARGO_FCR1, KL1_EIDE0_RESET_N, !value);
885 case 1:
886 return simple_feature_tweak(node, macio_unknown,
887 KEYLARGO_FCR1, KL1_EIDE1_RESET_N, !value);
888 case 2:
889 return simple_feature_tweak(node, macio_unknown,
890 KEYLARGO_FCR1, KL1_UIDE_RESET_N, !value);
891 default:
892 return -ENODEV;
893 }
894 }
895
896 static long
897 core99_gmac_enable(struct device_node *node, long param, long value)
898 {
899 unsigned long flags;
900
901 LOCK(flags);
902 if (value)
903 UN_BIS(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_GMAC);
904 else
905 UN_BIC(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_GMAC);
906 (void)UN_IN(UNI_N_CLOCK_CNTL);
907 UNLOCK(flags);
908 udelay(20);
909
910 return 0;
911 }
912
913 static long
914 core99_gmac_phy_reset(struct device_node *node, long param, long value)
915 {
916 unsigned long flags;
917 struct macio_chip *macio;
918
919 macio = &macio_chips[0];
920 if (macio->type != macio_keylargo && macio->type != macio_pangea &&
921 macio->type != macio_intrepid)
922 return -ENODEV;
923
924 LOCK(flags);
925 MACIO_OUT8(KL_GPIO_ETH_PHY_RESET, KEYLARGO_GPIO_OUTPUT_ENABLE);
926 (void)MACIO_IN8(KL_GPIO_ETH_PHY_RESET);
927 UNLOCK(flags);
928 mdelay(10);
929 LOCK(flags);
930 MACIO_OUT8(KL_GPIO_ETH_PHY_RESET, /*KEYLARGO_GPIO_OUTPUT_ENABLE | */
931 KEYLARGO_GPIO_OUTOUT_DATA);
932 UNLOCK(flags);
933 mdelay(10);
934
935 return 0;
936 }
937
938 static long
939 core99_sound_chip_enable(struct device_node *node, long param, long value)
940 {
941 struct macio_chip* macio;
942 unsigned long flags;
943
944 macio = macio_find(node, 0);
945 if (!macio)
946 return -ENODEV;
947
948 /* Do a better probe code, screamer G4 desktops &
949 * iMacs can do that too, add a recalibrate in
950 * the driver as well
951 */
952 if (pmac_mb.model_id == PMAC_TYPE_PISMO ||
953 pmac_mb.model_id == PMAC_TYPE_TITANIUM) {
954 LOCK(flags);
955 if (value)
956 MACIO_OUT8(KL_GPIO_SOUND_POWER,
957 KEYLARGO_GPIO_OUTPUT_ENABLE |
958 KEYLARGO_GPIO_OUTOUT_DATA);
959 else
960 MACIO_OUT8(KL_GPIO_SOUND_POWER,
961 KEYLARGO_GPIO_OUTPUT_ENABLE);
962 (void)MACIO_IN8(KL_GPIO_SOUND_POWER);
963 UNLOCK(flags);
964 }
965 return 0;
966 }
967
968 static long
969 core99_airport_enable(struct device_node *node, long param, long value)
970 {
971 struct macio_chip* macio;
972 unsigned long flags;
973 int state;
974
975 macio = macio_find(node, 0);
976 if (!macio)
977 return -ENODEV;
978
979 /* Hint: we allow passing of macio itself for the sake of the
980 * sleep code
981 */
982 if (node != macio->of_node &&
983 (!node->parent || node->parent != macio->of_node))
984 return -ENODEV;
985 state = (macio->flags & MACIO_FLAG_AIRPORT_ON) != 0;
986 if (value == state)
987 return 0;
988 if (value) {
989 /* This code is a reproduction of OF enable-cardslot
990 * and init-wireless methods, slightly hacked until
991 * I got it working.
992 */
993 LOCK(flags);
994 MACIO_OUT8(KEYLARGO_GPIO_0+0xf, 5);
995 (void)MACIO_IN8(KEYLARGO_GPIO_0+0xf);
996 UNLOCK(flags);
997 mdelay(10);
998 LOCK(flags);
999 MACIO_OUT8(KEYLARGO_GPIO_0+0xf, 4);
1000 (void)MACIO_IN8(KEYLARGO_GPIO_0+0xf);
1001 UNLOCK(flags);
1002
1003 mdelay(10);
1004
1005 LOCK(flags);
1006 MACIO_BIC(KEYLARGO_FCR2, KL2_CARDSEL_16);
1007 (void)MACIO_IN32(KEYLARGO_FCR2);
1008 udelay(10);
1009 MACIO_OUT8(KEYLARGO_GPIO_EXTINT_0+0xb, 0);
1010 (void)MACIO_IN8(KEYLARGO_GPIO_EXTINT_0+0xb);
1011 udelay(10);
1012 MACIO_OUT8(KEYLARGO_GPIO_EXTINT_0+0xa, 0x28);
1013 (void)MACIO_IN8(KEYLARGO_GPIO_EXTINT_0+0xa);
1014 udelay(10);
1015 MACIO_OUT8(KEYLARGO_GPIO_EXTINT_0+0xd, 0x28);
1016 (void)MACIO_IN8(KEYLARGO_GPIO_EXTINT_0+0xd);
1017 udelay(10);
1018 MACIO_OUT8(KEYLARGO_GPIO_0+0xd, 0x28);
1019 (void)MACIO_IN8(KEYLARGO_GPIO_0+0xd);
1020 udelay(10);
1021 MACIO_OUT8(KEYLARGO_GPIO_0+0xe, 0x28);
1022 (void)MACIO_IN8(KEYLARGO_GPIO_0+0xe);
1023 UNLOCK(flags);
1024 udelay(10);
1025 MACIO_OUT32(0x1c000, 0);
1026 mdelay(1);
1027 MACIO_OUT8(0x1a3e0, 0x41);
1028 (void)MACIO_IN8(0x1a3e0);
1029 udelay(10);
1030 LOCK(flags);
1031 MACIO_BIS(KEYLARGO_FCR2, KL2_CARDSEL_16);
1032 (void)MACIO_IN32(KEYLARGO_FCR2);
1033 UNLOCK(flags);
1034 mdelay(100);
1035
1036 macio->flags |= MACIO_FLAG_AIRPORT_ON;
1037 } else {
1038 LOCK(flags);
1039 MACIO_BIC(KEYLARGO_FCR2, KL2_CARDSEL_16);
1040 (void)MACIO_IN32(KEYLARGO_FCR2);
1041 MACIO_OUT8(KL_GPIO_AIRPORT_0, 0);
1042 MACIO_OUT8(KL_GPIO_AIRPORT_1, 0);
1043 MACIO_OUT8(KL_GPIO_AIRPORT_2, 0);
1044 MACIO_OUT8(KL_GPIO_AIRPORT_3, 0);
1045 MACIO_OUT8(KL_GPIO_AIRPORT_4, 0);
1046 (void)MACIO_IN8(KL_GPIO_AIRPORT_4);
1047 UNLOCK(flags);
1048
1049 macio->flags &= ~MACIO_FLAG_AIRPORT_ON;
1050 }
1051 return 0;
1052 }
1053
1054 #ifdef CONFIG_SMP
1055 static long
1056 core99_reset_cpu(struct device_node *node, long param, long value)
1057 {
1058 unsigned int reset_io = 0;
1059 unsigned long flags;
1060 struct macio_chip *macio;
1061 struct device_node *np;
1062 const int dflt_reset_lines[] = { KL_GPIO_RESET_CPU0,
1063 KL_GPIO_RESET_CPU1,
1064 KL_GPIO_RESET_CPU2,
1065 KL_GPIO_RESET_CPU3 };
1066
1067 macio = &macio_chips[0];
1068 if (macio->type != macio_keylargo)
1069 return -ENODEV;
1070
1071 np = find_path_device("/cpus");
1072 if (np == NULL)
1073 return -ENODEV;
1074 for (np = np->child; np != NULL; np = np->sibling) {
1075 u32 *num = (u32 *)get_property(np, "reg", NULL);
1076 u32 *rst = (u32 *)get_property(np, "soft-reset", NULL);
1077 if (num == NULL || rst == NULL)
1078 continue;
1079 if (param == *num) {
1080 reset_io = *rst;
1081 break;
1082 }
1083 }
1084 if (np == NULL || reset_io == 0)
1085 reset_io = dflt_reset_lines[param];
1086
1087 LOCK(flags);
1088 MACIO_OUT8(reset_io, KEYLARGO_GPIO_OUTPUT_ENABLE);
1089 (void)MACIO_IN8(reset_io);
1090 udelay(1);
1091 MACIO_OUT8(reset_io, 0);
1092 (void)MACIO_IN8(reset_io);
1093 UNLOCK(flags);
1094
1095 return 0;
1096 }
1097 #endif /* CONFIG_SMP */
1098
1099 static long
1100 core99_usb_enable(struct device_node *node, long param, long value)
1101 {
1102 struct macio_chip *macio;
1103 unsigned long flags;
1104 char *prop;
1105 int number;
1106 u32 reg;
1107
1108 macio = &macio_chips[0];
1109 if (macio->type != macio_keylargo && macio->type != macio_pangea &&
1110 macio->type != macio_intrepid)
1111 return -ENODEV;
1112
1113 prop = (char *)get_property(node, "AAPL,clock-id", NULL);
1114 if (!prop)
1115 return -ENODEV;
1116 if (strncmp(prop, "usb0u048", 8) == 0)
1117 number = 0;
1118 else if (strncmp(prop, "usb1u148", 8) == 0)
1119 number = 2;
1120 else if (strncmp(prop, "usb2u248", 8) == 0)
1121 number = 4;
1122 else
1123 return -ENODEV;
1124
1125 /* Sorry for the brute-force locking, but this is only used during
1126 * sleep and the timing seem to be critical
1127 */
1128 LOCK(flags);
1129 if (value) {
1130 /* Turn ON */
1131 if (number == 0) {
1132 MACIO_BIC(KEYLARGO_FCR0, (KL0_USB0_PAD_SUSPEND0 | KL0_USB0_PAD_SUSPEND1));
1133 (void)MACIO_IN32(KEYLARGO_FCR0);
1134 UNLOCK(flags);
1135 mdelay(1);
1136 LOCK(flags);
1137 MACIO_BIS(KEYLARGO_FCR0, KL0_USB0_CELL_ENABLE);
1138 } else if (number == 2) {
1139 MACIO_BIC(KEYLARGO_FCR0, (KL0_USB1_PAD_SUSPEND0 | KL0_USB1_PAD_SUSPEND1));
1140 UNLOCK(flags);
1141 (void)MACIO_IN32(KEYLARGO_FCR0);
1142 mdelay(1);
1143 LOCK(flags);
1144 MACIO_BIS(KEYLARGO_FCR0, KL0_USB1_CELL_ENABLE);
1145 } else if (number == 4) {
1146 MACIO_BIC(KEYLARGO_FCR1, (KL1_USB2_PAD_SUSPEND0 | KL1_USB2_PAD_SUSPEND1));
1147 UNLOCK(flags);
1148 (void)MACIO_IN32(KEYLARGO_FCR1);
1149 mdelay(1);
1150 LOCK(flags);
1151 MACIO_BIS(KEYLARGO_FCR1, KL1_USB2_CELL_ENABLE);
1152 }
1153 if (number < 4) {
1154 reg = MACIO_IN32(KEYLARGO_FCR4);
1155 reg &= ~(KL4_PORT_WAKEUP_ENABLE(number) | KL4_PORT_RESUME_WAKE_EN(number) |
1156 KL4_PORT_CONNECT_WAKE_EN(number) | KL4_PORT_DISCONNECT_WAKE_EN(number));
1157 reg &= ~(KL4_PORT_WAKEUP_ENABLE(number+1) | KL4_PORT_RESUME_WAKE_EN(number+1) |
1158 KL4_PORT_CONNECT_WAKE_EN(number+1) | KL4_PORT_DISCONNECT_WAKE_EN(number+1));
1159 MACIO_OUT32(KEYLARGO_FCR4, reg);
1160 (void)MACIO_IN32(KEYLARGO_FCR4);
1161 udelay(10);
1162 } else {
1163 reg = MACIO_IN32(KEYLARGO_FCR3);
1164 reg &= ~(KL3_IT_PORT_WAKEUP_ENABLE(0) | KL3_IT_PORT_RESUME_WAKE_EN(0) |
1165 KL3_IT_PORT_CONNECT_WAKE_EN(0) | KL3_IT_PORT_DISCONNECT_WAKE_EN(0));
1166 reg &= ~(KL3_IT_PORT_WAKEUP_ENABLE(1) | KL3_IT_PORT_RESUME_WAKE_EN(1) |
1167 KL3_IT_PORT_CONNECT_WAKE_EN(1) | KL3_IT_PORT_DISCONNECT_WAKE_EN(1));
1168 MACIO_OUT32(KEYLARGO_FCR3, reg);
1169 (void)MACIO_IN32(KEYLARGO_FCR3);
1170 udelay(10);
1171 }
1172 if (macio->type == macio_intrepid) {
1173 /* wait for clock stopped bits to clear */
1174 u32 test0 = 0, test1 = 0;
1175 u32 status0, status1;
1176 int timeout = 1000;
1177
1178 UNLOCK(flags);
1179 switch (number) {
1180 case 0:
1181 test0 = UNI_N_CLOCK_STOPPED_USB0;
1182 test1 = UNI_N_CLOCK_STOPPED_USB0PCI;
1183 break;
1184 case 2:
1185 test0 = UNI_N_CLOCK_STOPPED_USB1;
1186 test1 = UNI_N_CLOCK_STOPPED_USB1PCI;
1187 break;
1188 case 4:
1189 test0 = UNI_N_CLOCK_STOPPED_USB2;
1190 test1 = UNI_N_CLOCK_STOPPED_USB2PCI;
1191 break;
1192 }
1193 do {
1194 if (--timeout <= 0) {
1195 printk(KERN_ERR "core99_usb_enable: "
1196 "Timeout waiting for clocks\n");
1197 break;
1198 }
1199 mdelay(1);
1200 status0 = UN_IN(UNI_N_CLOCK_STOP_STATUS0);
1201 status1 = UN_IN(UNI_N_CLOCK_STOP_STATUS1);
1202 } while ((status0 & test0) | (status1 & test1));
1203 LOCK(flags);
1204 }
1205 } else {
1206 /* Turn OFF */
1207 if (number < 4) {
1208 reg = MACIO_IN32(KEYLARGO_FCR4);
1209 reg |= KL4_PORT_WAKEUP_ENABLE(number) | KL4_PORT_RESUME_WAKE_EN(number) |
1210 KL4_PORT_CONNECT_WAKE_EN(number) | KL4_PORT_DISCONNECT_WAKE_EN(number);
1211 reg |= KL4_PORT_WAKEUP_ENABLE(number+1) | KL4_PORT_RESUME_WAKE_EN(number+1) |
1212 KL4_PORT_CONNECT_WAKE_EN(number+1) | KL4_PORT_DISCONNECT_WAKE_EN(number+1);
1213 MACIO_OUT32(KEYLARGO_FCR4, reg);
1214 (void)MACIO_IN32(KEYLARGO_FCR4);
1215 udelay(1);
1216 } else {
1217 reg = MACIO_IN32(KEYLARGO_FCR3);
1218 reg |= KL3_IT_PORT_WAKEUP_ENABLE(0) | KL3_IT_PORT_RESUME_WAKE_EN(0) |
1219 KL3_IT_PORT_CONNECT_WAKE_EN(0) | KL3_IT_PORT_DISCONNECT_WAKE_EN(0);
1220 reg |= KL3_IT_PORT_WAKEUP_ENABLE(1) | KL3_IT_PORT_RESUME_WAKE_EN(1) |
1221 KL3_IT_PORT_CONNECT_WAKE_EN(1) | KL3_IT_PORT_DISCONNECT_WAKE_EN(1);
1222 MACIO_OUT32(KEYLARGO_FCR3, reg);
1223 (void)MACIO_IN32(KEYLARGO_FCR3);
1224 udelay(1);
1225 }
1226 if (number == 0) {
1227 if (macio->type != macio_intrepid)
1228 MACIO_BIC(KEYLARGO_FCR0, KL0_USB0_CELL_ENABLE);
1229 (void)MACIO_IN32(KEYLARGO_FCR0);
1230 udelay(1);
1231 MACIO_BIS(KEYLARGO_FCR0, (KL0_USB0_PAD_SUSPEND0 | KL0_USB0_PAD_SUSPEND1));
1232 (void)MACIO_IN32(KEYLARGO_FCR0);
1233 } else if (number == 2) {
1234 if (macio->type != macio_intrepid)
1235 MACIO_BIC(KEYLARGO_FCR0, KL0_USB1_CELL_ENABLE);
1236 (void)MACIO_IN32(KEYLARGO_FCR0);
1237 udelay(1);
1238 MACIO_BIS(KEYLARGO_FCR0, (KL0_USB1_PAD_SUSPEND0 | KL0_USB1_PAD_SUSPEND1));
1239 (void)MACIO_IN32(KEYLARGO_FCR0);
1240 } else if (number == 4) {
1241 udelay(1);
1242 MACIO_BIS(KEYLARGO_FCR1, (KL1_USB2_PAD_SUSPEND0 | KL1_USB2_PAD_SUSPEND1));
1243 (void)MACIO_IN32(KEYLARGO_FCR1);
1244 }
1245 udelay(1);
1246 }
1247 UNLOCK(flags);
1248
1249 return 0;
1250 }
1251
1252 static long
1253 core99_firewire_enable(struct device_node *node, long param, long value)
1254 {
1255 unsigned long flags;
1256 struct macio_chip *macio;
1257
1258 macio = &macio_chips[0];
1259 if (macio->type != macio_keylargo && macio->type != macio_pangea &&
1260 macio->type != macio_intrepid)
1261 return -ENODEV;
1262 if (!(macio->flags & MACIO_FLAG_FW_SUPPORTED))
1263 return -ENODEV;
1264
1265 LOCK(flags);
1266 if (value) {
1267 UN_BIS(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_FW);
1268 (void)UN_IN(UNI_N_CLOCK_CNTL);
1269 } else {
1270 UN_BIC(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_FW);
1271 (void)UN_IN(UNI_N_CLOCK_CNTL);
1272 }
1273 UNLOCK(flags);
1274 mdelay(1);
1275
1276 return 0;
1277 }
1278
1279 static long
1280 core99_firewire_cable_power(struct device_node *node, long param, long value)
1281 {
1282 unsigned long flags;
1283 struct macio_chip *macio;
1284
1285 /* Trick: we allow NULL node */
1286 if ((pmac_mb.board_flags & PMAC_MB_HAS_FW_POWER) == 0)
1287 return -ENODEV;
1288 macio = &macio_chips[0];
1289 if (macio->type != macio_keylargo && macio->type != macio_pangea &&
1290 macio->type != macio_intrepid)
1291 return -ENODEV;
1292 if (!(macio->flags & MACIO_FLAG_FW_SUPPORTED))
1293 return -ENODEV;
1294
1295 LOCK(flags);
1296 if (value) {
1297 MACIO_OUT8(KL_GPIO_FW_CABLE_POWER , 0);
1298 MACIO_IN8(KL_GPIO_FW_CABLE_POWER);
1299 udelay(10);
1300 } else {
1301 MACIO_OUT8(KL_GPIO_FW_CABLE_POWER , 4);
1302 MACIO_IN8(KL_GPIO_FW_CABLE_POWER); udelay(10);
1303 }
1304 UNLOCK(flags);
1305 mdelay(1);
1306
1307 return 0;
1308 }
1309
1310 static long
1311 intrepid_aack_delay_enable(struct device_node *node, long param, long value)
1312 {
1313 unsigned long flags;
1314
1315 if (uninorth_rev < 0xd2)
1316 return -ENODEV;
1317
1318 LOCK(flags);
1319 if (param)
1320 UN_BIS(UNI_N_AACK_DELAY, UNI_N_AACK_DELAY_ENABLE);
1321 else
1322 UN_BIC(UNI_N_AACK_DELAY, UNI_N_AACK_DELAY_ENABLE);
1323 UNLOCK(flags);
1324
1325 return 0;
1326 }
1327
1328
1329 #endif /* CONFIG_POWER4 */
1330
1331 static long
1332 core99_read_gpio(struct device_node *node, long param, long value)
1333 {
1334 struct macio_chip *macio = &macio_chips[0];
1335
1336 return MACIO_IN8(param);
1337 }
1338
1339
1340 static long
1341 core99_write_gpio(struct device_node *node, long param, long value)
1342 {
1343 struct macio_chip *macio = &macio_chips[0];
1344
1345 MACIO_OUT8(param, (u8)(value & 0xff));
1346 return 0;
1347 }
1348
1349 #ifdef CONFIG_POWER4
1350 static long g5_gmac_enable(struct device_node *node, long param, long value)
1351 {
1352 struct macio_chip *macio = &macio_chips[0];
1353 unsigned long flags;
1354
1355 if (node == NULL)
1356 return -ENODEV;
1357
1358 LOCK(flags);
1359 if (value) {
1360 MACIO_BIS(KEYLARGO_FCR1, K2_FCR1_GMAC_CLK_ENABLE);
1361 mb();
1362 k2_skiplist[0] = NULL;
1363 } else {
1364 k2_skiplist[0] = node;
1365 mb();
1366 MACIO_BIC(KEYLARGO_FCR1, K2_FCR1_GMAC_CLK_ENABLE);
1367 }
1368
1369 UNLOCK(flags);
1370 mdelay(1);
1371
1372 return 0;
1373 }
1374
1375 static long g5_fw_enable(struct device_node *node, long param, long value)
1376 {
1377 struct macio_chip *macio = &macio_chips[0];
1378 unsigned long flags;
1379
1380 if (node == NULL)
1381 return -ENODEV;
1382
1383 LOCK(flags);
1384 if (value) {
1385 MACIO_BIS(KEYLARGO_FCR1, K2_FCR1_FW_CLK_ENABLE);
1386 mb();
1387 k2_skiplist[1] = NULL;
1388 } else {
1389 k2_skiplist[1] = node;
1390 mb();
1391 MACIO_BIC(KEYLARGO_FCR1, K2_FCR1_FW_CLK_ENABLE);
1392 }
1393
1394 UNLOCK(flags);
1395 mdelay(1);
1396
1397 return 0;
1398 }
1399
1400 static long g5_mpic_enable(struct device_node *node, long param, long value)
1401 {
1402 unsigned long flags;
1403 struct device_node *parent = of_get_parent(node);
1404 int is_u3;
1405
1406 if (parent == NULL)
1407 return 0;
1408 is_u3 = strcmp(parent->name, "u3") == 0 ||
1409 strcmp(parent->name, "u4") == 0;
1410 of_node_put(parent);
1411 if (!is_u3)
1412 return 0;
1413
1414 LOCK(flags);
1415 UN_BIS(U3_TOGGLE_REG, U3_MPIC_RESET | U3_MPIC_OUTPUT_ENABLE);
1416 UNLOCK(flags);
1417
1418 return 0;
1419 }
1420
1421 static long g5_eth_phy_reset(struct device_node *node, long param, long value)
1422 {
1423 struct macio_chip *macio = &macio_chips[0];
1424 struct device_node *phy;
1425 int need_reset;
1426
1427 /*
1428 * We must not reset the combo PHYs, only the BCM5221 found in
1429 * the iMac G5.
1430 */
1431 phy = of_get_next_child(node, NULL);
1432 if (!phy)
1433 return -ENODEV;
1434 need_reset = device_is_compatible(phy, "B5221");
1435 of_node_put(phy);
1436 if (!need_reset)
1437 return 0;
1438
1439 /* PHY reset is GPIO 29, not in device-tree unfortunately */
1440 MACIO_OUT8(K2_GPIO_EXTINT_0 + 29,
1441 KEYLARGO_GPIO_OUTPUT_ENABLE | KEYLARGO_GPIO_OUTOUT_DATA);
1442 /* Thankfully, this is now always called at a time when we can
1443 * schedule by sungem.
1444 */
1445 msleep(10);
1446 MACIO_OUT8(K2_GPIO_EXTINT_0 + 29, 0);
1447
1448 return 0;
1449 }
1450
1451 static long g5_i2s_enable(struct device_node *node, long param, long value)
1452 {
1453 /* Very crude implementation for now */
1454 struct macio_chip *macio = &macio_chips[0];
1455 unsigned long flags;
1456 int cell;
1457 u32 fcrs[3][3] = {
1458 { 0,
1459 K2_FCR1_I2S0_CELL_ENABLE |
1460 K2_FCR1_I2S0_CLK_ENABLE_BIT | K2_FCR1_I2S0_ENABLE,
1461 KL3_I2S0_CLK18_ENABLE
1462 },
1463 { KL0_SCC_A_INTF_ENABLE,
1464 K2_FCR1_I2S1_CELL_ENABLE |
1465 K2_FCR1_I2S1_CLK_ENABLE_BIT | K2_FCR1_I2S1_ENABLE,
1466 KL3_I2S1_CLK18_ENABLE
1467 },
1468 { KL0_SCC_B_INTF_ENABLE,
1469 SH_FCR1_I2S2_CELL_ENABLE |
1470 SH_FCR1_I2S2_CLK_ENABLE_BIT | SH_FCR1_I2S2_ENABLE,
1471 SH_FCR3_I2S2_CLK18_ENABLE
1472 },
1473 };
1474
1475 if (macio->type != macio_keylargo2 && macio->type != macio_shasta)
1476 return -ENODEV;
1477 if (strncmp(node->name, "i2s-", 4))
1478 return -ENODEV;
1479 cell = node->name[4] - 'a';
1480 switch(cell) {
1481 case 0:
1482 case 1:
1483 break;
1484 case 2:
1485 if (macio->type == macio_shasta)
1486 break;
1487 default:
1488 return -ENODEV;
1489 }
1490
1491 LOCK(flags);
1492 if (value) {
1493 MACIO_BIC(KEYLARGO_FCR0, fcrs[cell][0]);
1494 MACIO_BIS(KEYLARGO_FCR1, fcrs[cell][1]);
1495 MACIO_BIS(KEYLARGO_FCR3, fcrs[cell][2]);
1496 } else {
1497 MACIO_BIC(KEYLARGO_FCR3, fcrs[cell][2]);
1498 MACIO_BIC(KEYLARGO_FCR1, fcrs[cell][1]);
1499 MACIO_BIS(KEYLARGO_FCR0, fcrs[cell][0]);
1500 }
1501 udelay(10);
1502 UNLOCK(flags);
1503
1504 return 0;
1505 }
1506
1507
1508 #ifdef CONFIG_SMP
1509 static long g5_reset_cpu(struct device_node *node, long param, long value)
1510 {
1511 unsigned int reset_io = 0;
1512 unsigned long flags;
1513 struct macio_chip *macio;
1514 struct device_node *np;
1515
1516 macio = &macio_chips[0];
1517 if (macio->type != macio_keylargo2 && macio->type != macio_shasta)
1518 return -ENODEV;
1519
1520 np = find_path_device("/cpus");
1521 if (np == NULL)
1522 return -ENODEV;
1523 for (np = np->child; np != NULL; np = np->sibling) {
1524 u32 *num = (u32 *)get_property(np, "reg", NULL);
1525 u32 *rst = (u32 *)get_property(np, "soft-reset", NULL);
1526 if (num == NULL || rst == NULL)
1527 continue;
1528 if (param == *num) {
1529 reset_io = *rst;
1530 break;
1531 }
1532 }
1533 if (np == NULL || reset_io == 0)
1534 return -ENODEV;
1535
1536 LOCK(flags);
1537 MACIO_OUT8(reset_io, KEYLARGO_GPIO_OUTPUT_ENABLE);
1538 (void)MACIO_IN8(reset_io);
1539 udelay(1);
1540 MACIO_OUT8(reset_io, 0);
1541 (void)MACIO_IN8(reset_io);
1542 UNLOCK(flags);
1543
1544 return 0;
1545 }
1546 #endif /* CONFIG_SMP */
1547
1548 /*
1549 * This can be called from pmac_smp so isn't static
1550 *
1551 * This takes the second CPU off the bus on dual CPU machines
1552 * running UP
1553 */
1554 void g5_phy_disable_cpu1(void)
1555 {
1556 if (uninorth_maj == 3)
1557 UN_OUT(U3_API_PHY_CONFIG_1, 0);
1558 }
1559 #endif /* CONFIG_POWER4 */
1560
1561 #ifndef CONFIG_POWER4
1562
1563 static void
1564 keylargo_shutdown(struct macio_chip *macio, int sleep_mode)
1565 {
1566 u32 temp;
1567
1568 if (sleep_mode) {
1569 mdelay(1);
1570 MACIO_BIS(KEYLARGO_FCR0, KL0_USB_REF_SUSPEND);
1571 (void)MACIO_IN32(KEYLARGO_FCR0);
1572 mdelay(1);
1573 }
1574
1575 MACIO_BIC(KEYLARGO_FCR0,KL0_SCCA_ENABLE | KL0_SCCB_ENABLE |
1576 KL0_SCC_CELL_ENABLE |
1577 KL0_IRDA_ENABLE | KL0_IRDA_CLK32_ENABLE |
1578 KL0_IRDA_CLK19_ENABLE);
1579
1580 MACIO_BIC(KEYLARGO_MBCR, KL_MBCR_MB0_DEV_MASK);
1581 MACIO_BIS(KEYLARGO_MBCR, KL_MBCR_MB0_IDE_ENABLE);
1582
1583 MACIO_BIC(KEYLARGO_FCR1,
1584 KL1_AUDIO_SEL_22MCLK | KL1_AUDIO_CLK_ENABLE_BIT |
1585 KL1_AUDIO_CLK_OUT_ENABLE | KL1_AUDIO_CELL_ENABLE |
1586 KL1_I2S0_CELL_ENABLE | KL1_I2S0_CLK_ENABLE_BIT |
1587 KL1_I2S0_ENABLE | KL1_I2S1_CELL_ENABLE |
1588 KL1_I2S1_CLK_ENABLE_BIT | KL1_I2S1_ENABLE |
1589 KL1_EIDE0_ENABLE | KL1_EIDE0_RESET_N |
1590 KL1_EIDE1_ENABLE | KL1_EIDE1_RESET_N |
1591 KL1_UIDE_ENABLE);
1592
1593 MACIO_BIS(KEYLARGO_FCR2, KL2_ALT_DATA_OUT);
1594 MACIO_BIC(KEYLARGO_FCR2, KL2_IOBUS_ENABLE);
1595
1596 temp = MACIO_IN32(KEYLARGO_FCR3);
1597 if (macio->rev >= 2) {
1598 temp |= KL3_SHUTDOWN_PLL2X;
1599 if (sleep_mode)
1600 temp |= KL3_SHUTDOWN_PLL_TOTAL;
1601 }
1602
1603 temp |= KL3_SHUTDOWN_PLLKW6 | KL3_SHUTDOWN_PLLKW4 |
1604 KL3_SHUTDOWN_PLLKW35;
1605 if (sleep_mode)
1606 temp |= KL3_SHUTDOWN_PLLKW12;
1607 temp &= ~(KL3_CLK66_ENABLE | KL3_CLK49_ENABLE | KL3_CLK45_ENABLE
1608 | KL3_CLK31_ENABLE | KL3_I2S1_CLK18_ENABLE | KL3_I2S0_CLK18_ENABLE);
1609 if (sleep_mode)
1610 temp &= ~(KL3_TIMER_CLK18_ENABLE | KL3_VIA_CLK16_ENABLE);
1611 MACIO_OUT32(KEYLARGO_FCR3, temp);
1612
1613 /* Flush posted writes & wait a bit */
1614 (void)MACIO_IN32(KEYLARGO_FCR0); mdelay(1);
1615 }
1616
1617 static void
1618 pangea_shutdown(struct macio_chip *macio, int sleep_mode)
1619 {
1620 u32 temp;
1621
1622 MACIO_BIC(KEYLARGO_FCR0,KL0_SCCA_ENABLE | KL0_SCCB_ENABLE |
1623 KL0_SCC_CELL_ENABLE |
1624 KL0_USB0_CELL_ENABLE | KL0_USB1_CELL_ENABLE);
1625
1626 MACIO_BIC(KEYLARGO_FCR1,
1627 KL1_AUDIO_SEL_22MCLK | KL1_AUDIO_CLK_ENABLE_BIT |
1628 KL1_AUDIO_CLK_OUT_ENABLE | KL1_AUDIO_CELL_ENABLE |
1629 KL1_I2S0_CELL_ENABLE | KL1_I2S0_CLK_ENABLE_BIT |
1630 KL1_I2S0_ENABLE | KL1_I2S1_CELL_ENABLE |
1631 KL1_I2S1_CLK_ENABLE_BIT | KL1_I2S1_ENABLE |
1632 KL1_UIDE_ENABLE);
1633 if (pmac_mb.board_flags & PMAC_MB_MOBILE)
1634 MACIO_BIC(KEYLARGO_FCR1, KL1_UIDE_RESET_N);
1635
1636 MACIO_BIS(KEYLARGO_FCR2, KL2_ALT_DATA_OUT);
1637
1638 temp = MACIO_IN32(KEYLARGO_FCR3);
1639 temp |= KL3_SHUTDOWN_PLLKW6 | KL3_SHUTDOWN_PLLKW4 |
1640 KL3_SHUTDOWN_PLLKW35;
1641 temp &= ~(KL3_CLK49_ENABLE | KL3_CLK45_ENABLE | KL3_CLK31_ENABLE
1642 | KL3_I2S0_CLK18_ENABLE | KL3_I2S1_CLK18_ENABLE);
1643 if (sleep_mode)
1644 temp &= ~(KL3_VIA_CLK16_ENABLE | KL3_TIMER_CLK18_ENABLE);
1645 MACIO_OUT32(KEYLARGO_FCR3, temp);
1646
1647 /* Flush posted writes & wait a bit */
1648 (void)MACIO_IN32(KEYLARGO_FCR0); mdelay(1);
1649 }
1650
1651 static void
1652 intrepid_shutdown(struct macio_chip *macio, int sleep_mode)
1653 {
1654 u32 temp;
1655
1656 MACIO_BIC(KEYLARGO_FCR0,KL0_SCCA_ENABLE | KL0_SCCB_ENABLE |
1657 KL0_SCC_CELL_ENABLE);
1658
1659 MACIO_BIC(KEYLARGO_FCR1,
1660 /*KL1_USB2_CELL_ENABLE |*/
1661 KL1_I2S0_CELL_ENABLE | KL1_I2S0_CLK_ENABLE_BIT |
1662 KL1_I2S0_ENABLE | KL1_I2S1_CELL_ENABLE |
1663 KL1_I2S1_CLK_ENABLE_BIT | KL1_I2S1_ENABLE);
1664 if (pmac_mb.board_flags & PMAC_MB_MOBILE)
1665 MACIO_BIC(KEYLARGO_FCR1, KL1_UIDE_RESET_N);
1666
1667 temp = MACIO_IN32(KEYLARGO_FCR3);
1668 temp &= ~(KL3_CLK49_ENABLE | KL3_CLK45_ENABLE |
1669 KL3_I2S1_CLK18_ENABLE | KL3_I2S0_CLK18_ENABLE);
1670 if (sleep_mode)
1671 temp &= ~(KL3_TIMER_CLK18_ENABLE | KL3_IT_VIA_CLK32_ENABLE);
1672 MACIO_OUT32(KEYLARGO_FCR3, temp);
1673
1674 /* Flush posted writes & wait a bit */
1675 (void)MACIO_IN32(KEYLARGO_FCR0);
1676 mdelay(10);
1677 }
1678
1679
1680 void pmac_tweak_clock_spreading(int enable)
1681 {
1682 struct macio_chip *macio = &macio_chips[0];
1683
1684 /* Hack for doing clock spreading on some machines PowerBooks and
1685 * iBooks. This implements the "platform-do-clockspreading" OF
1686 * property as decoded manually on various models. For safety, we also
1687 * check the product ID in the device-tree in cases we'll whack the i2c
1688 * chip to make reasonably sure we won't set wrong values in there
1689 *
1690 * Of course, ultimately, we have to implement a real parser for
1691 * the platform-do-* stuff...
1692 */
1693
1694 if (macio->type == macio_intrepid) {
1695 struct device_node *clock =
1696 of_find_node_by_path("/uni-n@f8000000/hw-clock");
1697 if (clock && get_property(clock, "platform-do-clockspreading",
1698 NULL)) {
1699 printk(KERN_INFO "%sabling clock spreading on Intrepid"
1700 " ASIC\n", enable ? "En" : "Dis");
1701 if (enable)
1702 UN_OUT(UNI_N_CLOCK_SPREADING, 2);
1703 else
1704 UN_OUT(UNI_N_CLOCK_SPREADING, 0);
1705 mdelay(40);
1706 }
1707 of_node_put(clock);
1708 }
1709
1710 while (machine_is_compatible("PowerBook5,2") ||
1711 machine_is_compatible("PowerBook5,3") ||
1712 machine_is_compatible("PowerBook6,2") ||
1713 machine_is_compatible("PowerBook6,3")) {
1714 struct device_node *ui2c = of_find_node_by_type(NULL, "i2c");
1715 struct device_node *dt = of_find_node_by_name(NULL, "device-tree");
1716 u8 buffer[9];
1717 u32 *productID;
1718 int i, rc, changed = 0;
1719
1720 if (dt == NULL)
1721 break;
1722 productID = (u32 *)get_property(dt, "pid#", NULL);
1723 if (productID == NULL)
1724 break;
1725 while(ui2c) {
1726 struct device_node *p = of_get_parent(ui2c);
1727 if (p && !strcmp(p->name, "uni-n"))
1728 break;
1729 ui2c = of_find_node_by_type(ui2c, "i2c");
1730 }
1731 if (ui2c == NULL)
1732 break;
1733 DBG("Trying to bump clock speed for PID: %08x...\n", *productID);
1734 rc = pmac_low_i2c_open(ui2c, 1);
1735 if (rc != 0)
1736 break;
1737 pmac_low_i2c_setmode(ui2c, pmac_low_i2c_mode_combined);
1738 rc = pmac_low_i2c_xfer(ui2c, 0xd2 | pmac_low_i2c_read, 0x80, buffer, 9);
1739 DBG("read result: %d,", rc);
1740 if (rc != 0) {
1741 pmac_low_i2c_close(ui2c);
1742 break;
1743 }
1744 for (i=0; i<9; i++)
1745 DBG(" %02x", buffer[i]);
1746 DBG("\n");
1747
1748 switch(*productID) {
1749 case 0x1182: /* AlBook 12" rev 2 */
1750 case 0x1183: /* iBook G4 12" */
1751 buffer[0] = (buffer[0] & 0x8f) | 0x70;
1752 buffer[2] = (buffer[2] & 0x7f) | 0x00;
1753 buffer[5] = (buffer[5] & 0x80) | 0x31;
1754 buffer[6] = (buffer[6] & 0x40) | 0xb0;
1755 buffer[7] = (buffer[7] & 0x00) | (enable ? 0xc0 : 0xba);
1756 buffer[8] = (buffer[8] & 0x00) | 0x30;
1757 changed = 1;
1758 break;
1759 case 0x3142: /* AlBook 15" (ATI M10) */
1760 case 0x3143: /* AlBook 17" (ATI M10) */
1761 buffer[0] = (buffer[0] & 0xaf) | 0x50;
1762 buffer[2] = (buffer[2] & 0x7f) | 0x00;
1763 buffer[5] = (buffer[5] & 0x80) | 0x31;
1764 buffer[6] = (buffer[6] & 0x40) | 0xb0;
1765 buffer[7] = (buffer[7] & 0x00) | (enable ? 0xd0 : 0xc0);
1766 buffer[8] = (buffer[8] & 0x00) | 0x30;
1767 changed = 1;
1768 break;
1769 default:
1770 DBG("i2c-hwclock: Machine model not handled\n");
1771 break;
1772 }
1773 if (!changed) {
1774 pmac_low_i2c_close(ui2c);
1775 break;
1776 }
1777 printk(KERN_INFO "%sabling clock spreading on i2c clock chip\n",
1778 enable ? "En" : "Dis");
1779
1780 pmac_low_i2c_setmode(ui2c, pmac_low_i2c_mode_stdsub);
1781 rc = pmac_low_i2c_xfer(ui2c, 0xd2 | pmac_low_i2c_write, 0x80, buffer, 9);
1782 DBG("write result: %d,", rc);
1783 pmac_low_i2c_setmode(ui2c, pmac_low_i2c_mode_combined);
1784 rc = pmac_low_i2c_xfer(ui2c, 0xd2 | pmac_low_i2c_read, 0x80, buffer, 9);
1785 DBG("read result: %d,", rc);
1786 if (rc != 0) {
1787 pmac_low_i2c_close(ui2c);
1788 break;
1789 }
1790 for (i=0; i<9; i++)
1791 DBG(" %02x", buffer[i]);
1792 pmac_low_i2c_close(ui2c);
1793 break;
1794 }
1795 }
1796
1797
1798 static int
1799 core99_sleep(void)
1800 {
1801 struct macio_chip *macio;
1802 int i;
1803
1804 macio = &macio_chips[0];
1805 if (macio->type != macio_keylargo && macio->type != macio_pangea &&
1806 macio->type != macio_intrepid)
1807 return -ENODEV;
1808
1809 /* We power off the wireless slot in case it was not done
1810 * by the driver. We don't power it on automatically however
1811 */
1812 if (macio->flags & MACIO_FLAG_AIRPORT_ON)
1813 core99_airport_enable(macio->of_node, 0, 0);
1814
1815 /* We power off the FW cable. Should be done by the driver... */
1816 if (macio->flags & MACIO_FLAG_FW_SUPPORTED) {
1817 core99_firewire_enable(NULL, 0, 0);
1818 core99_firewire_cable_power(NULL, 0, 0);
1819 }
1820
1821 /* We make sure int. modem is off (in case driver lost it) */
1822 if (macio->type == macio_keylargo)
1823 core99_modem_enable(macio->of_node, 0, 0);
1824 else
1825 pangea_modem_enable(macio->of_node, 0, 0);
1826
1827 /* We make sure the sound is off as well */
1828 core99_sound_chip_enable(macio->of_node, 0, 0);
1829
1830 /*
1831 * Save various bits of KeyLargo
1832 */
1833
1834 /* Save the state of the various GPIOs */
1835 save_gpio_levels[0] = MACIO_IN32(KEYLARGO_GPIO_LEVELS0);
1836 save_gpio_levels[1] = MACIO_IN32(KEYLARGO_GPIO_LEVELS1);
1837 for (i=0; i<KEYLARGO_GPIO_EXTINT_CNT; i++)
1838 save_gpio_extint[i] = MACIO_IN8(KEYLARGO_GPIO_EXTINT_0+i);
1839 for (i=0; i<KEYLARGO_GPIO_CNT; i++)
1840 save_gpio_normal[i] = MACIO_IN8(KEYLARGO_GPIO_0+i);
1841
1842 /* Save the FCRs */
1843 if (macio->type == macio_keylargo)
1844 save_mbcr = MACIO_IN32(KEYLARGO_MBCR);
1845 save_fcr[0] = MACIO_IN32(KEYLARGO_FCR0);
1846 save_fcr[1] = MACIO_IN32(KEYLARGO_FCR1);
1847 save_fcr[2] = MACIO_IN32(KEYLARGO_FCR2);
1848 save_fcr[3] = MACIO_IN32(KEYLARGO_FCR3);
1849 save_fcr[4] = MACIO_IN32(KEYLARGO_FCR4);
1850 if (macio->type == macio_pangea || macio->type == macio_intrepid)
1851 save_fcr[5] = MACIO_IN32(KEYLARGO_FCR5);
1852
1853 /* Save state & config of DBDMA channels */
1854 dbdma_save(macio, save_dbdma);
1855
1856 /*
1857 * Turn off as much as we can
1858 */
1859 if (macio->type == macio_pangea)
1860 pangea_shutdown(macio, 1);
1861 else if (macio->type == macio_intrepid)
1862 intrepid_shutdown(macio, 1);
1863 else if (macio->type == macio_keylargo)
1864 keylargo_shutdown(macio, 1);
1865
1866 /*
1867 * Put the host bridge to sleep
1868 */
1869
1870 save_unin_clock_ctl = UN_IN(UNI_N_CLOCK_CNTL);
1871 /* Note: do not switch GMAC off, driver does it when necessary, WOL must keep it
1872 * enabled !
1873 */
1874 UN_OUT(UNI_N_CLOCK_CNTL, save_unin_clock_ctl &
1875 ~(/*UNI_N_CLOCK_CNTL_GMAC|*/UNI_N_CLOCK_CNTL_FW/*|UNI_N_CLOCK_CNTL_PCI*/));
1876 udelay(100);
1877 UN_OUT(UNI_N_HWINIT_STATE, UNI_N_HWINIT_STATE_SLEEPING);
1878 UN_OUT(UNI_N_POWER_MGT, UNI_N_POWER_MGT_SLEEP);
1879 mdelay(10);
1880
1881 /*
1882 * FIXME: A bit of black magic with OpenPIC (don't ask me why)
1883 */
1884 if (pmac_mb.model_id == PMAC_TYPE_SAWTOOTH) {
1885 MACIO_BIS(0x506e0, 0x00400000);
1886 MACIO_BIS(0x506e0, 0x80000000);
1887 }
1888 return 0;
1889 }
1890
1891 static int
1892 core99_wake_up(void)
1893 {
1894 struct macio_chip *macio;
1895 int i;
1896
1897 macio = &macio_chips[0];
1898 if (macio->type != macio_keylargo && macio->type != macio_pangea &&
1899 macio->type != macio_intrepid)
1900 return -ENODEV;
1901
1902 /*
1903 * Wakeup the host bridge
1904 */
1905 UN_OUT(UNI_N_POWER_MGT, UNI_N_POWER_MGT_NORMAL);
1906 udelay(10);
1907 UN_OUT(UNI_N_HWINIT_STATE, UNI_N_HWINIT_STATE_RUNNING);
1908 udelay(10);
1909
1910 /*
1911 * Restore KeyLargo
1912 */
1913
1914 if (macio->type == macio_keylargo) {
1915 MACIO_OUT32(KEYLARGO_MBCR, save_mbcr);
1916 (void)MACIO_IN32(KEYLARGO_MBCR); udelay(10);
1917 }
1918 MACIO_OUT32(KEYLARGO_FCR0, save_fcr[0]);
1919 (void)MACIO_IN32(KEYLARGO_FCR0); udelay(10);
1920 MACIO_OUT32(KEYLARGO_FCR1, save_fcr[1]);
1921 (void)MACIO_IN32(KEYLARGO_FCR1); udelay(10);
1922 MACIO_OUT32(KEYLARGO_FCR2, save_fcr[2]);
1923 (void)MACIO_IN32(KEYLARGO_FCR2); udelay(10);
1924 MACIO_OUT32(KEYLARGO_FCR3, save_fcr[3]);
1925 (void)MACIO_IN32(KEYLARGO_FCR3); udelay(10);
1926 MACIO_OUT32(KEYLARGO_FCR4, save_fcr[4]);
1927 (void)MACIO_IN32(KEYLARGO_FCR4); udelay(10);
1928 if (macio->type == macio_pangea || macio->type == macio_intrepid) {
1929 MACIO_OUT32(KEYLARGO_FCR5, save_fcr[5]);
1930 (void)MACIO_IN32(KEYLARGO_FCR5); udelay(10);
1931 }
1932
1933 dbdma_restore(macio, save_dbdma);
1934
1935 MACIO_OUT32(KEYLARGO_GPIO_LEVELS0, save_gpio_levels[0]);
1936 MACIO_OUT32(KEYLARGO_GPIO_LEVELS1, save_gpio_levels[1]);
1937 for (i=0; i<KEYLARGO_GPIO_EXTINT_CNT; i++)
1938 MACIO_OUT8(KEYLARGO_GPIO_EXTINT_0+i, save_gpio_extint[i]);
1939 for (i=0; i<KEYLARGO_GPIO_CNT; i++)
1940 MACIO_OUT8(KEYLARGO_GPIO_0+i, save_gpio_normal[i]);
1941
1942 /* FIXME more black magic with OpenPIC ... */
1943 if (pmac_mb.model_id == PMAC_TYPE_SAWTOOTH) {
1944 MACIO_BIC(0x506e0, 0x00400000);
1945 MACIO_BIC(0x506e0, 0x80000000);
1946 }
1947
1948 UN_OUT(UNI_N_CLOCK_CNTL, save_unin_clock_ctl);
1949 udelay(100);
1950
1951 return 0;
1952 }
1953
1954 static long
1955 core99_sleep_state(struct device_node *node, long param, long value)
1956 {
1957 /* Param == 1 means to enter the "fake sleep" mode that is
1958 * used for CPU speed switch
1959 */
1960 if (param == 1) {
1961 if (value == 1) {
1962 UN_OUT(UNI_N_HWINIT_STATE, UNI_N_HWINIT_STATE_SLEEPING);
1963 UN_OUT(UNI_N_POWER_MGT, UNI_N_POWER_MGT_IDLE2);
1964 } else {
1965 UN_OUT(UNI_N_POWER_MGT, UNI_N_POWER_MGT_NORMAL);
1966 udelay(10);
1967 UN_OUT(UNI_N_HWINIT_STATE, UNI_N_HWINIT_STATE_RUNNING);
1968 udelay(10);
1969 }
1970 return 0;
1971 }
1972 if ((pmac_mb.board_flags & PMAC_MB_CAN_SLEEP) == 0)
1973 return -EPERM;
1974
1975 if (value == 1)
1976 return core99_sleep();
1977 else if (value == 0)
1978 return core99_wake_up();
1979 return 0;
1980 }
1981
1982 #endif /* CONFIG_POWER4 */
1983
1984 static long
1985 generic_dev_can_wake(struct device_node *node, long param, long value)
1986 {
1987 /* Todo: eventually check we are really dealing with on-board
1988 * video device ...
1989 */
1990
1991 if (pmac_mb.board_flags & PMAC_MB_MAY_SLEEP)
1992 pmac_mb.board_flags |= PMAC_MB_CAN_SLEEP;
1993 return 0;
1994 }
1995
1996 static long generic_get_mb_info(struct device_node *node, long param, long value)
1997 {
1998 switch(param) {
1999 case PMAC_MB_INFO_MODEL:
2000 return pmac_mb.model_id;
2001 case PMAC_MB_INFO_FLAGS:
2002 return pmac_mb.board_flags;
2003 case PMAC_MB_INFO_NAME:
2004 /* hack hack hack... but should work */
2005 *((const char **)value) = pmac_mb.model_name;
2006 return 0;
2007 }
2008 return -EINVAL;
2009 }
2010
2011
2012 /*
2013 * Table definitions
2014 */
2015
2016 /* Used on any machine
2017 */
2018 static struct feature_table_entry any_features[] = {
2019 { PMAC_FTR_GET_MB_INFO, generic_get_mb_info },
2020 { PMAC_FTR_DEVICE_CAN_WAKE, generic_dev_can_wake },
2021 { 0, NULL }
2022 };
2023
2024 #ifndef CONFIG_POWER4
2025
2026 /* OHare based motherboards. Currently, we only use these on the
2027 * 2400,3400 and 3500 series powerbooks. Some older desktops seem
2028 * to have issues with turning on/off those asic cells
2029 */
2030 static struct feature_table_entry ohare_features[] = {
2031 { PMAC_FTR_SCC_ENABLE, ohare_htw_scc_enable },
2032 { PMAC_FTR_SWIM3_ENABLE, ohare_floppy_enable },
2033 { PMAC_FTR_MESH_ENABLE, ohare_mesh_enable },
2034 { PMAC_FTR_IDE_ENABLE, ohare_ide_enable},
2035 { PMAC_FTR_IDE_RESET, ohare_ide_reset},
2036 { PMAC_FTR_SLEEP_STATE, ohare_sleep_state },
2037 { 0, NULL }
2038 };
2039
2040 /* Heathrow desktop machines (Beige G3).
2041 * Separated as some features couldn't be properly tested
2042 * and the serial port control bits appear to confuse it.
2043 */
2044 static struct feature_table_entry heathrow_desktop_features[] = {
2045 { PMAC_FTR_SWIM3_ENABLE, heathrow_floppy_enable },
2046 { PMAC_FTR_MESH_ENABLE, heathrow_mesh_enable },
2047 { PMAC_FTR_IDE_ENABLE, heathrow_ide_enable },
2048 { PMAC_FTR_IDE_RESET, heathrow_ide_reset },
2049 { PMAC_FTR_BMAC_ENABLE, heathrow_bmac_enable },
2050 { 0, NULL }
2051 };
2052
2053 /* Heathrow based laptop, that is the Wallstreet and mainstreet
2054 * powerbooks.
2055 */
2056 static struct feature_table_entry heathrow_laptop_features[] = {
2057 { PMAC_FTR_SCC_ENABLE, ohare_htw_scc_enable },
2058 { PMAC_FTR_MODEM_ENABLE, heathrow_modem_enable },
2059 { PMAC_FTR_SWIM3_ENABLE, heathrow_floppy_enable },
2060 { PMAC_FTR_MESH_ENABLE, heathrow_mesh_enable },
2061 { PMAC_FTR_IDE_ENABLE, heathrow_ide_enable },
2062 { PMAC_FTR_IDE_RESET, heathrow_ide_reset },
2063 { PMAC_FTR_BMAC_ENABLE, heathrow_bmac_enable },
2064 { PMAC_FTR_SOUND_CHIP_ENABLE, heathrow_sound_enable },
2065 { PMAC_FTR_SLEEP_STATE, heathrow_sleep_state },
2066 { 0, NULL }
2067 };
2068
2069 /* Paddington based machines
2070 * The lombard (101) powerbook, first iMac models, B&W G3 and Yikes G4.
2071 */
2072 static struct feature_table_entry paddington_features[] = {
2073 { PMAC_FTR_SCC_ENABLE, ohare_htw_scc_enable },
2074 { PMAC_FTR_MODEM_ENABLE, heathrow_modem_enable },
2075 { PMAC_FTR_SWIM3_ENABLE, heathrow_floppy_enable },
2076 { PMAC_FTR_MESH_ENABLE, heathrow_mesh_enable },
2077 { PMAC_FTR_IDE_ENABLE, heathrow_ide_enable },
2078 { PMAC_FTR_IDE_RESET, heathrow_ide_reset },
2079 { PMAC_FTR_BMAC_ENABLE, heathrow_bmac_enable },
2080 { PMAC_FTR_SOUND_CHIP_ENABLE, heathrow_sound_enable },
2081 { PMAC_FTR_SLEEP_STATE, heathrow_sleep_state },
2082 { 0, NULL }
2083 };
2084
2085 /* Core99 & MacRISC 2 machines (all machines released since the
2086 * iBook (included), that is all AGP machines, except pangea
2087 * chipset. The pangea chipset is the "combo" UniNorth/KeyLargo
2088 * used on iBook2 & iMac "flow power".
2089 */
2090 static struct feature_table_entry core99_features[] = {
2091 { PMAC_FTR_SCC_ENABLE, core99_scc_enable },
2092 { PMAC_FTR_MODEM_ENABLE, core99_modem_enable },
2093 { PMAC_FTR_IDE_ENABLE, core99_ide_enable },
2094 { PMAC_FTR_IDE_RESET, core99_ide_reset },
2095 { PMAC_FTR_GMAC_ENABLE, core99_gmac_enable },
2096 { PMAC_FTR_GMAC_PHY_RESET, core99_gmac_phy_reset },
2097 { PMAC_FTR_SOUND_CHIP_ENABLE, core99_sound_chip_enable },
2098 { PMAC_FTR_AIRPORT_ENABLE, core99_airport_enable },
2099 { PMAC_FTR_USB_ENABLE, core99_usb_enable },
2100 { PMAC_FTR_1394_ENABLE, core99_firewire_enable },
2101 { PMAC_FTR_1394_CABLE_POWER, core99_firewire_cable_power },
2102 { PMAC_FTR_SLEEP_STATE, core99_sleep_state },
2103 #ifdef CONFIG_SMP
2104 { PMAC_FTR_RESET_CPU, core99_reset_cpu },
2105 #endif /* CONFIG_SMP */
2106 { PMAC_FTR_READ_GPIO, core99_read_gpio },
2107 { PMAC_FTR_WRITE_GPIO, core99_write_gpio },
2108 { 0, NULL }
2109 };
2110
2111 /* RackMac
2112 */
2113 static struct feature_table_entry rackmac_features[] = {
2114 { PMAC_FTR_SCC_ENABLE, core99_scc_enable },
2115 { PMAC_FTR_IDE_ENABLE, core99_ide_enable },
2116 { PMAC_FTR_IDE_RESET, core99_ide_reset },
2117 { PMAC_FTR_GMAC_ENABLE, core99_gmac_enable },
2118 { PMAC_FTR_GMAC_PHY_RESET, core99_gmac_phy_reset },
2119 { PMAC_FTR_USB_ENABLE, core99_usb_enable },
2120 { PMAC_FTR_1394_ENABLE, core99_firewire_enable },
2121 { PMAC_FTR_1394_CABLE_POWER, core99_firewire_cable_power },
2122 { PMAC_FTR_SLEEP_STATE, core99_sleep_state },
2123 #ifdef CONFIG_SMP
2124 { PMAC_FTR_RESET_CPU, core99_reset_cpu },
2125 #endif /* CONFIG_SMP */
2126 { PMAC_FTR_READ_GPIO, core99_read_gpio },
2127 { PMAC_FTR_WRITE_GPIO, core99_write_gpio },
2128 { 0, NULL }
2129 };
2130
2131 /* Pangea features
2132 */
2133 static struct feature_table_entry pangea_features[] = {
2134 { PMAC_FTR_SCC_ENABLE, core99_scc_enable },
2135 { PMAC_FTR_MODEM_ENABLE, pangea_modem_enable },
2136 { PMAC_FTR_IDE_ENABLE, core99_ide_enable },
2137 { PMAC_FTR_IDE_RESET, core99_ide_reset },
2138 { PMAC_FTR_GMAC_ENABLE, core99_gmac_enable },
2139 { PMAC_FTR_GMAC_PHY_RESET, core99_gmac_phy_reset },
2140 { PMAC_FTR_SOUND_CHIP_ENABLE, core99_sound_chip_enable },
2141 { PMAC_FTR_AIRPORT_ENABLE, core99_airport_enable },
2142 { PMAC_FTR_USB_ENABLE, core99_usb_enable },
2143 { PMAC_FTR_1394_ENABLE, core99_firewire_enable },
2144 { PMAC_FTR_1394_CABLE_POWER, core99_firewire_cable_power },
2145 { PMAC_FTR_SLEEP_STATE, core99_sleep_state },
2146 { PMAC_FTR_READ_GPIO, core99_read_gpio },
2147 { PMAC_FTR_WRITE_GPIO, core99_write_gpio },
2148 { 0, NULL }
2149 };
2150
2151 /* Intrepid features
2152 */
2153 static struct feature_table_entry intrepid_features[] = {
2154 { PMAC_FTR_SCC_ENABLE, core99_scc_enable },
2155 { PMAC_FTR_MODEM_ENABLE, pangea_modem_enable },
2156 { PMAC_FTR_IDE_ENABLE, core99_ide_enable },
2157 { PMAC_FTR_IDE_RESET, core99_ide_reset },
2158 { PMAC_FTR_GMAC_ENABLE, core99_gmac_enable },
2159 { PMAC_FTR_GMAC_PHY_RESET, core99_gmac_phy_reset },
2160 { PMAC_FTR_SOUND_CHIP_ENABLE, core99_sound_chip_enable },
2161 { PMAC_FTR_AIRPORT_ENABLE, core99_airport_enable },
2162 { PMAC_FTR_USB_ENABLE, core99_usb_enable },
2163 { PMAC_FTR_1394_ENABLE, core99_firewire_enable },
2164 { PMAC_FTR_1394_CABLE_POWER, core99_firewire_cable_power },
2165 { PMAC_FTR_SLEEP_STATE, core99_sleep_state },
2166 { PMAC_FTR_READ_GPIO, core99_read_gpio },
2167 { PMAC_FTR_WRITE_GPIO, core99_write_gpio },
2168 { PMAC_FTR_AACK_DELAY_ENABLE, intrepid_aack_delay_enable },
2169 { 0, NULL }
2170 };
2171
2172 #else /* CONFIG_POWER4 */
2173
2174 /* G5 features
2175 */
2176 static struct feature_table_entry g5_features[] = {
2177 { PMAC_FTR_GMAC_ENABLE, g5_gmac_enable },
2178 { PMAC_FTR_1394_ENABLE, g5_fw_enable },
2179 { PMAC_FTR_ENABLE_MPIC, g5_mpic_enable },
2180 { PMAC_FTR_GMAC_PHY_RESET, g5_eth_phy_reset },
2181 { PMAC_FTR_SOUND_CHIP_ENABLE, g5_i2s_enable },
2182 #ifdef CONFIG_SMP
2183 { PMAC_FTR_RESET_CPU, g5_reset_cpu },
2184 #endif /* CONFIG_SMP */
2185 { PMAC_FTR_READ_GPIO, core99_read_gpio },
2186 { PMAC_FTR_WRITE_GPIO, core99_write_gpio },
2187 { 0, NULL }
2188 };
2189
2190 #endif /* CONFIG_POWER4 */
2191
2192 static struct pmac_mb_def pmac_mb_defs[] = {
2193 #ifndef CONFIG_POWER4
2194 /*
2195 * Desktops
2196 */
2197
2198 { "AAPL,8500", "PowerMac 8500/8600",
2199 PMAC_TYPE_PSURGE, NULL,
2200 0
2201 },
2202 { "AAPL,9500", "PowerMac 9500/9600",
2203 PMAC_TYPE_PSURGE, NULL,
2204 0
2205 },
2206 { "AAPL,7200", "PowerMac 7200",
2207 PMAC_TYPE_PSURGE, NULL,
2208 0
2209 },
2210 { "AAPL,7300", "PowerMac 7200/7300",
2211 PMAC_TYPE_PSURGE, NULL,
2212 0
2213 },
2214 { "AAPL,7500", "PowerMac 7500",
2215 PMAC_TYPE_PSURGE, NULL,
2216 0
2217 },
2218 { "AAPL,ShinerESB", "Apple Network Server",
2219 PMAC_TYPE_ANS, NULL,
2220 0
2221 },
2222 { "AAPL,e407", "Alchemy",
2223 PMAC_TYPE_ALCHEMY, NULL,
2224 0
2225 },
2226 { "AAPL,e411", "Gazelle",
2227 PMAC_TYPE_GAZELLE, NULL,
2228 0
2229 },
2230 { "AAPL,Gossamer", "PowerMac G3 (Gossamer)",
2231 PMAC_TYPE_GOSSAMER, heathrow_desktop_features,
2232 0
2233 },
2234 { "AAPL,PowerMac G3", "PowerMac G3 (Silk)",
2235 PMAC_TYPE_SILK, heathrow_desktop_features,
2236 0
2237 },
2238 { "PowerMac1,1", "Blue&White G3",
2239 PMAC_TYPE_YOSEMITE, paddington_features,
2240 0
2241 },
2242 { "PowerMac1,2", "PowerMac G4 PCI Graphics",
2243 PMAC_TYPE_YIKES, paddington_features,
2244 0
2245 },
2246 { "PowerMac2,1", "iMac FireWire",
2247 PMAC_TYPE_FW_IMAC, core99_features,
2248 PMAC_MB_MAY_SLEEP | PMAC_MB_OLD_CORE99
2249 },
2250 { "PowerMac2,2", "iMac FireWire",
2251 PMAC_TYPE_FW_IMAC, core99_features,
2252 PMAC_MB_MAY_SLEEP | PMAC_MB_OLD_CORE99
2253 },
2254 { "PowerMac3,1", "PowerMac G4 AGP Graphics",
2255 PMAC_TYPE_SAWTOOTH, core99_features,
2256 PMAC_MB_OLD_CORE99
2257 },
2258 { "PowerMac3,2", "PowerMac G4 AGP Graphics",
2259 PMAC_TYPE_SAWTOOTH, core99_features,
2260 PMAC_MB_MAY_SLEEP | PMAC_MB_OLD_CORE99
2261 },
2262 { "PowerMac3,3", "PowerMac G4 AGP Graphics",
2263 PMAC_TYPE_SAWTOOTH, core99_features,
2264 PMAC_MB_MAY_SLEEP | PMAC_MB_OLD_CORE99
2265 },
2266 { "PowerMac3,4", "PowerMac G4 Silver",
2267 PMAC_TYPE_QUICKSILVER, core99_features,
2268 PMAC_MB_MAY_SLEEP
2269 },
2270 { "PowerMac3,5", "PowerMac G4 Silver",
2271 PMAC_TYPE_QUICKSILVER, core99_features,
2272 PMAC_MB_MAY_SLEEP
2273 },
2274 { "PowerMac3,6", "PowerMac G4 Windtunnel",
2275 PMAC_TYPE_WINDTUNNEL, core99_features,
2276 PMAC_MB_MAY_SLEEP,
2277 },
2278 { "PowerMac4,1", "iMac \"Flower Power\"",
2279 PMAC_TYPE_PANGEA_IMAC, pangea_features,
2280 PMAC_MB_MAY_SLEEP
2281 },
2282 { "PowerMac4,2", "Flat panel iMac",
2283 PMAC_TYPE_FLAT_PANEL_IMAC, pangea_features,
2284 PMAC_MB_CAN_SLEEP
2285 },
2286 { "PowerMac4,4", "eMac",
2287 PMAC_TYPE_EMAC, core99_features,
2288 PMAC_MB_MAY_SLEEP
2289 },
2290 { "PowerMac5,1", "PowerMac G4 Cube",
2291 PMAC_TYPE_CUBE, core99_features,
2292 PMAC_MB_MAY_SLEEP | PMAC_MB_OLD_CORE99
2293 },
2294 { "PowerMac6,1", "Flat panel iMac",
2295 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2296 PMAC_MB_MAY_SLEEP,
2297 },
2298 { "PowerMac6,3", "Flat panel iMac",
2299 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2300 PMAC_MB_MAY_SLEEP,
2301 },
2302 { "PowerMac6,4", "eMac",
2303 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2304 PMAC_MB_MAY_SLEEP,
2305 },
2306 { "PowerMac10,1", "Mac mini",
2307 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2308 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER,
2309 },
2310 { "iMac,1", "iMac (first generation)",
2311 PMAC_TYPE_ORIG_IMAC, paddington_features,
2312 0
2313 },
2314
2315 /*
2316 * Xserve's
2317 */
2318
2319 { "RackMac1,1", "XServe",
2320 PMAC_TYPE_RACKMAC, rackmac_features,
2321 0,
2322 },
2323 { "RackMac1,2", "XServe rev. 2",
2324 PMAC_TYPE_RACKMAC, rackmac_features,
2325 0,
2326 },
2327
2328 /*
2329 * Laptops
2330 */
2331
2332 { "AAPL,3400/2400", "PowerBook 3400",
2333 PMAC_TYPE_HOOPER, ohare_features,
2334 PMAC_MB_CAN_SLEEP | PMAC_MB_MOBILE
2335 },
2336 { "AAPL,3500", "PowerBook 3500",
2337 PMAC_TYPE_KANGA, ohare_features,
2338 PMAC_MB_CAN_SLEEP | PMAC_MB_MOBILE
2339 },
2340 { "AAPL,PowerBook1998", "PowerBook Wallstreet",
2341 PMAC_TYPE_WALLSTREET, heathrow_laptop_features,
2342 PMAC_MB_CAN_SLEEP | PMAC_MB_MOBILE
2343 },
2344 { "PowerBook1,1", "PowerBook 101 (Lombard)",
2345 PMAC_TYPE_101_PBOOK, paddington_features,
2346 PMAC_MB_CAN_SLEEP | PMAC_MB_MOBILE
2347 },
2348 { "PowerBook2,1", "iBook (first generation)",
2349 PMAC_TYPE_ORIG_IBOOK, core99_features,
2350 PMAC_MB_CAN_SLEEP | PMAC_MB_OLD_CORE99 | PMAC_MB_MOBILE
2351 },
2352 { "PowerBook2,2", "iBook FireWire",
2353 PMAC_TYPE_FW_IBOOK, core99_features,
2354 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER |
2355 PMAC_MB_OLD_CORE99 | PMAC_MB_MOBILE
2356 },
2357 { "PowerBook3,1", "PowerBook Pismo",
2358 PMAC_TYPE_PISMO, core99_features,
2359 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER |
2360 PMAC_MB_OLD_CORE99 | PMAC_MB_MOBILE
2361 },
2362 { "PowerBook3,2", "PowerBook Titanium",
2363 PMAC_TYPE_TITANIUM, core99_features,
2364 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE
2365 },
2366 { "PowerBook3,3", "PowerBook Titanium II",
2367 PMAC_TYPE_TITANIUM2, core99_features,
2368 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE
2369 },
2370 { "PowerBook3,4", "PowerBook Titanium III",
2371 PMAC_TYPE_TITANIUM3, core99_features,
2372 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE
2373 },
2374 { "PowerBook3,5", "PowerBook Titanium IV",
2375 PMAC_TYPE_TITANIUM4, core99_features,
2376 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE
2377 },
2378 { "PowerBook4,1", "iBook 2",
2379 PMAC_TYPE_IBOOK2, pangea_features,
2380 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE
2381 },
2382 { "PowerBook4,2", "iBook 2",
2383 PMAC_TYPE_IBOOK2, pangea_features,
2384 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE
2385 },
2386 { "PowerBook4,3", "iBook 2 rev. 2",
2387 PMAC_TYPE_IBOOK2, pangea_features,
2388 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE
2389 },
2390 { "PowerBook5,1", "PowerBook G4 17\"",
2391 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2392 PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2393 },
2394 { "PowerBook5,2", "PowerBook G4 15\"",
2395 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2396 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2397 },
2398 { "PowerBook5,3", "PowerBook G4 17\"",
2399 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2400 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2401 },
2402 { "PowerBook5,4", "PowerBook G4 15\"",
2403 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2404 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2405 },
2406 { "PowerBook5,5", "PowerBook G4 17\"",
2407 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2408 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2409 },
2410 { "PowerBook5,6", "PowerBook G4 15\"",
2411 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2412 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2413 },
2414 { "PowerBook5,7", "PowerBook G4 17\"",
2415 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2416 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2417 },
2418 { "PowerBook5,8", "PowerBook G4 15\"",
2419 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2420 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2421 },
2422 { "PowerBook5,9", "PowerBook G4 17\"",
2423 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2424 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2425 },
2426 { "PowerBook6,1", "PowerBook G4 12\"",
2427 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2428 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2429 },
2430 { "PowerBook6,2", "PowerBook G4",
2431 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2432 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2433 },
2434 { "PowerBook6,3", "iBook G4",
2435 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2436 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2437 },
2438 { "PowerBook6,4", "PowerBook G4 12\"",
2439 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2440 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2441 },
2442 { "PowerBook6,5", "iBook G4",
2443 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2444 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2445 },
2446 { "PowerBook6,7", "iBook G4",
2447 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2448 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2449 },
2450 { "PowerBook6,8", "PowerBook G4 12\"",
2451 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2452 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2453 },
2454 #else /* CONFIG_POWER4 */
2455 { "PowerMac7,2", "PowerMac G5",
2456 PMAC_TYPE_POWERMAC_G5, g5_features,
2457 0,
2458 },
2459 #ifdef CONFIG_PPC64
2460 { "PowerMac7,3", "PowerMac G5",
2461 PMAC_TYPE_POWERMAC_G5, g5_features,
2462 0,
2463 },
2464 { "PowerMac8,1", "iMac G5",
2465 PMAC_TYPE_IMAC_G5, g5_features,
2466 0,
2467 },
2468 { "PowerMac9,1", "PowerMac G5",
2469 PMAC_TYPE_POWERMAC_G5_U3L, g5_features,
2470 0,
2471 },
2472 { "PowerMac11,2", "PowerMac G5 Dual Core",
2473 PMAC_TYPE_POWERMAC_G5_U3L, g5_features,
2474 0,
2475 },
2476 { "PowerMac12,1", "iMac G5 (iSight)",
2477 PMAC_TYPE_POWERMAC_G5_U3L, g5_features,
2478 0,
2479 },
2480 { "RackMac3,1", "XServe G5",
2481 PMAC_TYPE_XSERVE_G5, g5_features,
2482 0,
2483 },
2484 #endif /* CONFIG_PPC64 */
2485 #endif /* CONFIG_POWER4 */
2486 };
2487
2488 /*
2489 * The toplevel feature_call callback
2490 */
2491 long pmac_do_feature_call(unsigned int selector, ...)
2492 {
2493 struct device_node *node;
2494 long param, value;
2495 int i;
2496 feature_call func = NULL;
2497 va_list args;
2498
2499 if (pmac_mb.features)
2500 for (i=0; pmac_mb.features[i].function; i++)
2501 if (pmac_mb.features[i].selector == selector) {
2502 func = pmac_mb.features[i].function;
2503 break;
2504 }
2505 if (!func)
2506 for (i=0; any_features[i].function; i++)
2507 if (any_features[i].selector == selector) {
2508 func = any_features[i].function;
2509 break;
2510 }
2511 if (!func)
2512 return -ENODEV;
2513
2514 va_start(args, selector);
2515 node = (struct device_node*)va_arg(args, void*);
2516 param = va_arg(args, long);
2517 value = va_arg(args, long);
2518 va_end(args);
2519
2520 return func(node, param, value);
2521 }
2522
2523 static int __init probe_motherboard(void)
2524 {
2525 int i;
2526 struct macio_chip *macio = &macio_chips[0];
2527 const char *model = NULL;
2528 struct device_node *dt;
2529
2530 /* Lookup known motherboard type in device-tree. First try an
2531 * exact match on the "model" property, then try a "compatible"
2532 * match is none is found.
2533 */
2534 dt = find_devices("device-tree");
2535 if (dt != NULL)
2536 model = (const char *) get_property(dt, "model", NULL);
2537 for(i=0; model && i<(sizeof(pmac_mb_defs)/sizeof(struct pmac_mb_def)); i++) {
2538 if (strcmp(model, pmac_mb_defs[i].model_string) == 0) {
2539 pmac_mb = pmac_mb_defs[i];
2540 goto found;
2541 }
2542 }
2543 for(i=0; i<(sizeof(pmac_mb_defs)/sizeof(struct pmac_mb_def)); i++) {
2544 if (machine_is_compatible(pmac_mb_defs[i].model_string)) {
2545 pmac_mb = pmac_mb_defs[i];
2546 goto found;
2547 }
2548 }
2549
2550 /* Fallback to selection depending on mac-io chip type */
2551 switch(macio->type) {
2552 #ifndef CONFIG_POWER4
2553 case macio_grand_central:
2554 pmac_mb.model_id = PMAC_TYPE_PSURGE;
2555 pmac_mb.model_name = "Unknown PowerSurge";
2556 break;
2557 case macio_ohare:
2558 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_OHARE;
2559 pmac_mb.model_name = "Unknown OHare-based";
2560 break;
2561 case macio_heathrow:
2562 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_HEATHROW;
2563 pmac_mb.model_name = "Unknown Heathrow-based";
2564 pmac_mb.features = heathrow_desktop_features;
2565 break;
2566 case macio_paddington:
2567 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_PADDINGTON;
2568 pmac_mb.model_name = "Unknown Paddington-based";
2569 pmac_mb.features = paddington_features;
2570 break;
2571 case macio_keylargo:
2572 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_CORE99;
2573 pmac_mb.model_name = "Unknown Keylargo-based";
2574 pmac_mb.features = core99_features;
2575 break;
2576 case macio_pangea:
2577 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_PANGEA;
2578 pmac_mb.model_name = "Unknown Pangea-based";
2579 pmac_mb.features = pangea_features;
2580 break;
2581 case macio_intrepid:
2582 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_INTREPID;
2583 pmac_mb.model_name = "Unknown Intrepid-based";
2584 pmac_mb.features = intrepid_features;
2585 break;
2586 #else /* CONFIG_POWER4 */
2587 case macio_keylargo2:
2588 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_K2;
2589 pmac_mb.model_name = "Unknown K2-based";
2590 pmac_mb.features = g5_features;
2591 break;
2592 case macio_shasta:
2593 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_SHASTA;
2594 pmac_mb.model_name = "Unknown Shasta-based";
2595 pmac_mb.features = g5_features;
2596 break;
2597 #endif /* CONFIG_POWER4 */
2598 default:
2599 return -ENODEV;
2600 }
2601 found:
2602 #ifndef CONFIG_POWER4
2603 /* Fixup Hooper vs. Comet */
2604 if (pmac_mb.model_id == PMAC_TYPE_HOOPER) {
2605 u32 __iomem * mach_id_ptr = ioremap(0xf3000034, 4);
2606 if (!mach_id_ptr)
2607 return -ENODEV;
2608 /* Here, I used to disable the media-bay on comet. It
2609 * appears this is wrong, the floppy connector is actually
2610 * a kind of media-bay and works with the current driver.
2611 */
2612 if (__raw_readl(mach_id_ptr) & 0x20000000UL)
2613 pmac_mb.model_id = PMAC_TYPE_COMET;
2614 iounmap(mach_id_ptr);
2615 }
2616 #endif /* CONFIG_POWER4 */
2617
2618 #ifdef CONFIG_6xx
2619 /* Set default value of powersave_nap on machines that support it.
2620 * It appears that uninorth rev 3 has a problem with it, we don't
2621 * enable it on those. In theory, the flush-on-lock property is
2622 * supposed to be set when not supported, but I'm not very confident
2623 * that all Apple OF revs did it properly, I do it the paranoid way.
2624 */
2625 while (uninorth_base && uninorth_rev > 3) {
2626 struct device_node *np = find_path_device("/cpus");
2627 if (!np || !np->child) {
2628 printk(KERN_WARNING "Can't find CPU(s) in device tree !\n");
2629 break;
2630 }
2631 np = np->child;
2632 /* Nap mode not supported on SMP */
2633 if (np->sibling)
2634 break;
2635 /* Nap mode not supported if flush-on-lock property is present */
2636 if (get_property(np, "flush-on-lock", NULL))
2637 break;
2638 powersave_nap = 1;
2639 printk(KERN_INFO "Processor NAP mode on idle enabled.\n");
2640 break;
2641 }
2642
2643 /* On CPUs that support it (750FX), lowspeed by default during
2644 * NAP mode
2645 */
2646 powersave_lowspeed = 1;
2647 #endif /* CONFIG_6xx */
2648 #ifdef CONFIG_POWER4
2649 powersave_nap = 1;
2650 #endif
2651 /* Check for "mobile" machine */
2652 if (model && (strncmp(model, "PowerBook", 9) == 0
2653 || strncmp(model, "iBook", 5) == 0))
2654 pmac_mb.board_flags |= PMAC_MB_MOBILE;
2655
2656
2657 printk(KERN_INFO "PowerMac motherboard: %s\n", pmac_mb.model_name);
2658 return 0;
2659 }
2660
2661 /* Initialize the Core99 UniNorth host bridge and memory controller
2662 */
2663 static void __init probe_uninorth(void)
2664 {
2665 u32 *addrp;
2666 phys_addr_t address;
2667 unsigned long actrl;
2668
2669 /* Locate core99 Uni-N */
2670 uninorth_node = of_find_node_by_name(NULL, "uni-n");
2671 /* Locate G5 u3 */
2672 if (uninorth_node == NULL) {
2673 uninorth_node = of_find_node_by_name(NULL, "u3");
2674 uninorth_maj = 3;
2675 }
2676 /* Locate G5 u4 */
2677 if (uninorth_node == NULL) {
2678 uninorth_node = of_find_node_by_name(NULL, "u4");
2679 uninorth_maj = 4;
2680 }
2681 if (uninorth_node == NULL)
2682 return;
2683
2684 addrp = (u32 *)get_property(uninorth_node, "reg", NULL);
2685 if (addrp == NULL)
2686 return;
2687 address = of_translate_address(uninorth_node, addrp);
2688 if (address == 0)
2689 return;
2690 uninorth_base = ioremap(address, 0x40000);
2691 uninorth_rev = in_be32(UN_REG(UNI_N_VERSION));
2692 if (uninorth_maj == 3 || uninorth_maj == 4)
2693 u3_ht = ioremap(address + U3_HT_CONFIG_BASE, 0x1000);
2694
2695 printk(KERN_INFO "Found %s memory controller & host bridge"
2696 " @ 0x%08x revision: 0x%02x\n", uninorth_maj == 3 ? "U3" :
2697 uninorth_maj == 4 ? "U4" : "UniNorth",
2698 (unsigned int)address, uninorth_rev);
2699 printk(KERN_INFO "Mapped at 0x%08lx\n", (unsigned long)uninorth_base);
2700
2701 /* Set the arbitrer QAck delay according to what Apple does
2702 */
2703 if (uninorth_rev < 0x11) {
2704 actrl = UN_IN(UNI_N_ARB_CTRL) & ~UNI_N_ARB_CTRL_QACK_DELAY_MASK;
2705 actrl |= ((uninorth_rev < 3) ? UNI_N_ARB_CTRL_QACK_DELAY105 :
2706 UNI_N_ARB_CTRL_QACK_DELAY) <<
2707 UNI_N_ARB_CTRL_QACK_DELAY_SHIFT;
2708 UN_OUT(UNI_N_ARB_CTRL, actrl);
2709 }
2710
2711 /* Some more magic as done by them in recent MacOS X on UniNorth
2712 * revs 1.5 to 2.O and Pangea. Seem to toggle the UniN Maxbus/PCI
2713 * memory timeout
2714 */
2715 if ((uninorth_rev >= 0x11 && uninorth_rev <= 0x24) ||
2716 uninorth_rev == 0xc0)
2717 UN_OUT(0x2160, UN_IN(0x2160) & 0x00ffffff);
2718 }
2719
2720 static void __init probe_one_macio(const char *name, const char *compat, int type)
2721 {
2722 struct device_node* node;
2723 int i;
2724 volatile u32 __iomem *base;
2725 u32 *addrp, *revp;
2726 phys_addr_t addr;
2727 u64 size;
2728
2729 for (node = NULL; (node = of_find_node_by_name(node, name)) != NULL;) {
2730 if (!compat)
2731 break;
2732 if (device_is_compatible(node, compat))
2733 break;
2734 }
2735 if (!node)
2736 return;
2737 for(i=0; i<MAX_MACIO_CHIPS; i++) {
2738 if (!macio_chips[i].of_node)
2739 break;
2740 if (macio_chips[i].of_node == node)
2741 return;
2742 }
2743
2744 if (i >= MAX_MACIO_CHIPS) {
2745 printk(KERN_ERR "pmac_feature: Please increase MAX_MACIO_CHIPS !\n");
2746 printk(KERN_ERR "pmac_feature: %s skipped\n", node->full_name);
2747 return;
2748 }
2749 addrp = of_get_pci_address(node, 0, &size, NULL);
2750 if (addrp == NULL) {
2751 printk(KERN_ERR "pmac_feature: %s: can't find base !\n",
2752 node->full_name);
2753 return;
2754 }
2755 addr = of_translate_address(node, addrp);
2756 if (addr == 0) {
2757 printk(KERN_ERR "pmac_feature: %s, can't translate base !\n",
2758 node->full_name);
2759 return;
2760 }
2761 base = ioremap(addr, (unsigned long)size);
2762 if (!base) {
2763 printk(KERN_ERR "pmac_feature: %s, can't map mac-io chip !\n",
2764 node->full_name);
2765 return;
2766 }
2767 if (type == macio_keylargo || type == macio_keylargo2) {
2768 u32 *did = (u32 *)get_property(node, "device-id", NULL);
2769 if (*did == 0x00000025)
2770 type = macio_pangea;
2771 if (*did == 0x0000003e)
2772 type = macio_intrepid;
2773 if (*did == 0x0000004f)
2774 type = macio_shasta;
2775 }
2776 macio_chips[i].of_node = node;
2777 macio_chips[i].type = type;
2778 macio_chips[i].base = base;
2779 macio_chips[i].flags = MACIO_FLAG_SCCB_ON | MACIO_FLAG_SCCB_ON;
2780 macio_chips[i].name = macio_names[type];
2781 revp = (u32 *)get_property(node, "revision-id", NULL);
2782 if (revp)
2783 macio_chips[i].rev = *revp;
2784 printk(KERN_INFO "Found a %s mac-io controller, rev: %d, mapped at 0x%p\n",
2785 macio_names[type], macio_chips[i].rev, macio_chips[i].base);
2786 }
2787
2788 static int __init
2789 probe_macios(void)
2790 {
2791 /* Warning, ordering is important */
2792 probe_one_macio("gc", NULL, macio_grand_central);
2793 probe_one_macio("ohare", NULL, macio_ohare);
2794 probe_one_macio("pci106b,7", NULL, macio_ohareII);
2795 probe_one_macio("mac-io", "keylargo", macio_keylargo);
2796 probe_one_macio("mac-io", "paddington", macio_paddington);
2797 probe_one_macio("mac-io", "gatwick", macio_gatwick);
2798 probe_one_macio("mac-io", "heathrow", macio_heathrow);
2799 probe_one_macio("mac-io", "K2-Keylargo", macio_keylargo2);
2800
2801 /* Make sure the "main" macio chip appear first */
2802 if (macio_chips[0].type == macio_gatwick
2803 && macio_chips[1].type == macio_heathrow) {
2804 struct macio_chip temp = macio_chips[0];
2805 macio_chips[0] = macio_chips[1];
2806 macio_chips[1] = temp;
2807 }
2808 if (macio_chips[0].type == macio_ohareII
2809 && macio_chips[1].type == macio_ohare) {
2810 struct macio_chip temp = macio_chips[0];
2811 macio_chips[0] = macio_chips[1];
2812 macio_chips[1] = temp;
2813 }
2814 macio_chips[0].lbus.index = 0;
2815 macio_chips[1].lbus.index = 1;
2816
2817 return (macio_chips[0].of_node == NULL) ? -ENODEV : 0;
2818 }
2819
2820 static void __init
2821 initial_serial_shutdown(struct device_node *np)
2822 {
2823 int len;
2824 struct slot_names_prop {
2825 int count;
2826 char name[1];
2827 } *slots;
2828 char *conn;
2829 int port_type = PMAC_SCC_ASYNC;
2830 int modem = 0;
2831
2832 slots = (struct slot_names_prop *)get_property(np, "slot-names", &len);
2833 conn = get_property(np, "AAPL,connector", &len);
2834 if (conn && (strcmp(conn, "infrared") == 0))
2835 port_type = PMAC_SCC_IRDA;
2836 else if (device_is_compatible(np, "cobalt"))
2837 modem = 1;
2838 else if (slots && slots->count > 0) {
2839 if (strcmp(slots->name, "IrDA") == 0)
2840 port_type = PMAC_SCC_IRDA;
2841 else if (strcmp(slots->name, "Modem") == 0)
2842 modem = 1;
2843 }
2844 if (modem)
2845 pmac_call_feature(PMAC_FTR_MODEM_ENABLE, np, 0, 0);
2846 pmac_call_feature(PMAC_FTR_SCC_ENABLE, np, port_type, 0);
2847 }
2848
2849 static void __init
2850 set_initial_features(void)
2851 {
2852 struct device_node *np;
2853
2854 /* That hack appears to be necessary for some StarMax motherboards
2855 * but I'm not too sure it was audited for side-effects on other
2856 * ohare based machines...
2857 * Since I still have difficulties figuring the right way to
2858 * differenciate them all and since that hack was there for a long
2859 * time, I'll keep it around
2860 */
2861 if (macio_chips[0].type == macio_ohare && !find_devices("via-pmu")) {
2862 struct macio_chip *macio = &macio_chips[0];
2863 MACIO_OUT32(OHARE_FCR, STARMAX_FEATURES);
2864 } else if (macio_chips[0].type == macio_ohare) {
2865 struct macio_chip *macio = &macio_chips[0];
2866 MACIO_BIS(OHARE_FCR, OH_IOBUS_ENABLE);
2867 } else if (macio_chips[1].type == macio_ohare) {
2868 struct macio_chip *macio = &macio_chips[1];
2869 MACIO_BIS(OHARE_FCR, OH_IOBUS_ENABLE);
2870 }
2871
2872 #ifdef CONFIG_POWER4
2873 if (macio_chips[0].type == macio_keylargo2 ||
2874 macio_chips[0].type == macio_shasta) {
2875 #ifndef CONFIG_SMP
2876 /* On SMP machines running UP, we have the second CPU eating
2877 * bus cycles. We need to take it off the bus. This is done
2878 * from pmac_smp for SMP kernels running on one CPU
2879 */
2880 np = of_find_node_by_type(NULL, "cpu");
2881 if (np != NULL)
2882 np = of_find_node_by_type(np, "cpu");
2883 if (np != NULL) {
2884 g5_phy_disable_cpu1();
2885 of_node_put(np);
2886 }
2887 #endif /* CONFIG_SMP */
2888 /* Enable GMAC for now for PCI probing. It will be disabled
2889 * later on after PCI probe
2890 */
2891 np = of_find_node_by_name(NULL, "ethernet");
2892 while(np) {
2893 if (device_is_compatible(np, "K2-GMAC"))
2894 g5_gmac_enable(np, 0, 1);
2895 np = of_find_node_by_name(np, "ethernet");
2896 }
2897
2898 /* Enable FW before PCI probe. Will be disabled later on
2899 * Note: We should have a batter way to check that we are
2900 * dealing with uninorth internal cell and not a PCI cell
2901 * on the external PCI. The code below works though.
2902 */
2903 np = of_find_node_by_name(NULL, "firewire");
2904 while(np) {
2905 if (device_is_compatible(np, "pci106b,5811")) {
2906 macio_chips[0].flags |= MACIO_FLAG_FW_SUPPORTED;
2907 g5_fw_enable(np, 0, 1);
2908 }
2909 np = of_find_node_by_name(np, "firewire");
2910 }
2911 }
2912 #else /* CONFIG_POWER4 */
2913
2914 if (macio_chips[0].type == macio_keylargo ||
2915 macio_chips[0].type == macio_pangea ||
2916 macio_chips[0].type == macio_intrepid) {
2917 /* Enable GMAC for now for PCI probing. It will be disabled
2918 * later on after PCI probe
2919 */
2920 np = of_find_node_by_name(NULL, "ethernet");
2921 while(np) {
2922 if (np->parent
2923 && device_is_compatible(np->parent, "uni-north")
2924 && device_is_compatible(np, "gmac"))
2925 core99_gmac_enable(np, 0, 1);
2926 np = of_find_node_by_name(np, "ethernet");
2927 }
2928
2929 /* Enable FW before PCI probe. Will be disabled later on
2930 * Note: We should have a batter way to check that we are
2931 * dealing with uninorth internal cell and not a PCI cell
2932 * on the external PCI. The code below works though.
2933 */
2934 np = of_find_node_by_name(NULL, "firewire");
2935 while(np) {
2936 if (np->parent
2937 && device_is_compatible(np->parent, "uni-north")
2938 && (device_is_compatible(np, "pci106b,18") ||
2939 device_is_compatible(np, "pci106b,30") ||
2940 device_is_compatible(np, "pci11c1,5811"))) {
2941 macio_chips[0].flags |= MACIO_FLAG_FW_SUPPORTED;
2942 core99_firewire_enable(np, 0, 1);
2943 }
2944 np = of_find_node_by_name(np, "firewire");
2945 }
2946
2947 /* Enable ATA-100 before PCI probe. */
2948 np = of_find_node_by_name(NULL, "ata-6");
2949 while(np) {
2950 if (np->parent
2951 && device_is_compatible(np->parent, "uni-north")
2952 && device_is_compatible(np, "kauai-ata")) {
2953 core99_ata100_enable(np, 1);
2954 }
2955 np = of_find_node_by_name(np, "ata-6");
2956 }
2957
2958 /* Switch airport off */
2959 np = find_devices("radio");
2960 while(np) {
2961 if (np && np->parent == macio_chips[0].of_node) {
2962 macio_chips[0].flags |= MACIO_FLAG_AIRPORT_ON;
2963 core99_airport_enable(np, 0, 0);
2964 }
2965 np = np->next;
2966 }
2967 }
2968
2969 /* On all machines that support sound PM, switch sound off */
2970 if (macio_chips[0].of_node)
2971 pmac_do_feature_call(PMAC_FTR_SOUND_CHIP_ENABLE,
2972 macio_chips[0].of_node, 0, 0);
2973
2974 /* While on some desktop G3s, we turn it back on */
2975 if (macio_chips[0].of_node && macio_chips[0].type == macio_heathrow
2976 && (pmac_mb.model_id == PMAC_TYPE_GOSSAMER ||
2977 pmac_mb.model_id == PMAC_TYPE_SILK)) {
2978 struct macio_chip *macio = &macio_chips[0];
2979 MACIO_BIS(HEATHROW_FCR, HRW_SOUND_CLK_ENABLE);
2980 MACIO_BIC(HEATHROW_FCR, HRW_SOUND_POWER_N);
2981 }
2982
2983 /* Some machine models need the clock chip to be properly setup for
2984 * clock spreading now. This should be a platform function but we
2985 * don't do these at the moment
2986 */
2987 pmac_tweak_clock_spreading(1);
2988
2989 #endif /* CONFIG_POWER4 */
2990
2991 /* On all machines, switch modem & serial ports off */
2992 np = find_devices("ch-a");
2993 while(np) {
2994 initial_serial_shutdown(np);
2995 np = np->next;
2996 }
2997 np = find_devices("ch-b");
2998 while(np) {
2999 initial_serial_shutdown(np);
3000 np = np->next;
3001 }
3002 }
3003
3004 void __init
3005 pmac_feature_init(void)
3006 {
3007 /* Detect the UniNorth memory controller */
3008 probe_uninorth();
3009
3010 /* Probe mac-io controllers */
3011 if (probe_macios()) {
3012 printk(KERN_WARNING "No mac-io chip found\n");
3013 return;
3014 }
3015
3016 /* Setup low-level i2c stuffs */
3017 pmac_init_low_i2c();
3018
3019 /* Probe machine type */
3020 if (probe_motherboard())
3021 printk(KERN_WARNING "Unknown PowerMac !\n");
3022
3023 /* Set some initial features (turn off some chips that will
3024 * be later turned on)
3025 */
3026 set_initial_features();
3027 }
3028
3029 #if 0
3030 static void dump_HT_speeds(char *name, u32 cfg, u32 frq)
3031 {
3032 int freqs[16] = { 200,300,400,500,600,800,1000,0,0,0,0,0,0,0,0,0 };
3033 int bits[8] = { 8,16,0,32,2,4,0,0 };
3034 int freq = (frq >> 8) & 0xf;
3035
3036 if (freqs[freq] == 0)
3037 printk("%s: Unknown HT link frequency %x\n", name, freq);
3038 else
3039 printk("%s: %d MHz on main link, (%d in / %d out) bits width\n",
3040 name, freqs[freq],
3041 bits[(cfg >> 28) & 0x7], bits[(cfg >> 24) & 0x7]);
3042 }
3043
3044 void __init pmac_check_ht_link(void)
3045 {
3046 u32 ufreq, freq, ucfg, cfg;
3047 struct device_node *pcix_node;
3048 u8 px_bus, px_devfn;
3049 struct pci_controller *px_hose;
3050
3051 (void)in_be32(u3_ht + U3_HT_LINK_COMMAND);
3052 ucfg = cfg = in_be32(u3_ht + U3_HT_LINK_CONFIG);
3053 ufreq = freq = in_be32(u3_ht + U3_HT_LINK_FREQ);
3054 dump_HT_speeds("U3 HyperTransport", cfg, freq);
3055
3056 pcix_node = of_find_compatible_node(NULL, "pci", "pci-x");
3057 if (pcix_node == NULL) {
3058 printk("No PCI-X bridge found\n");
3059 return;
3060 }
3061 if (pci_device_from_OF_node(pcix_node, &px_bus, &px_devfn) != 0) {
3062 printk("PCI-X bridge found but not matched to pci\n");
3063 return;
3064 }
3065 px_hose = pci_find_hose_for_OF_device(pcix_node);
3066 if (px_hose == NULL) {
3067 printk("PCI-X bridge found but not matched to host\n");
3068 return;
3069 }
3070 early_read_config_dword(px_hose, px_bus, px_devfn, 0xc4, &cfg);
3071 early_read_config_dword(px_hose, px_bus, px_devfn, 0xcc, &freq);
3072 dump_HT_speeds("PCI-X HT Uplink", cfg, freq);
3073 early_read_config_dword(px_hose, px_bus, px_devfn, 0xc8, &cfg);
3074 early_read_config_dword(px_hose, px_bus, px_devfn, 0xd0, &freq);
3075 dump_HT_speeds("PCI-X HT Downlink", cfg, freq);
3076 }
3077 #endif /* 0 */
3078
3079 /*
3080 * Early video resume hook
3081 */
3082
3083 static void (*pmac_early_vresume_proc)(void *data);
3084 static void *pmac_early_vresume_data;
3085
3086 void pmac_set_early_video_resume(void (*proc)(void *data), void *data)
3087 {
3088 if (_machine != _MACH_Pmac)
3089 return;
3090 preempt_disable();
3091 pmac_early_vresume_proc = proc;
3092 pmac_early_vresume_data = data;
3093 preempt_enable();
3094 }
3095 EXPORT_SYMBOL(pmac_set_early_video_resume);
3096
3097 void pmac_call_early_video_resume(void)
3098 {
3099 if (pmac_early_vresume_proc)
3100 pmac_early_vresume_proc(pmac_early_vresume_data);
3101 }
3102
3103 /*
3104 * AGP related suspend/resume code
3105 */
3106
3107 static struct pci_dev *pmac_agp_bridge;
3108 static int (*pmac_agp_suspend)(struct pci_dev *bridge);
3109 static int (*pmac_agp_resume)(struct pci_dev *bridge);
3110
3111 void pmac_register_agp_pm(struct pci_dev *bridge,
3112 int (*suspend)(struct pci_dev *bridge),
3113 int (*resume)(struct pci_dev *bridge))
3114 {
3115 if (suspend || resume) {
3116 pmac_agp_bridge = bridge;
3117 pmac_agp_suspend = suspend;
3118 pmac_agp_resume = resume;
3119 return;
3120 }
3121 if (bridge != pmac_agp_bridge)
3122 return;
3123 pmac_agp_suspend = pmac_agp_resume = NULL;
3124 return;
3125 }
3126 EXPORT_SYMBOL(pmac_register_agp_pm);
3127
3128 void pmac_suspend_agp_for_card(struct pci_dev *dev)
3129 {
3130 if (pmac_agp_bridge == NULL || pmac_agp_suspend == NULL)
3131 return;
3132 if (pmac_agp_bridge->bus != dev->bus)
3133 return;
3134 pmac_agp_suspend(pmac_agp_bridge);
3135 }
3136 EXPORT_SYMBOL(pmac_suspend_agp_for_card);
3137
3138 void pmac_resume_agp_for_card(struct pci_dev *dev)
3139 {
3140 if (pmac_agp_bridge == NULL || pmac_agp_resume == NULL)
3141 return;
3142 if (pmac_agp_bridge->bus != dev->bus)
3143 return;
3144 pmac_agp_resume(pmac_agp_bridge);
3145 }
3146 EXPORT_SYMBOL(pmac_resume_agp_for_card);
Linux kernel - Deliverables
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