arch/powerpc/platforms/powernv/eeh-ioda.c

   1 /*
   2  * The file intends to implement the functions needed by EEH, which is
   3  * built on IODA compliant chip. Actually, lots of functions related
   4  * to EEH would be built based on the OPAL APIs.
   5  *
   6  * Copyright Benjamin Herrenschmidt & Gavin Shan, IBM Corporation 2013.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  */
  13
  14 #include <linux/bootmem.h>
  15 #include <linux/debugfs.h>
  16 #include <linux/delay.h>
  17 #include <linux/init.h>
  18 #include <linux/io.h>
  19 #include <linux/irq.h>
  20 #include <linux/kernel.h>
  21 #include <linux/msi.h>
  22 #include <linux/notifier.h>
  23 #include <linux/pci.h>
  24 #include <linux/string.h>
  25
  26 #include <asm/eeh.h>
  27 #include <asm/eeh_event.h>
  28 #include <asm/io.h>
  29 #include <asm/iommu.h>
  30 #include <asm/msi_bitmap.h>
  31 #include <asm/opal.h>
  32 #include <asm/pci-bridge.h>
  33 #include <asm/ppc-pci.h>
  34 #include <asm/tce.h>
  35
  36 #include "powernv.h"
  37 #include "pci.h"
  38
  39 /* Debugging option */
  40 #ifdef IODA_EEH_DBG_ON
  41 #define IODA_EEH_DBG(args...)   pr_info(args)
  42 #else
  43 #define IODA_EEH_DBG(args...)
  44 #endif
  45
  46 static char *hub_diag = NULL;
  47 static int ioda_eeh_nb_init = 0;
  48
  49 static int ioda_eeh_event(struct notifier_block *nb,
  50                           unsigned long events, void *change)
  51 {
  52         uint64_t changed_evts = (uint64_t)change;
  53
  54         /* We simply send special EEH event */
  55         if ((changed_evts & OPAL_EVENT_PCI_ERROR) &&
  56             (events & OPAL_EVENT_PCI_ERROR))
  57                 eeh_send_failure_event(NULL);
  58
  59         return 0;
  60 }
  61
  62 static struct notifier_block ioda_eeh_nb = {
  63         .notifier_call  = ioda_eeh_event,
  64         .next           = NULL,
  65         .priority       = 0
  66 };
  67
  68 #ifdef CONFIG_DEBUG_FS
  69 static int ioda_eeh_dbgfs_set(void *data, u64 val)
  70 {
  71         struct pci_controller *hose = data;
  72         struct pnv_phb *phb = hose->private_data;
  73
  74         out_be64(phb->regs + 0xD10, val);
  75         return 0;
  76 }
  77
  78 static int ioda_eeh_dbgfs_get(void *data, u64 *val)
  79 {
  80         struct pci_controller *hose = data;
  81         struct pnv_phb *phb = hose->private_data;
  82
  83         *val = in_be64(phb->regs + 0xD10);
  84         return 0;
  85 }
  86
  87 DEFINE_SIMPLE_ATTRIBUTE(ioda_eeh_dbgfs_ops, ioda_eeh_dbgfs_get,
  88                         ioda_eeh_dbgfs_set, "0x%llx\n");
  89 #endif /* CONFIG_DEBUG_FS */
  90
  91 /**
  92  * ioda_eeh_post_init - Chip dependent post initialization
  93  * @hose: PCI controller
  94  *
  95  * The function will be called after eeh PEs and devices
  96  * have been built. That means the EEH is ready to supply
  97  * service with I/O cache.
  98  */
  99 static int ioda_eeh_post_init(struct pci_controller *hose)
 100 {
 101         struct pnv_phb *phb = hose->private_data;
 102         int ret;
 103
 104         /* Register OPAL event notifier */
 105         if (!ioda_eeh_nb_init) {
 106                 ret = opal_notifier_register(&ioda_eeh_nb);
 107                 if (ret) {
 108                         pr_err("%s: Can't register OPAL event notifier (%d)\n",
 109                                __func__, ret);
 110                         return ret;
 111                 }
 112
 113                 ioda_eeh_nb_init = 1;
 114         }
 115
 116         /* FIXME: Enable it for PHB3 later */
 117         if (phb->type == PNV_PHB_IODA1) {
 118                 if (!hub_diag) {
 119                         hub_diag = (char *)__get_free_page(GFP_KERNEL |
 120                                                            __GFP_ZERO);
 121                         if (!hub_diag) {
 122                                 pr_err("%s: Out of memory !\n",
 123                                        __func__);
 124                                 return -ENOMEM;
 125                         }
 126                 }
 127
 128 #ifdef CONFIG_DEBUG_FS
 129                 if (phb->dbgfs)
 130                         debugfs_create_file("err_injct", 0600,
 131                                             phb->dbgfs, hose,
 132                                             &ioda_eeh_dbgfs_ops);
 133 #endif
 134
 135                 phb->eeh_state |= PNV_EEH_STATE_ENABLED;
 136         }
 137
 138         return 0;
 139 }
 140
 141 /**
 142  * ioda_eeh_set_option - Set EEH operation or I/O setting
 143  * @pe: EEH PE
 144  * @option: options
 145  *
 146  * Enable or disable EEH option for the indicated PE. The
 147  * function also can be used to enable I/O or DMA for the
 148  * PE.
 149  */
 150 static int ioda_eeh_set_option(struct eeh_pe *pe, int option)
 151 {
 152         s64 ret;
 153         u32 pe_no;
 154         struct pci_controller *hose = pe->phb;
 155         struct pnv_phb *phb = hose->private_data;
 156
 157         /* Check on PE number */
 158         if (pe->addr < 0 || pe->addr >= phb->ioda.total_pe) {
 159                 pr_err("%s: PE address %x out of range [0, %x] "
 160                        "on PHB#%x\n",
 161                         __func__, pe->addr, phb->ioda.total_pe,
 162                         hose->global_number);
 163                 return -EINVAL;
 164         }
 165
 166         pe_no = pe->addr;
 167         switch (option) {
 168         case EEH_OPT_DISABLE:
 169                 ret = -EEXIST;
 170                 break;
 171         case EEH_OPT_ENABLE:
 172                 ret = 0;
 173                 break;
 174         case EEH_OPT_THAW_MMIO:
 175                 ret = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no,
 176                                 OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO);
 177                 if (ret) {
 178                         pr_warning("%s: Failed to enable MMIO for "
 179                                    "PHB#%x-PE#%x, err=%lld\n",
 180                                 __func__, hose->global_number, pe_no, ret);
 181                         return -EIO;
 182                 }
 183
 184                 break;
 185         case EEH_OPT_THAW_DMA:
 186                 ret = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no,
 187                                 OPAL_EEH_ACTION_CLEAR_FREEZE_DMA);
 188                 if (ret) {
 189                         pr_warning("%s: Failed to enable DMA for "
 190                                    "PHB#%x-PE#%x, err=%lld\n",
 191                                 __func__, hose->global_number, pe_no, ret);
 192                         return -EIO;
 193                 }
 194
 195                 break;
 196         default:
 197                 pr_warning("%s: Invalid option %d\n", __func__, option);
 198                 return -EINVAL;
 199         }
 200
 201         return ret;
 202 }
 203
 204 /**
 205  * ioda_eeh_get_state - Retrieve the state of PE
 206  * @pe: EEH PE
 207  *
 208  * The PE's state should be retrieved from the PEEV, PEST
 209  * IODA tables. Since the OPAL has exported the function
 210  * to do it, it'd better to use that.
 211  */
 212 static int ioda_eeh_get_state(struct eeh_pe *pe)
 213 {
 214         s64 ret = 0;
 215         u8 fstate;
 216         u16 pcierr;
 217         u32 pe_no;
 218         int result;
 219         struct pci_controller *hose = pe->phb;
 220         struct pnv_phb *phb = hose->private_data;
 221
 222         /*
 223          * Sanity check on PE address. The PHB PE address should
 224          * be zero.
 225          */
 226         if (pe->addr < 0 || pe->addr >= phb->ioda.total_pe) {
 227                 pr_err("%s: PE address %x out of range [0, %x] "
 228                        "on PHB#%x\n",
 229                        __func__, pe->addr, phb->ioda.total_pe,
 230                        hose->global_number);
 231                 return EEH_STATE_NOT_SUPPORT;
 232         }
 233
 234         /* Retrieve PE status through OPAL */
 235         pe_no = pe->addr;
 236         ret = opal_pci_eeh_freeze_status(phb->opal_id, pe_no,
 237                         &fstate, &pcierr, NULL);
 238         if (ret) {
 239                 pr_err("%s: Failed to get EEH status on "
 240                        "PHB#%x-PE#%x\n, err=%lld\n",
 241                        __func__, hose->global_number, pe_no, ret);
 242                 return EEH_STATE_NOT_SUPPORT;
 243         }
 244
 245         /* Check PHB status */
 246         if (pe->type & EEH_PE_PHB) {
 247                 result = 0;
 248                 result &= ~EEH_STATE_RESET_ACTIVE;
 249
 250                 if (pcierr != OPAL_EEH_PHB_ERROR) {
 251                         result |= EEH_STATE_MMIO_ACTIVE;
 252                         result |= EEH_STATE_DMA_ACTIVE;
 253                         result |= EEH_STATE_MMIO_ENABLED;
 254                         result |= EEH_STATE_DMA_ENABLED;
 255                 }
 256
 257                 return result;
 258         }
 259
 260         /* Parse result out */
 261         result = 0;
 262         switch (fstate) {
 263         case OPAL_EEH_STOPPED_NOT_FROZEN:
 264                 result &= ~EEH_STATE_RESET_ACTIVE;
 265                 result |= EEH_STATE_MMIO_ACTIVE;
 266                 result |= EEH_STATE_DMA_ACTIVE;
 267                 result |= EEH_STATE_MMIO_ENABLED;
 268                 result |= EEH_STATE_DMA_ENABLED;
 269                 break;
 270         case OPAL_EEH_STOPPED_MMIO_FREEZE:
 271                 result &= ~EEH_STATE_RESET_ACTIVE;
 272                 result |= EEH_STATE_DMA_ACTIVE;
 273                 result |= EEH_STATE_DMA_ENABLED;
 274                 break;
 275         case OPAL_EEH_STOPPED_DMA_FREEZE:
 276                 result &= ~EEH_STATE_RESET_ACTIVE;
 277                 result |= EEH_STATE_MMIO_ACTIVE;
 278                 result |= EEH_STATE_MMIO_ENABLED;
 279                 break;
 280         case OPAL_EEH_STOPPED_MMIO_DMA_FREEZE:
 281                 result &= ~EEH_STATE_RESET_ACTIVE;
 282                 break;
 283         case OPAL_EEH_STOPPED_RESET:
 284                 result |= EEH_STATE_RESET_ACTIVE;
 285                 break;
 286         case OPAL_EEH_STOPPED_TEMP_UNAVAIL:
 287                 result |= EEH_STATE_UNAVAILABLE;
 288                 break;
 289         case OPAL_EEH_STOPPED_PERM_UNAVAIL:
 290                 result |= EEH_STATE_NOT_SUPPORT;
 291                 break;
 292         default:
 293                 pr_warning("%s: Unexpected EEH status 0x%x "
 294                            "on PHB#%x-PE#%x\n",
 295                            __func__, fstate, hose->global_number, pe_no);
 296         }
 297
 298         return result;
 299 }
 300
 301 static int ioda_eeh_pe_clear(struct eeh_pe *pe)
 302 {
 303         struct pci_controller *hose;
 304         struct pnv_phb *phb;
 305         u32 pe_no;
 306         u8 fstate;
 307         u16 pcierr;
 308         s64 ret;
 309
 310         pe_no = pe->addr;
 311         hose = pe->phb;
 312         phb = pe->phb->private_data;
 313
 314         /* Clear the EEH error on the PE */
 315         ret = opal_pci_eeh_freeze_clear(phb->opal_id,
 316                         pe_no, OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
 317         if (ret) {
 318                 pr_err("%s: Failed to clear EEH error for "
 319                        "PHB#%x-PE#%x, err=%lld\n",
 320                        __func__, hose->global_number, pe_no, ret);
 321                 return -EIO;
 322         }
 323
 324         /*
 325          * Read the PE state back and verify that the frozen
 326          * state has been removed.
 327          */
 328         ret = opal_pci_eeh_freeze_status(phb->opal_id, pe_no,
 329                         &fstate, &pcierr, NULL);
 330         if (ret) {
 331                 pr_err("%s: Failed to get EEH status on "
 332                        "PHB#%x-PE#%x\n, err=%lld\n",
 333                        __func__, hose->global_number, pe_no, ret);
 334                 return -EIO;
 335         }
 336
 337         if (fstate != OPAL_EEH_STOPPED_NOT_FROZEN) {
 338                 pr_err("%s: Frozen state not cleared on "
 339                        "PHB#%x-PE#%x, sts=%x\n",
 340                        __func__, hose->global_number, pe_no, fstate);
 341                 return -EIO;
 342         }
 343
 344         return 0;
 345 }
 346
 347 static s64 ioda_eeh_phb_poll(struct pnv_phb *phb)
 348 {
 349         s64 rc = OPAL_HARDWARE;
 350
 351         while (1) {
 352                 rc = opal_pci_poll(phb->opal_id);
 353                 if (rc <= 0)
 354                         break;
 355
 356                 msleep(rc);
 357         }
 358
 359         return rc;
 360 }
 361
 362 static int ioda_eeh_phb_reset(struct pci_controller *hose, int option)
 363 {
 364         struct pnv_phb *phb = hose->private_data;
 365         s64 rc = OPAL_HARDWARE;
 366
 367         pr_debug("%s: Reset PHB#%x, option=%d\n",
 368                  __func__, hose->global_number, option);
 369
 370         /* Issue PHB complete reset request */
 371         if (option == EEH_RESET_FUNDAMENTAL ||
 372             option == EEH_RESET_HOT)
 373                 rc = opal_pci_reset(phb->opal_id,
 374                                 OPAL_PHB_COMPLETE,
 375                                 OPAL_ASSERT_RESET);
 376         else if (option == EEH_RESET_DEACTIVATE)
 377                 rc = opal_pci_reset(phb->opal_id,
 378                                 OPAL_PHB_COMPLETE,
 379                                 OPAL_DEASSERT_RESET);
 380         if (rc < 0)
 381                 goto out;
 382
 383         /*
 384          * Poll state of the PHB until the request is done
 385          * successfully.
 386          */
 387         rc = ioda_eeh_phb_poll(phb);
 388 out:
 389         if (rc != OPAL_SUCCESS)
 390                 return -EIO;
 391
 392         return 0;
 393 }
 394
 395 static int ioda_eeh_root_reset(struct pci_controller *hose, int option)
 396 {
 397         struct pnv_phb *phb = hose->private_data;
 398         s64 rc = OPAL_SUCCESS;
 399
 400         pr_debug("%s: Reset PHB#%x, option=%d\n",
 401                  __func__, hose->global_number, option);
 402
 403         /*
 404          * During the reset deassert time, we needn't care
 405          * the reset scope because the firmware does nothing
 406          * for fundamental or hot reset during deassert phase.
 407          */
 408         if (option == EEH_RESET_FUNDAMENTAL)
 409                 rc = opal_pci_reset(phb->opal_id,
 410                                 OPAL_PCI_FUNDAMENTAL_RESET,
 411                                 OPAL_ASSERT_RESET);
 412         else if (option == EEH_RESET_HOT)
 413                 rc = opal_pci_reset(phb->opal_id,
 414                                 OPAL_PCI_HOT_RESET,
 415                                 OPAL_ASSERT_RESET);
 416         else if (option == EEH_RESET_DEACTIVATE)
 417                 rc = opal_pci_reset(phb->opal_id,
 418                                 OPAL_PCI_HOT_RESET,
 419                                 OPAL_DEASSERT_RESET);
 420         if (rc < 0)
 421                 goto out;
 422
 423         /* Poll state of the PHB until the request is done */
 424         rc = ioda_eeh_phb_poll(phb);
 425 out:
 426         if (rc != OPAL_SUCCESS)
 427                 return -EIO;
 428
 429         return 0;
 430 }
 431
 432 static int ioda_eeh_bridge_reset(struct pci_controller *hose,
 433                 struct pci_dev *dev, int option)
 434 {
 435         u16 ctrl;
 436
 437         pr_debug("%s: Reset device %04x:%02x:%02x.%01x with option %d\n",
 438                  __func__, hose->global_number, dev->bus->number,
 439                  PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), option);
 440
 441         switch (option) {
 442         case EEH_RESET_FUNDAMENTAL:
 443         case EEH_RESET_HOT:
 444                 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
 445                 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
 446                 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
 447                 break;
 448         case EEH_RESET_DEACTIVATE:
 449                 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
 450                 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
 451                 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
 452                 break;
 453         }
 454
 455         return 0;
 456 }
 457
 458 /**
 459  * ioda_eeh_reset - Reset the indicated PE
 460  * @pe: EEH PE
 461  * @option: reset option
 462  *
 463  * Do reset on the indicated PE. For PCI bus sensitive PE,
 464  * we need to reset the parent p2p bridge. The PHB has to
 465  * be reinitialized if the p2p bridge is root bridge. For
 466  * PCI device sensitive PE, we will try to reset the device
 467  * through FLR. For now, we don't have OPAL APIs to do HARD
 468  * reset yet, so all reset would be SOFT (HOT) reset.
 469  */
 470 static int ioda_eeh_reset(struct eeh_pe *pe, int option)
 471 {
 472         struct pci_controller *hose = pe->phb;
 473         struct eeh_dev *edev;
 474         struct pci_dev *dev;
 475         int ret;
 476
 477         /*
 478          * Anyway, we have to clear the problematic state for the
 479          * corresponding PE. However, we needn't do it if the PE
 480          * is PHB associated. That means the PHB is having fatal
 481          * errors and it needs reset. Further more, the AIB interface
 482          * isn't reliable any more.
 483          */
 484         if (!(pe->type & EEH_PE_PHB) &&
 485             (option == EEH_RESET_HOT ||
 486             option == EEH_RESET_FUNDAMENTAL)) {
 487                 ret = ioda_eeh_pe_clear(pe);
 488                 if (ret)
 489                         return -EIO;
 490         }
 491
 492         /*
 493          * The rules applied to reset, either fundamental or hot reset:
 494          *
 495          * We always reset the direct upstream bridge of the PE. If the
 496          * direct upstream bridge isn't root bridge, we always take hot
 497          * reset no matter what option (fundamental or hot) is. Otherwise,
 498          * we should do the reset according to the required option.
 499          */
 500         if (pe->type & EEH_PE_PHB) {
 501                 ret = ioda_eeh_phb_reset(hose, option);
 502         } else {
 503                 if (pe->type & EEH_PE_DEVICE) {
 504                         /*
 505                          * If it's device PE, we didn't refer to the parent
 506                          * PCI bus yet. So we have to figure it out indirectly.
 507                          */
 508                         edev = list_first_entry(&pe->edevs,
 509                                         struct eeh_dev, list);
 510                         dev = eeh_dev_to_pci_dev(edev);
 511                         dev = dev->bus->self;
 512                 } else {
 513                         /*
 514                          * If it's bus PE, the parent PCI bus is already there
 515                          * and just pick it up.
 516                          */
 517                         dev = pe->bus->self;
 518                 }
 519
 520                 /*
 521                  * Do reset based on the fact that the direct upstream bridge
 522                  * is root bridge (port) or not.
 523                  */
 524                 if (dev->bus->number == 0)
 525                         ret = ioda_eeh_root_reset(hose, option);
 526                 else
 527                         ret = ioda_eeh_bridge_reset(hose, dev, option);
 528         }
 529
 530         return ret;
 531 }
 532
 533 /**
 534  * ioda_eeh_get_log - Retrieve error log
 535  * @pe: EEH PE
 536  * @severity: Severity level of the log
 537  * @drv_log: buffer to store the log
 538  * @len: space of the log buffer
 539  *
 540  * The function is used to retrieve error log from P7IOC.
 541  */
 542 static int ioda_eeh_get_log(struct eeh_pe *pe, int severity,
 543                             char *drv_log, unsigned long len)
 544 {
 545         s64 ret;
 546         unsigned long flags;
 547         struct pci_controller *hose = pe->phb;
 548         struct pnv_phb *phb = hose->private_data;
 549
 550         spin_lock_irqsave(&phb->lock, flags);
 551
 552         ret = opal_pci_get_phb_diag_data2(phb->opal_id,
 553                         phb->diag.blob, PNV_PCI_DIAG_BUF_SIZE);
 554         if (ret) {
 555                 spin_unlock_irqrestore(&phb->lock, flags);
 556                 pr_warning("%s: Failed to get log for PHB#%x-PE#%x\n",
 557                            __func__, hose->global_number, pe->addr);
 558                 return -EIO;
 559         }
 560
 561         /*
 562          * FIXME: We probably need log the error in somewhere.
 563          * Lets make it up in future.
 564          */
 565         /* pr_info("%s", phb->diag.blob); */
 566
 567         spin_unlock_irqrestore(&phb->lock, flags);
 568
 569         return 0;
 570 }
 571
 572 /**
 573  * ioda_eeh_configure_bridge - Configure the PCI bridges for the indicated PE
 574  * @pe: EEH PE
 575  *
 576  * For particular PE, it might have included PCI bridges. In order
 577  * to make the PE work properly, those PCI bridges should be configured
 578  * correctly. However, we need do nothing on P7IOC since the reset
 579  * function will do everything that should be covered by the function.
 580  */
 581 static int ioda_eeh_configure_bridge(struct eeh_pe *pe)
 582 {
 583         return 0;
 584 }
 585
 586 static void ioda_eeh_hub_diag_common(struct OpalIoP7IOCErrorData *data)
 587 {
 588         /* GEM */
 589         pr_info("  GEM XFIR:        %016llx\n", data->gemXfir);
 590         pr_info("  GEM RFIR:        %016llx\n", data->gemRfir);
 591         pr_info("  GEM RIRQFIR:     %016llx\n", data->gemRirqfir);
 592         pr_info("  GEM Mask:        %016llx\n", data->gemMask);
 593         pr_info("  GEM RWOF:        %016llx\n", data->gemRwof);
 594
 595         /* LEM */
 596         pr_info("  LEM FIR:         %016llx\n", data->lemFir);
 597         pr_info("  LEM Error Mask:  %016llx\n", data->lemErrMask);
 598         pr_info("  LEM Action 0:    %016llx\n", data->lemAction0);
 599         pr_info("  LEM Action 1:    %016llx\n", data->lemAction1);
 600         pr_info("  LEM WOF:         %016llx\n", data->lemWof);
 601 }
 602
 603 static void ioda_eeh_hub_diag(struct pci_controller *hose)
 604 {
 605         struct pnv_phb *phb = hose->private_data;
 606         struct OpalIoP7IOCErrorData *data;
 607         long rc;
 608
 609         data = (struct OpalIoP7IOCErrorData *)ioda_eeh_hub_diag;
 610         rc = opal_pci_get_hub_diag_data(phb->hub_id, data, PAGE_SIZE);
 611         if (rc != OPAL_SUCCESS) {
 612                 pr_warning("%s: Failed to get HUB#%llx diag-data (%ld)\n",
 613                            __func__, phb->hub_id, rc);
 614                 return;
 615         }
 616
 617         switch (data->type) {
 618         case OPAL_P7IOC_DIAG_TYPE_RGC:
 619                 pr_info("P7IOC diag-data for RGC\n\n");
 620                 ioda_eeh_hub_diag_common(data);
 621                 pr_info("  RGC Status:      %016llx\n", data->rgc.rgcStatus);
 622                 pr_info("  RGC LDCP:        %016llx\n", data->rgc.rgcLdcp);
 623                 break;
 624         case OPAL_P7IOC_DIAG_TYPE_BI:
 625                 pr_info("P7IOC diag-data for BI %s\n\n",
 626                         data->bi.biDownbound ? "Downbound" : "Upbound");
 627                 ioda_eeh_hub_diag_common(data);
 628                 pr_info("  BI LDCP 0:       %016llx\n", data->bi.biLdcp0);
 629                 pr_info("  BI LDCP 1:       %016llx\n", data->bi.biLdcp1);
 630                 pr_info("  BI LDCP 2:       %016llx\n", data->bi.biLdcp2);
 631                 pr_info("  BI Fence Status: %016llx\n", data->bi.biFenceStatus);
 632                 break;
 633         case OPAL_P7IOC_DIAG_TYPE_CI:
 634                 pr_info("P7IOC diag-data for CI Port %d\\nn",
 635                         data->ci.ciPort);
 636                 ioda_eeh_hub_diag_common(data);
 637                 pr_info("  CI Port Status:  %016llx\n", data->ci.ciPortStatus);
 638                 pr_info("  CI Port LDCP:    %016llx\n", data->ci.ciPortLdcp);
 639                 break;
 640         case OPAL_P7IOC_DIAG_TYPE_MISC:
 641                 pr_info("P7IOC diag-data for MISC\n\n");
 642                 ioda_eeh_hub_diag_common(data);
 643                 break;
 644         case OPAL_P7IOC_DIAG_TYPE_I2C:
 645                 pr_info("P7IOC diag-data for I2C\n\n");
 646                 ioda_eeh_hub_diag_common(data);
 647                 break;
 648         default:
 649                 pr_warning("%s: Invalid type of HUB#%llx diag-data (%d)\n",
 650                            __func__, phb->hub_id, data->type);
 651         }
 652 }
 653
 654 static void ioda_eeh_p7ioc_phb_diag(struct pci_controller *hose,
 655                                     struct OpalIoPhbErrorCommon *common)
 656 {
 657         struct OpalIoP7IOCPhbErrorData *data;
 658         int i;
 659
 660         data = (struct OpalIoP7IOCPhbErrorData *)common;
 661
 662         pr_info("P7IOC PHB#%x Diag-data (Version: %d)\n\n",
 663                 hose->global_number, common->version);
 664
 665         pr_info("  brdgCtl:              %08x\n", data->brdgCtl);
 666
 667         pr_info("  portStatusReg:        %08x\n", data->portStatusReg);
 668         pr_info("  rootCmplxStatus:      %08x\n", data->rootCmplxStatus);
 669         pr_info("  busAgentStatus:       %08x\n", data->busAgentStatus);
 670
 671         pr_info("  deviceStatus:         %08x\n", data->deviceStatus);
 672         pr_info("  slotStatus:           %08x\n", data->slotStatus);
 673         pr_info("  linkStatus:           %08x\n", data->linkStatus);
 674         pr_info("  devCmdStatus:         %08x\n", data->devCmdStatus);
 675         pr_info("  devSecStatus:         %08x\n", data->devSecStatus);
 676
 677         pr_info("  rootErrorStatus:      %08x\n", data->rootErrorStatus);
 678         pr_info("  uncorrErrorStatus:    %08x\n", data->uncorrErrorStatus);
 679         pr_info("  corrErrorStatus:      %08x\n", data->corrErrorStatus);
 680         pr_info("  tlpHdr1:              %08x\n", data->tlpHdr1);
 681         pr_info("  tlpHdr2:              %08x\n", data->tlpHdr2);
 682         pr_info("  tlpHdr3:              %08x\n", data->tlpHdr3);
 683         pr_info("  tlpHdr4:              %08x\n", data->tlpHdr4);
 684         pr_info("  sourceId:             %08x\n", data->sourceId);
 685
 686         pr_info("  errorClass:           %016llx\n", data->errorClass);
 687         pr_info("  correlator:           %016llx\n", data->correlator);
 688         pr_info("  p7iocPlssr:           %016llx\n", data->p7iocPlssr);
 689         pr_info("  p7iocCsr:             %016llx\n", data->p7iocCsr);
 690         pr_info("  lemFir:               %016llx\n", data->lemFir);
 691         pr_info("  lemErrorMask:         %016llx\n", data->lemErrorMask);
 692         pr_info("  lemWOF:               %016llx\n", data->lemWOF);
 693         pr_info("  phbErrorStatus:       %016llx\n", data->phbErrorStatus);
 694         pr_info("  phbFirstErrorStatus:  %016llx\n", data->phbFirstErrorStatus);
 695         pr_info("  phbErrorLog0:         %016llx\n", data->phbErrorLog0);
 696         pr_info("  phbErrorLog1:         %016llx\n", data->phbErrorLog1);
 697         pr_info("  mmioErrorStatus:      %016llx\n", data->mmioErrorStatus);
 698         pr_info("  mmioFirstErrorStatus: %016llx\n", data->mmioFirstErrorStatus);
 699         pr_info("  mmioErrorLog0:        %016llx\n", data->mmioErrorLog0);
 700         pr_info("  mmioErrorLog1:        %016llx\n", data->mmioErrorLog1);
 701         pr_info("  dma0ErrorStatus:      %016llx\n", data->dma0ErrorStatus);
 702         pr_info("  dma0FirstErrorStatus: %016llx\n", data->dma0FirstErrorStatus);
 703         pr_info("  dma0ErrorLog0:        %016llx\n", data->dma0ErrorLog0);
 704         pr_info("  dma0ErrorLog1:        %016llx\n", data->dma0ErrorLog1);
 705         pr_info("  dma1ErrorStatus:      %016llx\n", data->dma1ErrorStatus);
 706         pr_info("  dma1FirstErrorStatus: %016llx\n", data->dma1FirstErrorStatus);
 707         pr_info("  dma1ErrorLog0:        %016llx\n", data->dma1ErrorLog0);
 708         pr_info("  dma1ErrorLog1:        %016llx\n", data->dma1ErrorLog1);
 709
 710         for (i = 0; i < OPAL_P7IOC_NUM_PEST_REGS; i++) {
 711                 if ((data->pestA[i] >> 63) == 0 &&
 712                     (data->pestB[i] >> 63) == 0)
 713                         continue;
 714
 715                 pr_info("  PE[%3d] PESTA:        %016llx\n", i, data->pestA[i]);
 716                 pr_info("          PESTB:        %016llx\n", data->pestB[i]);
 717         }
 718 }
 719
 720 static void ioda_eeh_phb_diag(struct pci_controller *hose)
 721 {
 722         struct pnv_phb *phb = hose->private_data;
 723         struct OpalIoPhbErrorCommon *common;
 724         long rc;
 725
 726         common = (struct OpalIoPhbErrorCommon *)phb->diag.blob;
 727         rc = opal_pci_get_phb_diag_data2(phb->opal_id, common, PAGE_SIZE);
 728         if (rc != OPAL_SUCCESS) {
 729                 pr_warning("%s: Failed to get diag-data for PHB#%x (%ld)\n",
 730                             __func__, hose->global_number, rc);
 731                 return;
 732         }
 733
 734         switch (common->ioType) {
 735         case OPAL_PHB_ERROR_DATA_TYPE_P7IOC:
 736                 ioda_eeh_p7ioc_phb_diag(hose, common);
 737                 break;
 738         default:
 739                 pr_warning("%s: Unrecognized I/O chip %d\n",
 740                            __func__, common->ioType);
 741         }
 742 }
 743
 744 static int ioda_eeh_get_phb_pe(struct pci_controller *hose,
 745                                struct eeh_pe **pe)
 746 {
 747         struct eeh_pe *phb_pe;
 748
 749         phb_pe = eeh_phb_pe_get(hose);
 750         if (!phb_pe) {
 751                 pr_warning("%s Can't find PE for PHB#%d\n",
 752                            __func__, hose->global_number);
 753                 return -EEXIST;
 754         }
 755
 756         *pe = phb_pe;
 757         return 0;
 758 }
 759
 760 static int ioda_eeh_get_pe(struct pci_controller *hose,
 761                            u16 pe_no, struct eeh_pe **pe)
 762 {
 763         struct eeh_pe *phb_pe, *dev_pe;
 764         struct eeh_dev dev;
 765
 766         /* Find the PHB PE */
 767         if (ioda_eeh_get_phb_pe(hose, &phb_pe))
 768                 return -EEXIST;
 769
 770         /* Find the PE according to PE# */
 771         memset(&dev, 0, sizeof(struct eeh_dev));
 772         dev.phb = hose;
 773         dev.pe_config_addr = pe_no;
 774         dev_pe = eeh_pe_get(&dev);
 775         if (!dev_pe) {
 776                 pr_warning("%s: Can't find PE for PHB#%x - PE#%x\n",
 777                            __func__, hose->global_number, pe_no);
 778                 return -EEXIST;
 779         }
 780
 781         *pe = dev_pe;
 782         return 0;
 783 }
 784
 785 /**
 786  * ioda_eeh_next_error - Retrieve next error for EEH core to handle
 787  * @pe: The affected PE
 788  *
 789  * The function is expected to be called by EEH core while it gets
 790  * special EEH event (without binding PE). The function calls to
 791  * OPAL APIs for next error to handle. The informational error is
 792  * handled internally by platform. However, the dead IOC, dead PHB,
 793  * fenced PHB and frozen PE should be handled by EEH core eventually.
 794  */
 795 static int ioda_eeh_next_error(struct eeh_pe **pe)
 796 {
 797         struct pci_controller *hose, *tmp;
 798         struct pnv_phb *phb;
 799         u64 frozen_pe_no;
 800         u16 err_type, severity;
 801         long rc;
 802         int ret = 1;
 803
 804         /*
 805          * While running here, it's safe to purge the event queue.
 806          * And we should keep the cached OPAL notifier event sychronized
 807          * between the kernel and firmware.
 808          */
 809         eeh_remove_event(NULL);
 810         opal_notifier_update_evt(OPAL_EVENT_PCI_ERROR, 0x0ul);
 811
 812         list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
 813                 /*
 814                  * If the subordinate PCI buses of the PHB has been
 815                  * removed, we needn't take care of it any more.
 816                  */
 817                 phb = hose->private_data;
 818                 if (phb->eeh_state & PNV_EEH_STATE_REMOVED)
 819                         continue;
 820
 821                 rc = opal_pci_next_error(phb->opal_id,
 822                                 &frozen_pe_no, &err_type, &severity);
 823
 824                 /* If OPAL API returns error, we needn't proceed */
 825                 if (rc != OPAL_SUCCESS) {
 826                         IODA_EEH_DBG("%s: Invalid return value on "
 827                                      "PHB#%x (0x%lx) from opal_pci_next_error",
 828                                      __func__, hose->global_number, rc);
 829                         continue;
 830                 }
 831
 832                 /* If the PHB doesn't have error, stop processing */
 833                 if (err_type == OPAL_EEH_NO_ERROR ||
 834                     severity == OPAL_EEH_SEV_NO_ERROR) {
 835                         IODA_EEH_DBG("%s: No error found on PHB#%x\n",
 836                                      __func__, hose->global_number);
 837                         continue;
 838                 }
 839
 840                 /*
 841                  * Processing the error. We're expecting the error with
 842                  * highest priority reported upon multiple errors on the
 843                  * specific PHB.
 844                  */
 845                 IODA_EEH_DBG("%s: Error (%d, %d, %d) on PHB#%x\n",
 846                         err_type, severity, pe_no, hose->global_number);
 847                 switch (err_type) {
 848                 case OPAL_EEH_IOC_ERROR:
 849                         if (severity == OPAL_EEH_SEV_IOC_DEAD) {
 850                                 list_for_each_entry_safe(hose, tmp,
 851                                                 &hose_list, list_node) {
 852                                         phb = hose->private_data;
 853                                         phb->eeh_state |= PNV_EEH_STATE_REMOVED;
 854                                 }
 855
 856                                 WARN(1, "EEH: dead IOC detected\n");
 857                                 ret = 4;
 858                                 goto out;
 859                         } else if (severity == OPAL_EEH_SEV_INF)
 860                                 ioda_eeh_hub_diag(hose);
 861
 862                         break;
 863                 case OPAL_EEH_PHB_ERROR:
 864                         if (severity == OPAL_EEH_SEV_PHB_DEAD) {
 865                                 if (ioda_eeh_get_phb_pe(hose, pe))
 866                                         break;
 867
 868                                 WARN(1, "EEH: dead PHB#%x detected\n",
 869                                      hose->global_number);
 870                                 phb->eeh_state |= PNV_EEH_STATE_REMOVED;
 871                                 ret = 3;
 872                                 goto out;
 873                         } else if (severity == OPAL_EEH_SEV_PHB_FENCED) {
 874                                 if (ioda_eeh_get_phb_pe(hose, pe))
 875                                         break;
 876
 877                                 WARN(1, "EEH: fenced PHB#%x detected\n",
 878                                      hose->global_number);
 879                                 ret = 2;
 880                                 goto out;
 881                         } else if (severity == OPAL_EEH_SEV_INF)
 882                                 ioda_eeh_phb_diag(hose);
 883
 884                         break;
 885                 case OPAL_EEH_PE_ERROR:
 886                         if (ioda_eeh_get_pe(hose, frozen_pe_no, pe))
 887                                 break;
 888
 889                         WARN(1, "EEH: Frozen PE#%x on PHB#%x detected\n",
 890                              (*pe)->addr, (*pe)->phb->global_number);
 891                         ret = 1;
 892                         goto out;
 893                 }
 894         }
 895
 896         ret = 0;
 897 out:
 898         return ret;
 899 }
 900
 901 struct pnv_eeh_ops ioda_eeh_ops = {
 902         .post_init              = ioda_eeh_post_init,
 903         .set_option             = ioda_eeh_set_option,
 904         .get_state              = ioda_eeh_get_state,
 905         .reset                  = ioda_eeh_reset,
 906         .get_log                = ioda_eeh_get_log,
 907         .configure_bridge       = ioda_eeh_configure_bridge,
 908         .next_error             = ioda_eeh_next_error
 909 };