arch/powerpc/platforms/powernv/eeh-ioda.c

   1 /*
   2  * The file intends to implement the functions needed by EEH, which is
   3  * built on IODA compliant chip. Actually, lots of functions related
   4  * to EEH would be built based on the OPAL APIs.
   5  *
   6  * Copyright Benjamin Herrenschmidt & Gavin Shan, IBM Corporation 2013.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  */
  13
  14 #include <linux/bootmem.h>
  15 #include <linux/delay.h>
  16 #include <linux/init.h>
  17 #include <linux/io.h>
  18 #include <linux/irq.h>
  19 #include <linux/kernel.h>
  20 #include <linux/msi.h>
  21 #include <linux/pci.h>
  22 #include <linux/string.h>
  23
  24 #include <asm/eeh.h>
  25 #include <asm/eeh_event.h>
  26 #include <asm/io.h>
  27 #include <asm/iommu.h>
  28 #include <asm/msi_bitmap.h>
  29 #include <asm/opal.h>
  30 #include <asm/pci-bridge.h>
  31 #include <asm/ppc-pci.h>
  32 #include <asm/tce.h>
  33
  34 #include "powernv.h"
  35 #include "pci.h"
  36
  37 /* Debugging option */
  38 #ifdef IODA_EEH_DBG_ON
  39 #define IODA_EEH_DBG(args...)   pr_info(args)
  40 #else
  41 #define IODA_EEH_DBG(args...)
  42 #endif
  43
  44 static char *hub_diag = NULL;
  45
  46 /**
  47  * ioda_eeh_post_init - Chip dependent post initialization
  48  * @hose: PCI controller
  49  *
  50  * The function will be called after eeh PEs and devices
  51  * have been built. That means the EEH is ready to supply
  52  * service with I/O cache.
  53  */
  54 static int ioda_eeh_post_init(struct pci_controller *hose)
  55 {
  56         struct pnv_phb *phb = hose->private_data;
  57
  58         /* FIXME: Enable it for PHB3 later */
  59         if (phb->type == PNV_PHB_IODA1) {
  60                 if (!hub_diag) {
  61                         hub_diag = (char *)__get_free_page(GFP_KERNEL |
  62                                                            __GFP_ZERO);
  63                         if (!hub_diag) {
  64                                 pr_err("%s: Out of memory !\n",
  65                                        __func__);
  66                                 return -ENOMEM;
  67                         }
  68                 }
  69
  70                 phb->eeh_enabled = 1;
  71         }
  72
  73         return 0;
  74 }
  75
  76 /**
  77  * ioda_eeh_set_option - Set EEH operation or I/O setting
  78  * @pe: EEH PE
  79  * @option: options
  80  *
  81  * Enable or disable EEH option for the indicated PE. The
  82  * function also can be used to enable I/O or DMA for the
  83  * PE.
  84  */
  85 static int ioda_eeh_set_option(struct eeh_pe *pe, int option)
  86 {
  87         s64 ret;
  88         u32 pe_no;
  89         struct pci_controller *hose = pe->phb;
  90         struct pnv_phb *phb = hose->private_data;
  91
  92         /* Check on PE number */
  93         if (pe->addr < 0 || pe->addr >= phb->ioda.total_pe) {
  94                 pr_err("%s: PE address %x out of range [0, %x] "
  95                        "on PHB#%x\n",
  96                         __func__, pe->addr, phb->ioda.total_pe,
  97                         hose->global_number);
  98                 return -EINVAL;
  99         }
 100
 101         pe_no = pe->addr;
 102         switch (option) {
 103         case EEH_OPT_DISABLE:
 104                 ret = -EEXIST;
 105                 break;
 106         case EEH_OPT_ENABLE:
 107                 ret = 0;
 108                 break;
 109         case EEH_OPT_THAW_MMIO:
 110                 ret = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no,
 111                                 OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO);
 112                 if (ret) {
 113                         pr_warning("%s: Failed to enable MMIO for "
 114                                    "PHB#%x-PE#%x, err=%lld\n",
 115                                 __func__, hose->global_number, pe_no, ret);
 116                         return -EIO;
 117                 }
 118
 119                 break;
 120         case EEH_OPT_THAW_DMA:
 121                 ret = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no,
 122                                 OPAL_EEH_ACTION_CLEAR_FREEZE_DMA);
 123                 if (ret) {
 124                         pr_warning("%s: Failed to enable DMA for "
 125                                    "PHB#%x-PE#%x, err=%lld\n",
 126                                 __func__, hose->global_number, pe_no, ret);
 127                         return -EIO;
 128                 }
 129
 130                 break;
 131         default:
 132                 pr_warning("%s: Invalid option %d\n", __func__, option);
 133                 return -EINVAL;
 134         }
 135
 136         return ret;
 137 }
 138
 139 /**
 140  * ioda_eeh_get_state - Retrieve the state of PE
 141  * @pe: EEH PE
 142  *
 143  * The PE's state should be retrieved from the PEEV, PEST
 144  * IODA tables. Since the OPAL has exported the function
 145  * to do it, it'd better to use that.
 146  */
 147 static int ioda_eeh_get_state(struct eeh_pe *pe)
 148 {
 149         s64 ret = 0;
 150         u8 fstate;
 151         u16 pcierr;
 152         u32 pe_no;
 153         int result;
 154         struct pci_controller *hose = pe->phb;
 155         struct pnv_phb *phb = hose->private_data;
 156
 157         /*
 158          * Sanity check on PE address. The PHB PE address should
 159          * be zero.
 160          */
 161         if (pe->addr < 0 || pe->addr >= phb->ioda.total_pe) {
 162                 pr_err("%s: PE address %x out of range [0, %x] "
 163                        "on PHB#%x\n",
 164                        __func__, pe->addr, phb->ioda.total_pe,
 165                        hose->global_number);
 166                 return EEH_STATE_NOT_SUPPORT;
 167         }
 168
 169         /* Retrieve PE status through OPAL */
 170         pe_no = pe->addr;
 171         ret = opal_pci_eeh_freeze_status(phb->opal_id, pe_no,
 172                         &fstate, &pcierr, NULL);
 173         if (ret) {
 174                 pr_err("%s: Failed to get EEH status on "
 175                        "PHB#%x-PE#%x\n, err=%lld\n",
 176                        __func__, hose->global_number, pe_no, ret);
 177                 return EEH_STATE_NOT_SUPPORT;
 178         }
 179
 180         /* Check PHB status */
 181         if (pe->type & EEH_PE_PHB) {
 182                 result = 0;
 183                 result &= ~EEH_STATE_RESET_ACTIVE;
 184
 185                 if (pcierr != OPAL_EEH_PHB_ERROR) {
 186                         result |= EEH_STATE_MMIO_ACTIVE;
 187                         result |= EEH_STATE_DMA_ACTIVE;
 188                         result |= EEH_STATE_MMIO_ENABLED;
 189                         result |= EEH_STATE_DMA_ENABLED;
 190                 }
 191
 192                 return result;
 193         }
 194
 195         /* Parse result out */
 196         result = 0;
 197         switch (fstate) {
 198         case OPAL_EEH_STOPPED_NOT_FROZEN:
 199                 result &= ~EEH_STATE_RESET_ACTIVE;
 200                 result |= EEH_STATE_MMIO_ACTIVE;
 201                 result |= EEH_STATE_DMA_ACTIVE;
 202                 result |= EEH_STATE_MMIO_ENABLED;
 203                 result |= EEH_STATE_DMA_ENABLED;
 204                 break;
 205         case OPAL_EEH_STOPPED_MMIO_FREEZE:
 206                 result &= ~EEH_STATE_RESET_ACTIVE;
 207                 result |= EEH_STATE_DMA_ACTIVE;
 208                 result |= EEH_STATE_DMA_ENABLED;
 209                 break;
 210         case OPAL_EEH_STOPPED_DMA_FREEZE:
 211                 result &= ~EEH_STATE_RESET_ACTIVE;
 212                 result |= EEH_STATE_MMIO_ACTIVE;
 213                 result |= EEH_STATE_MMIO_ENABLED;
 214                 break;
 215         case OPAL_EEH_STOPPED_MMIO_DMA_FREEZE:
 216                 result &= ~EEH_STATE_RESET_ACTIVE;
 217                 break;
 218         case OPAL_EEH_STOPPED_RESET:
 219                 result |= EEH_STATE_RESET_ACTIVE;
 220                 break;
 221         case OPAL_EEH_STOPPED_TEMP_UNAVAIL:
 222                 result |= EEH_STATE_UNAVAILABLE;
 223                 break;
 224         case OPAL_EEH_STOPPED_PERM_UNAVAIL:
 225                 result |= EEH_STATE_NOT_SUPPORT;
 226                 break;
 227         default:
 228                 pr_warning("%s: Unexpected EEH status 0x%x "
 229                            "on PHB#%x-PE#%x\n",
 230                            __func__, fstate, hose->global_number, pe_no);
 231         }
 232
 233         return result;
 234 }
 235
 236 static int ioda_eeh_pe_clear(struct eeh_pe *pe)
 237 {
 238         struct pci_controller *hose;
 239         struct pnv_phb *phb;
 240         u32 pe_no;
 241         u8 fstate;
 242         u16 pcierr;
 243         s64 ret;
 244
 245         pe_no = pe->addr;
 246         hose = pe->phb;
 247         phb = pe->phb->private_data;
 248
 249         /* Clear the EEH error on the PE */
 250         ret = opal_pci_eeh_freeze_clear(phb->opal_id,
 251                         pe_no, OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
 252         if (ret) {
 253                 pr_err("%s: Failed to clear EEH error for "
 254                        "PHB#%x-PE#%x, err=%lld\n",
 255                        __func__, hose->global_number, pe_no, ret);
 256                 return -EIO;
 257         }
 258
 259         /*
 260          * Read the PE state back and verify that the frozen
 261          * state has been removed.
 262          */
 263         ret = opal_pci_eeh_freeze_status(phb->opal_id, pe_no,
 264                         &fstate, &pcierr, NULL);
 265         if (ret) {
 266                 pr_err("%s: Failed to get EEH status on "
 267                        "PHB#%x-PE#%x\n, err=%lld\n",
 268                        __func__, hose->global_number, pe_no, ret);
 269                 return -EIO;
 270         }
 271
 272         if (fstate != OPAL_EEH_STOPPED_NOT_FROZEN) {
 273                 pr_err("%s: Frozen state not cleared on "
 274                        "PHB#%x-PE#%x, sts=%x\n",
 275                        __func__, hose->global_number, pe_no, fstate);
 276                 return -EIO;
 277         }
 278
 279         return 0;
 280 }
 281
 282 static s64 ioda_eeh_phb_poll(struct pnv_phb *phb)
 283 {
 284         s64 rc = OPAL_HARDWARE;
 285
 286         while (1) {
 287                 rc = opal_pci_poll(phb->opal_id);
 288                 if (rc <= 0)
 289                         break;
 290
 291                 msleep(rc);
 292         }
 293
 294         return rc;
 295 }
 296
 297 static int ioda_eeh_phb_reset(struct pci_controller *hose, int option)
 298 {
 299         struct pnv_phb *phb = hose->private_data;
 300         s64 rc = OPAL_HARDWARE;
 301
 302         pr_debug("%s: Reset PHB#%x, option=%d\n",
 303                  __func__, hose->global_number, option);
 304
 305         /* Issue PHB complete reset request */
 306         if (option == EEH_RESET_FUNDAMENTAL ||
 307             option == EEH_RESET_HOT)
 308                 rc = opal_pci_reset(phb->opal_id,
 309                                 OPAL_PHB_COMPLETE,
 310                                 OPAL_ASSERT_RESET);
 311         else if (option == EEH_RESET_DEACTIVATE)
 312                 rc = opal_pci_reset(phb->opal_id,
 313                                 OPAL_PHB_COMPLETE,
 314                                 OPAL_DEASSERT_RESET);
 315         if (rc < 0)
 316                 goto out;
 317
 318         /*
 319          * Poll state of the PHB until the request is done
 320          * successfully.
 321          */
 322         rc = ioda_eeh_phb_poll(phb);
 323 out:
 324         if (rc != OPAL_SUCCESS)
 325                 return -EIO;
 326
 327         return 0;
 328 }
 329
 330 static int ioda_eeh_root_reset(struct pci_controller *hose, int option)
 331 {
 332         struct pnv_phb *phb = hose->private_data;
 333         s64 rc = OPAL_SUCCESS;
 334
 335         pr_debug("%s: Reset PHB#%x, option=%d\n",
 336                  __func__, hose->global_number, option);
 337
 338         /*
 339          * During the reset deassert time, we needn't care
 340          * the reset scope because the firmware does nothing
 341          * for fundamental or hot reset during deassert phase.
 342          */
 343         if (option == EEH_RESET_FUNDAMENTAL)
 344                 rc = opal_pci_reset(phb->opal_id,
 345                                 OPAL_PCI_FUNDAMENTAL_RESET,
 346                                 OPAL_ASSERT_RESET);
 347         else if (option == EEH_RESET_HOT)
 348                 rc = opal_pci_reset(phb->opal_id,
 349                                 OPAL_PCI_HOT_RESET,
 350                                 OPAL_ASSERT_RESET);
 351         else if (option == EEH_RESET_DEACTIVATE)
 352                 rc = opal_pci_reset(phb->opal_id,
 353                                 OPAL_PCI_HOT_RESET,
 354                                 OPAL_DEASSERT_RESET);
 355         if (rc < 0)
 356                 goto out;
 357
 358         /* Poll state of the PHB until the request is done */
 359         rc = ioda_eeh_phb_poll(phb);
 360 out:
 361         if (rc != OPAL_SUCCESS)
 362                 return -EIO;
 363
 364         return 0;
 365 }
 366
 367 static int ioda_eeh_bridge_reset(struct pci_controller *hose,
 368                 struct pci_dev *dev, int option)
 369 {
 370         u16 ctrl;
 371
 372         pr_debug("%s: Reset device %04x:%02x:%02x.%01x with option %d\n",
 373                  __func__, hose->global_number, dev->bus->number,
 374                  PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), option);
 375
 376         switch (option) {
 377         case EEH_RESET_FUNDAMENTAL:
 378         case EEH_RESET_HOT:
 379                 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
 380                 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
 381                 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
 382                 break;
 383         case EEH_RESET_DEACTIVATE:
 384                 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
 385                 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
 386                 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
 387                 break;
 388         }
 389
 390         return 0;
 391 }
 392
 393 /**
 394  * ioda_eeh_reset - Reset the indicated PE
 395  * @pe: EEH PE
 396  * @option: reset option
 397  *
 398  * Do reset on the indicated PE. For PCI bus sensitive PE,
 399  * we need to reset the parent p2p bridge. The PHB has to
 400  * be reinitialized if the p2p bridge is root bridge. For
 401  * PCI device sensitive PE, we will try to reset the device
 402  * through FLR. For now, we don't have OPAL APIs to do HARD
 403  * reset yet, so all reset would be SOFT (HOT) reset.
 404  */
 405 static int ioda_eeh_reset(struct eeh_pe *pe, int option)
 406 {
 407         struct pci_controller *hose = pe->phb;
 408         struct eeh_dev *edev;
 409         struct pci_dev *dev;
 410         int ret;
 411
 412         /*
 413          * Anyway, we have to clear the problematic state for the
 414          * corresponding PE. However, we needn't do it if the PE
 415          * is PHB associated. That means the PHB is having fatal
 416          * errors and it needs reset. Further more, the AIB interface
 417          * isn't reliable any more.
 418          */
 419         if (!(pe->type & EEH_PE_PHB) &&
 420             (option == EEH_RESET_HOT ||
 421             option == EEH_RESET_FUNDAMENTAL)) {
 422                 ret = ioda_eeh_pe_clear(pe);
 423                 if (ret)
 424                         return -EIO;
 425         }
 426
 427         /*
 428          * The rules applied to reset, either fundamental or hot reset:
 429          *
 430          * We always reset the direct upstream bridge of the PE. If the
 431          * direct upstream bridge isn't root bridge, we always take hot
 432          * reset no matter what option (fundamental or hot) is. Otherwise,
 433          * we should do the reset according to the required option.
 434          */
 435         if (pe->type & EEH_PE_PHB) {
 436                 ret = ioda_eeh_phb_reset(hose, option);
 437         } else {
 438                 if (pe->type & EEH_PE_DEVICE) {
 439                         /*
 440                          * If it's device PE, we didn't refer to the parent
 441                          * PCI bus yet. So we have to figure it out indirectly.
 442                          */
 443                         edev = list_first_entry(&pe->edevs,
 444                                         struct eeh_dev, list);
 445                         dev = eeh_dev_to_pci_dev(edev);
 446                         dev = dev->bus->self;
 447                 } else {
 448                         /*
 449                          * If it's bus PE, the parent PCI bus is already there
 450                          * and just pick it up.
 451                          */
 452                         dev = pe->bus->self;
 453                 }
 454
 455                 /*
 456                  * Do reset based on the fact that the direct upstream bridge
 457                  * is root bridge (port) or not.
 458                  */
 459                 if (dev->bus->number == 0)
 460                         ret = ioda_eeh_root_reset(hose, option);
 461                 else
 462                         ret = ioda_eeh_bridge_reset(hose, dev, option);
 463         }
 464
 465         return ret;
 466 }
 467
 468 /**
 469  * ioda_eeh_get_log - Retrieve error log
 470  * @pe: EEH PE
 471  * @severity: Severity level of the log
 472  * @drv_log: buffer to store the log
 473  * @len: space of the log buffer
 474  *
 475  * The function is used to retrieve error log from P7IOC.
 476  */
 477 static int ioda_eeh_get_log(struct eeh_pe *pe, int severity,
 478                             char *drv_log, unsigned long len)
 479 {
 480         s64 ret;
 481         unsigned long flags;
 482         struct pci_controller *hose = pe->phb;
 483         struct pnv_phb *phb = hose->private_data;
 484
 485         spin_lock_irqsave(&phb->lock, flags);
 486
 487         ret = opal_pci_get_phb_diag_data2(phb->opal_id,
 488                         phb->diag.blob, PNV_PCI_DIAG_BUF_SIZE);
 489         if (ret) {
 490                 spin_unlock_irqrestore(&phb->lock, flags);
 491                 pr_warning("%s: Failed to get log for PHB#%x-PE#%x\n",
 492                            __func__, hose->global_number, pe->addr);
 493                 return -EIO;
 494         }
 495
 496         /*
 497          * FIXME: We probably need log the error in somewhere.
 498          * Lets make it up in future.
 499          */
 500         /* pr_info("%s", phb->diag.blob); */
 501
 502         spin_unlock_irqrestore(&phb->lock, flags);
 503
 504         return 0;
 505 }
 506
 507 /**
 508  * ioda_eeh_configure_bridge - Configure the PCI bridges for the indicated PE
 509  * @pe: EEH PE
 510  *
 511  * For particular PE, it might have included PCI bridges. In order
 512  * to make the PE work properly, those PCI bridges should be configured
 513  * correctly. However, we need do nothing on P7IOC since the reset
 514  * function will do everything that should be covered by the function.
 515  */
 516 static int ioda_eeh_configure_bridge(struct eeh_pe *pe)
 517 {
 518         return 0;
 519 }
 520
 521 static void ioda_eeh_hub_diag_common(struct OpalIoP7IOCErrorData *data)
 522 {
 523         /* GEM */
 524         pr_info("  GEM XFIR:        %016llx\n", data->gemXfir);
 525         pr_info("  GEM RFIR:        %016llx\n", data->gemRfir);
 526         pr_info("  GEM RIRQFIR:     %016llx\n", data->gemRirqfir);
 527         pr_info("  GEM Mask:        %016llx\n", data->gemMask);
 528         pr_info("  GEM RWOF:        %016llx\n", data->gemRwof);
 529
 530         /* LEM */
 531         pr_info("  LEM FIR:         %016llx\n", data->lemFir);
 532         pr_info("  LEM Error Mask:  %016llx\n", data->lemErrMask);
 533         pr_info("  LEM Action 0:    %016llx\n", data->lemAction0);
 534         pr_info("  LEM Action 1:    %016llx\n", data->lemAction1);
 535         pr_info("  LEM WOF:         %016llx\n", data->lemWof);
 536 }
 537
 538 static void ioda_eeh_hub_diag(struct pci_controller *hose)
 539 {
 540         struct pnv_phb *phb = hose->private_data;
 541         struct OpalIoP7IOCErrorData *data;
 542         long rc;
 543
 544         data = (struct OpalIoP7IOCErrorData *)ioda_eeh_hub_diag;
 545         rc = opal_pci_get_hub_diag_data(phb->hub_id, data, PAGE_SIZE);
 546         if (rc != OPAL_SUCCESS) {
 547                 pr_warning("%s: Failed to get HUB#%llx diag-data (%ld)\n",
 548                            __func__, phb->hub_id, rc);
 549                 return;
 550         }
 551
 552         switch (data->type) {
 553         case OPAL_P7IOC_DIAG_TYPE_RGC:
 554                 pr_info("P7IOC diag-data for RGC\n\n");
 555                 ioda_eeh_hub_diag_common(data);
 556                 pr_info("  RGC Status:      %016llx\n", data->rgc.rgcStatus);
 557                 pr_info("  RGC LDCP:        %016llx\n", data->rgc.rgcLdcp);
 558                 break;
 559         case OPAL_P7IOC_DIAG_TYPE_BI:
 560                 pr_info("P7IOC diag-data for BI %s\n\n",
 561                         data->bi.biDownbound ? "Downbound" : "Upbound");
 562                 ioda_eeh_hub_diag_common(data);
 563                 pr_info("  BI LDCP 0:       %016llx\n", data->bi.biLdcp0);
 564                 pr_info("  BI LDCP 1:       %016llx\n", data->bi.biLdcp1);
 565                 pr_info("  BI LDCP 2:       %016llx\n", data->bi.biLdcp2);
 566                 pr_info("  BI Fence Status: %016llx\n", data->bi.biFenceStatus);
 567                 break;
 568         case OPAL_P7IOC_DIAG_TYPE_CI:
 569                 pr_info("P7IOC diag-data for CI Port %d\\nn",
 570                         data->ci.ciPort);
 571                 ioda_eeh_hub_diag_common(data);
 572                 pr_info("  CI Port Status:  %016llx\n", data->ci.ciPortStatus);
 573                 pr_info("  CI Port LDCP:    %016llx\n", data->ci.ciPortLdcp);
 574                 break;
 575         case OPAL_P7IOC_DIAG_TYPE_MISC:
 576                 pr_info("P7IOC diag-data for MISC\n\n");
 577                 ioda_eeh_hub_diag_common(data);
 578                 break;
 579         case OPAL_P7IOC_DIAG_TYPE_I2C:
 580                 pr_info("P7IOC diag-data for I2C\n\n");
 581                 ioda_eeh_hub_diag_common(data);
 582                 break;
 583         default:
 584                 pr_warning("%s: Invalid type of HUB#%llx diag-data (%d)\n",
 585                            __func__, phb->hub_id, data->type);
 586         }
 587 }
 588
 589 static void ioda_eeh_p7ioc_phb_diag(struct pci_controller *hose,
 590                                     struct OpalIoPhbErrorCommon *common)
 591 {
 592         struct OpalIoP7IOCPhbErrorData *data;
 593         int i;
 594
 595         data = (struct OpalIoP7IOCPhbErrorData *)common;
 596
 597         pr_info("P7IOC PHB#%x Diag-data (Version: %d)\n\n",
 598                 hose->global_number, common->version);
 599
 600         pr_info("  brdgCtl:              %08x\n", data->brdgCtl);
 601
 602         pr_info("  portStatusReg:        %08x\n", data->portStatusReg);
 603         pr_info("  rootCmplxStatus:      %08x\n", data->rootCmplxStatus);
 604         pr_info("  busAgentStatus:       %08x\n", data->busAgentStatus);
 605
 606         pr_info("  deviceStatus:         %08x\n", data->deviceStatus);
 607         pr_info("  slotStatus:           %08x\n", data->slotStatus);
 608         pr_info("  linkStatus:           %08x\n", data->linkStatus);
 609         pr_info("  devCmdStatus:         %08x\n", data->devCmdStatus);
 610         pr_info("  devSecStatus:         %08x\n", data->devSecStatus);
 611
 612         pr_info("  rootErrorStatus:      %08x\n", data->rootErrorStatus);
 613         pr_info("  uncorrErrorStatus:    %08x\n", data->uncorrErrorStatus);
 614         pr_info("  corrErrorStatus:      %08x\n", data->corrErrorStatus);
 615         pr_info("  tlpHdr1:              %08x\n", data->tlpHdr1);
 616         pr_info("  tlpHdr2:              %08x\n", data->tlpHdr2);
 617         pr_info("  tlpHdr3:              %08x\n", data->tlpHdr3);
 618         pr_info("  tlpHdr4:              %08x\n", data->tlpHdr4);
 619         pr_info("  sourceId:             %08x\n", data->sourceId);
 620
 621         pr_info("  errorClass:           %016llx\n", data->errorClass);
 622         pr_info("  correlator:           %016llx\n", data->correlator);
 623         pr_info("  p7iocPlssr:           %016llx\n", data->p7iocPlssr);
 624         pr_info("  p7iocCsr:             %016llx\n", data->p7iocCsr);
 625         pr_info("  lemFir:               %016llx\n", data->lemFir);
 626         pr_info("  lemErrorMask:         %016llx\n", data->lemErrorMask);
 627         pr_info("  lemWOF:               %016llx\n", data->lemWOF);
 628         pr_info("  phbErrorStatus:       %016llx\n", data->phbErrorStatus);
 629         pr_info("  phbFirstErrorStatus:  %016llx\n", data->phbFirstErrorStatus);
 630         pr_info("  phbErrorLog0:         %016llx\n", data->phbErrorLog0);
 631         pr_info("  phbErrorLog1:         %016llx\n", data->phbErrorLog1);
 632         pr_info("  mmioErrorStatus:      %016llx\n", data->mmioErrorStatus);
 633         pr_info("  mmioFirstErrorStatus: %016llx\n", data->mmioFirstErrorStatus);
 634         pr_info("  mmioErrorLog0:        %016llx\n", data->mmioErrorLog0);
 635         pr_info("  mmioErrorLog1:        %016llx\n", data->mmioErrorLog1);
 636         pr_info("  dma0ErrorStatus:      %016llx\n", data->dma0ErrorStatus);
 637         pr_info("  dma0FirstErrorStatus: %016llx\n", data->dma0FirstErrorStatus);
 638         pr_info("  dma0ErrorLog0:        %016llx\n", data->dma0ErrorLog0);
 639         pr_info("  dma0ErrorLog1:        %016llx\n", data->dma0ErrorLog1);
 640         pr_info("  dma1ErrorStatus:      %016llx\n", data->dma1ErrorStatus);
 641         pr_info("  dma1FirstErrorStatus: %016llx\n", data->dma1FirstErrorStatus);
 642         pr_info("  dma1ErrorLog0:        %016llx\n", data->dma1ErrorLog0);
 643         pr_info("  dma1ErrorLog1:        %016llx\n", data->dma1ErrorLog1);
 644
 645         for (i = 0; i < OPAL_P7IOC_NUM_PEST_REGS; i++) {
 646                 if ((data->pestA[i] >> 63) == 0 &&
 647                     (data->pestB[i] >> 63) == 0)
 648                         continue;
 649
 650                 pr_info("  PE[%3d] PESTA:        %016llx\n", i, data->pestA[i]);
 651                 pr_info("          PESTB:        %016llx\n", data->pestB[i]);
 652         }
 653 }
 654
 655 static void ioda_eeh_phb_diag(struct pci_controller *hose)
 656 {
 657         struct pnv_phb *phb = hose->private_data;
 658         struct OpalIoPhbErrorCommon *common;
 659         long rc;
 660
 661         common = (struct OpalIoPhbErrorCommon *)phb->diag.blob;
 662         rc = opal_pci_get_phb_diag_data2(phb->opal_id, common, PAGE_SIZE);
 663         if (rc != OPAL_SUCCESS) {
 664                 pr_warning("%s: Failed to get diag-data for PHB#%x (%ld)\n",
 665                             __func__, hose->global_number, rc);
 666                 return;
 667         }
 668
 669         switch (common->ioType) {
 670         case OPAL_PHB_ERROR_DATA_TYPE_P7IOC:
 671                 ioda_eeh_p7ioc_phb_diag(hose, common);
 672                 break;
 673         default:
 674                 pr_warning("%s: Unrecognized I/O chip %d\n",
 675                            __func__, common->ioType);
 676         }
 677 }
 678
 679 static int ioda_eeh_get_phb_pe(struct pci_controller *hose,
 680                                struct eeh_pe **pe)
 681 {
 682         struct eeh_pe *phb_pe;
 683
 684         phb_pe = eeh_phb_pe_get(hose);
 685         if (!phb_pe) {
 686                 pr_warning("%s Can't find PE for PHB#%d\n",
 687                            __func__, hose->global_number);
 688                 return -EEXIST;
 689         }
 690
 691         *pe = phb_pe;
 692         return 0;
 693 }
 694
 695 static int ioda_eeh_get_pe(struct pci_controller *hose,
 696                            u16 pe_no, struct eeh_pe **pe)
 697 {
 698         struct eeh_pe *phb_pe, *dev_pe;
 699         struct eeh_dev dev;
 700
 701         /* Find the PHB PE */
 702         if (ioda_eeh_get_phb_pe(hose, &phb_pe))
 703                 return -EEXIST;
 704
 705         /* Find the PE according to PE# */
 706         memset(&dev, 0, sizeof(struct eeh_dev));
 707         dev.phb = hose;
 708         dev.pe_config_addr = pe_no;
 709         dev_pe = eeh_pe_get(&dev);
 710         if (!dev_pe) {
 711                 pr_warning("%s: Can't find PE for PHB#%x - PE#%x\n",
 712                            __func__, hose->global_number, pe_no);
 713                 return -EEXIST;
 714         }
 715
 716         *pe = dev_pe;
 717         return 0;
 718 }
 719
 720 /**
 721  * ioda_eeh_next_error - Retrieve next error for EEH core to handle
 722  * @pe: The affected PE
 723  *
 724  * The function is expected to be called by EEH core while it gets
 725  * special EEH event (without binding PE). The function calls to
 726  * OPAL APIs for next error to handle. The informational error is
 727  * handled internally by platform. However, the dead IOC, dead PHB,
 728  * fenced PHB and frozen PE should be handled by EEH core eventually.
 729  */
 730 static int ioda_eeh_next_error(struct eeh_pe **pe)
 731 {
 732         struct pci_controller *hose, *tmp;
 733         struct pnv_phb *phb;
 734         u64 frozen_pe_no;
 735         u16 err_type, severity;
 736         long rc;
 737         int ret = 1;
 738
 739         /* While running here, it's safe to purge the event queue */
 740         eeh_remove_event(NULL);
 741
 742         list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
 743                 /*
 744                  * If the subordinate PCI buses of the PHB has been
 745                  * removed, we needn't take care of it any more.
 746                  */
 747                 phb = hose->private_data;
 748                 if (phb->removed)
 749                         continue;
 750
 751                 rc = opal_pci_next_error(phb->opal_id,
 752                                 &frozen_pe_no, &err_type, &severity);
 753
 754                 /* If OPAL API returns error, we needn't proceed */
 755                 if (rc != OPAL_SUCCESS) {
 756                         IODA_EEH_DBG("%s: Invalid return value on "
 757                                      "PHB#%x (0x%lx) from opal_pci_next_error",
 758                                      __func__, hose->global_number, rc);
 759                         continue;
 760                 }
 761
 762                 /* If the PHB doesn't have error, stop processing */
 763                 if (err_type == OPAL_EEH_NO_ERROR ||
 764                     severity == OPAL_EEH_SEV_NO_ERROR) {
 765                         IODA_EEH_DBG("%s: No error found on PHB#%x\n",
 766                                      __func__, hose->global_number);
 767                         continue;
 768                 }
 769
 770                 /*
 771                  * Processing the error. We're expecting the error with
 772                  * highest priority reported upon multiple errors on the
 773                  * specific PHB.
 774                  */
 775                 IODA_EEH_DBG("%s: Error (%d, %d, %d) on PHB#%x\n",
 776                         err_type, severity, pe_no, hose->global_number);
 777                 switch (err_type) {
 778                 case OPAL_EEH_IOC_ERROR:
 779                         if (severity == OPAL_EEH_SEV_IOC_DEAD) {
 780                                 list_for_each_entry_safe(hose, tmp,
 781                                                 &hose_list, list_node) {
 782                                         phb = hose->private_data;
 783                                         phb->removed = 1;
 784                                 }
 785
 786                                 WARN(1, "EEH: dead IOC detected\n");
 787                                 ret = 4;
 788                                 goto out;
 789                         } else if (severity == OPAL_EEH_SEV_INF)
 790                                 ioda_eeh_hub_diag(hose);
 791
 792                         break;
 793                 case OPAL_EEH_PHB_ERROR:
 794                         if (severity == OPAL_EEH_SEV_PHB_DEAD) {
 795                                 if (ioda_eeh_get_phb_pe(hose, pe))
 796                                         break;
 797
 798                                 WARN(1, "EEH: dead PHB#%x detected\n",
 799                                      hose->global_number);
 800                                 phb->removed = 1;
 801                                 ret = 3;
 802                                 goto out;
 803                         } else if (severity == OPAL_EEH_SEV_PHB_FENCED) {
 804                                 if (ioda_eeh_get_phb_pe(hose, pe))
 805                                         break;
 806
 807                                 WARN(1, "EEH: fenced PHB#%x detected\n",
 808                                      hose->global_number);
 809                                 ret = 2;
 810                                 goto out;
 811                         } else if (severity == OPAL_EEH_SEV_INF)
 812                                 ioda_eeh_phb_diag(hose);
 813
 814                         break;
 815                 case OPAL_EEH_PE_ERROR:
 816                         if (ioda_eeh_get_pe(hose, frozen_pe_no, pe))
 817                                 break;
 818
 819                         WARN(1, "EEH: Frozen PE#%x on PHB#%x detected\n",
 820                              (*pe)->addr, (*pe)->phb->global_number);
 821                         ret = 1;
 822                         goto out;
 823                 }
 824         }
 825
 826         ret = 0;
 827 out:
 828         return ret;
 829 }
 830
 831 struct pnv_eeh_ops ioda_eeh_ops = {
 832         .post_init              = ioda_eeh_post_init,
 833         .set_option             = ioda_eeh_set_option,
 834         .get_state              = ioda_eeh_get_state,
 835         .reset                  = ioda_eeh_reset,
 836         .get_log                = ioda_eeh_get_log,
 837         .configure_bridge       = ioda_eeh_configure_bridge,
 838         .next_error             = ioda_eeh_next_error
 839 };