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powerpc/powernv/ioda2: Export debug helper pe_level_printk()
[deliverable/linux.git] / arch / powerpc / platforms / powernv / pci-ioda.c
1 /*
2 * Support PCI/PCIe on PowerNV platforms
3 *
4 * Copyright 2011 Benjamin Herrenschmidt, IBM Corp.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12 #undef DEBUG
13
14 #include <linux/kernel.h>
15 #include <linux/pci.h>
16 #include <linux/crash_dump.h>
17 #include <linux/debugfs.h>
18 #include <linux/delay.h>
19 #include <linux/string.h>
20 #include <linux/init.h>
21 #include <linux/bootmem.h>
22 #include <linux/irq.h>
23 #include <linux/io.h>
24 #include <linux/msi.h>
25 #include <linux/memblock.h>
26 #include <linux/iommu.h>
27 #include <linux/rculist.h>
28 #include <linux/sizes.h>
29
30 #include <asm/sections.h>
31 #include <asm/io.h>
32 #include <asm/prom.h>
33 #include <asm/pci-bridge.h>
34 #include <asm/machdep.h>
35 #include <asm/msi_bitmap.h>
36 #include <asm/ppc-pci.h>
37 #include <asm/opal.h>
38 #include <asm/iommu.h>
39 #include <asm/tce.h>
40 #include <asm/xics.h>
41 #include <asm/debug.h>
42 #include <asm/firmware.h>
43 #include <asm/pnv-pci.h>
44 #include <asm/mmzone.h>
45
46 #include <misc/cxl-base.h>
47
48 #include "powernv.h"
49 #include "pci.h"
50
51 #define PNV_IODA1_M64_NUM 16 /* Number of M64 BARs */
52 #define PNV_IODA1_M64_SEGS 8 /* Segments per M64 BAR */
53 #define PNV_IODA1_DMA32_SEGSIZE 0x10000000
54
55 #define POWERNV_IOMMU_DEFAULT_LEVELS 1
56 #define POWERNV_IOMMU_MAX_LEVELS 5
57
58 static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl);
59
60 void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level,
61 const char *fmt, ...)
62 {
63 struct va_format vaf;
64 va_list args;
65 char pfix[32];
66
67 va_start(args, fmt);
68
69 vaf.fmt = fmt;
70 vaf.va = &args;
71
72 if (pe->flags & PNV_IODA_PE_DEV)
73 strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix));
74 else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
75 sprintf(pfix, "%04x:%02x ",
76 pci_domain_nr(pe->pbus), pe->pbus->number);
77 #ifdef CONFIG_PCI_IOV
78 else if (pe->flags & PNV_IODA_PE_VF)
79 sprintf(pfix, "%04x:%02x:%2x.%d",
80 pci_domain_nr(pe->parent_dev->bus),
81 (pe->rid & 0xff00) >> 8,
82 PCI_SLOT(pe->rid), PCI_FUNC(pe->rid));
83 #endif /* CONFIG_PCI_IOV*/
84
85 printk("%spci %s: [PE# %.3d] %pV",
86 level, pfix, pe->pe_number, &vaf);
87
88 va_end(args);
89 }
90
91 static bool pnv_iommu_bypass_disabled __read_mostly;
92
93 static int __init iommu_setup(char *str)
94 {
95 if (!str)
96 return -EINVAL;
97
98 while (*str) {
99 if (!strncmp(str, "nobypass", 8)) {
100 pnv_iommu_bypass_disabled = true;
101 pr_info("PowerNV: IOMMU bypass window disabled.\n");
102 break;
103 }
104 str += strcspn(str, ",");
105 if (*str == ',')
106 str++;
107 }
108
109 return 0;
110 }
111 early_param("iommu", iommu_setup);
112
113 static inline bool pnv_pci_is_mem_pref_64(unsigned long flags)
114 {
115 return ((flags & (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH)) ==
116 (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH));
117 }
118
119 static struct pnv_ioda_pe *pnv_ioda_init_pe(struct pnv_phb *phb, int pe_no)
120 {
121 phb->ioda.pe_array[pe_no].phb = phb;
122 phb->ioda.pe_array[pe_no].pe_number = pe_no;
123
124 return &phb->ioda.pe_array[pe_no];
125 }
126
127 static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no)
128 {
129 if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe_num)) {
130 pr_warn("%s: Invalid PE %d on PHB#%x\n",
131 __func__, pe_no, phb->hose->global_number);
132 return;
133 }
134
135 if (test_and_set_bit(pe_no, phb->ioda.pe_alloc))
136 pr_debug("%s: PE %d was reserved on PHB#%x\n",
137 __func__, pe_no, phb->hose->global_number);
138
139 pnv_ioda_init_pe(phb, pe_no);
140 }
141
142 static struct pnv_ioda_pe *pnv_ioda_alloc_pe(struct pnv_phb *phb)
143 {
144 unsigned long pe;
145
146 do {
147 pe = find_next_zero_bit(phb->ioda.pe_alloc,
148 phb->ioda.total_pe_num, 0);
149 if (pe >= phb->ioda.total_pe_num)
150 return NULL;
151 } while(test_and_set_bit(pe, phb->ioda.pe_alloc));
152
153 return pnv_ioda_init_pe(phb, pe);
154 }
155
156 static void pnv_ioda_free_pe(struct pnv_ioda_pe *pe)
157 {
158 struct pnv_phb *phb = pe->phb;
159
160 WARN_ON(pe->pdev);
161
162 memset(pe, 0, sizeof(struct pnv_ioda_pe));
163 clear_bit(pe->pe_number, phb->ioda.pe_alloc);
164 }
165
166 /* The default M64 BAR is shared by all PEs */
167 static int pnv_ioda2_init_m64(struct pnv_phb *phb)
168 {
169 const char *desc;
170 struct resource *r;
171 s64 rc;
172
173 /* Configure the default M64 BAR */
174 rc = opal_pci_set_phb_mem_window(phb->opal_id,
175 OPAL_M64_WINDOW_TYPE,
176 phb->ioda.m64_bar_idx,
177 phb->ioda.m64_base,
178 0, /* unused */
179 phb->ioda.m64_size);
180 if (rc != OPAL_SUCCESS) {
181 desc = "configuring";
182 goto fail;
183 }
184
185 /* Enable the default M64 BAR */
186 rc = opal_pci_phb_mmio_enable(phb->opal_id,
187 OPAL_M64_WINDOW_TYPE,
188 phb->ioda.m64_bar_idx,
189 OPAL_ENABLE_M64_SPLIT);
190 if (rc != OPAL_SUCCESS) {
191 desc = "enabling";
192 goto fail;
193 }
194
195 /* Mark the M64 BAR assigned */
196 set_bit(phb->ioda.m64_bar_idx, &phb->ioda.m64_bar_alloc);
197
198 /*
199 * Strip off the segment used by the reserved PE, which is
200 * expected to be 0 or last one of PE capabicity.
201 */
202 r = &phb->hose->mem_resources[1];
203 if (phb->ioda.reserved_pe_idx == 0)
204 r->start += phb->ioda.m64_segsize;
205 else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1))
206 r->end -= phb->ioda.m64_segsize;
207 else
208 pr_warn(" Cannot strip M64 segment for reserved PE#%d\n",
209 phb->ioda.reserved_pe_idx);
210
211 return 0;
212
213 fail:
214 pr_warn(" Failure %lld %s M64 BAR#%d\n",
215 rc, desc, phb->ioda.m64_bar_idx);
216 opal_pci_phb_mmio_enable(phb->opal_id,
217 OPAL_M64_WINDOW_TYPE,
218 phb->ioda.m64_bar_idx,
219 OPAL_DISABLE_M64);
220 return -EIO;
221 }
222
223 static void pnv_ioda_reserve_dev_m64_pe(struct pci_dev *pdev,
224 unsigned long *pe_bitmap)
225 {
226 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
227 struct pnv_phb *phb = hose->private_data;
228 struct resource *r;
229 resource_size_t base, sgsz, start, end;
230 int segno, i;
231
232 base = phb->ioda.m64_base;
233 sgsz = phb->ioda.m64_segsize;
234 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
235 r = &pdev->resource[i];
236 if (!r->parent || !pnv_pci_is_mem_pref_64(r->flags))
237 continue;
238
239 start = _ALIGN_DOWN(r->start - base, sgsz);
240 end = _ALIGN_UP(r->end - base, sgsz);
241 for (segno = start / sgsz; segno < end / sgsz; segno++) {
242 if (pe_bitmap)
243 set_bit(segno, pe_bitmap);
244 else
245 pnv_ioda_reserve_pe(phb, segno);
246 }
247 }
248 }
249
250 static int pnv_ioda1_init_m64(struct pnv_phb *phb)
251 {
252 struct resource *r;
253 int index;
254
255 /*
256 * There are 16 M64 BARs, each of which has 8 segments. So
257 * there are as many M64 segments as the maximum number of
258 * PEs, which is 128.
259 */
260 for (index = 0; index < PNV_IODA1_M64_NUM; index++) {
261 unsigned long base, segsz = phb->ioda.m64_segsize;
262 int64_t rc;
263
264 base = phb->ioda.m64_base +
265 index * PNV_IODA1_M64_SEGS * segsz;
266 rc = opal_pci_set_phb_mem_window(phb->opal_id,
267 OPAL_M64_WINDOW_TYPE, index, base, 0,
268 PNV_IODA1_M64_SEGS * segsz);
269 if (rc != OPAL_SUCCESS) {
270 pr_warn(" Error %lld setting M64 PHB#%d-BAR#%d\n",
271 rc, phb->hose->global_number, index);
272 goto fail;
273 }
274
275 rc = opal_pci_phb_mmio_enable(phb->opal_id,
276 OPAL_M64_WINDOW_TYPE, index,
277 OPAL_ENABLE_M64_SPLIT);
278 if (rc != OPAL_SUCCESS) {
279 pr_warn(" Error %lld enabling M64 PHB#%d-BAR#%d\n",
280 rc, phb->hose->global_number, index);
281 goto fail;
282 }
283 }
284
285 /*
286 * Exclude the segment used by the reserved PE, which
287 * is expected to be 0 or last supported PE#.
288 */
289 r = &phb->hose->mem_resources[1];
290 if (phb->ioda.reserved_pe_idx == 0)
291 r->start += phb->ioda.m64_segsize;
292 else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1))
293 r->end -= phb->ioda.m64_segsize;
294 else
295 WARN(1, "Wrong reserved PE#%d on PHB#%d\n",
296 phb->ioda.reserved_pe_idx, phb->hose->global_number);
297
298 return 0;
299
300 fail:
301 for ( ; index >= 0; index--)
302 opal_pci_phb_mmio_enable(phb->opal_id,
303 OPAL_M64_WINDOW_TYPE, index, OPAL_DISABLE_M64);
304
305 return -EIO;
306 }
307
308 static void pnv_ioda_reserve_m64_pe(struct pci_bus *bus,
309 unsigned long *pe_bitmap,
310 bool all)
311 {
312 struct pci_dev *pdev;
313
314 list_for_each_entry(pdev, &bus->devices, bus_list) {
315 pnv_ioda_reserve_dev_m64_pe(pdev, pe_bitmap);
316
317 if (all && pdev->subordinate)
318 pnv_ioda_reserve_m64_pe(pdev->subordinate,
319 pe_bitmap, all);
320 }
321 }
322
323 static struct pnv_ioda_pe *pnv_ioda_pick_m64_pe(struct pci_bus *bus, bool all)
324 {
325 struct pci_controller *hose = pci_bus_to_host(bus);
326 struct pnv_phb *phb = hose->private_data;
327 struct pnv_ioda_pe *master_pe, *pe;
328 unsigned long size, *pe_alloc;
329 int i;
330
331 /* Root bus shouldn't use M64 */
332 if (pci_is_root_bus(bus))
333 return NULL;
334
335 /* Allocate bitmap */
336 size = _ALIGN_UP(phb->ioda.total_pe_num / 8, sizeof(unsigned long));
337 pe_alloc = kzalloc(size, GFP_KERNEL);
338 if (!pe_alloc) {
339 pr_warn("%s: Out of memory !\n",
340 __func__);
341 return NULL;
342 }
343
344 /* Figure out reserved PE numbers by the PE */
345 pnv_ioda_reserve_m64_pe(bus, pe_alloc, all);
346
347 /*
348 * the current bus might not own M64 window and that's all
349 * contributed by its child buses. For the case, we needn't
350 * pick M64 dependent PE#.
351 */
352 if (bitmap_empty(pe_alloc, phb->ioda.total_pe_num)) {
353 kfree(pe_alloc);
354 return NULL;
355 }
356
357 /*
358 * Figure out the master PE and put all slave PEs to master
359 * PE's list to form compound PE.
360 */
361 master_pe = NULL;
362 i = -1;
363 while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe_num, i + 1)) <
364 phb->ioda.total_pe_num) {
365 pe = &phb->ioda.pe_array[i];
366
367 phb->ioda.m64_segmap[pe->pe_number] = pe->pe_number;
368 if (!master_pe) {
369 pe->flags |= PNV_IODA_PE_MASTER;
370 INIT_LIST_HEAD(&pe->slaves);
371 master_pe = pe;
372 } else {
373 pe->flags |= PNV_IODA_PE_SLAVE;
374 pe->master = master_pe;
375 list_add_tail(&pe->list, &master_pe->slaves);
376 }
377
378 /*
379 * P7IOC supports M64DT, which helps mapping M64 segment
380 * to one particular PE#. However, PHB3 has fixed mapping
381 * between M64 segment and PE#. In order to have same logic
382 * for P7IOC and PHB3, we enforce fixed mapping between M64
383 * segment and PE# on P7IOC.
384 */
385 if (phb->type == PNV_PHB_IODA1) {
386 int64_t rc;
387
388 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
389 pe->pe_number, OPAL_M64_WINDOW_TYPE,
390 pe->pe_number / PNV_IODA1_M64_SEGS,
391 pe->pe_number % PNV_IODA1_M64_SEGS);
392 if (rc != OPAL_SUCCESS)
393 pr_warn("%s: Error %lld mapping M64 for PHB#%d-PE#%d\n",
394 __func__, rc, phb->hose->global_number,
395 pe->pe_number);
396 }
397 }
398
399 kfree(pe_alloc);
400 return master_pe;
401 }
402
403 static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb)
404 {
405 struct pci_controller *hose = phb->hose;
406 struct device_node *dn = hose->dn;
407 struct resource *res;
408 const u32 *r;
409 u64 pci_addr;
410
411 if (phb->type != PNV_PHB_IODA1 && phb->type != PNV_PHB_IODA2) {
412 pr_info(" Not support M64 window\n");
413 return;
414 }
415
416 if (!firmware_has_feature(FW_FEATURE_OPAL)) {
417 pr_info(" Firmware too old to support M64 window\n");
418 return;
419 }
420
421 r = of_get_property(dn, "ibm,opal-m64-window", NULL);
422 if (!r) {
423 pr_info(" No <ibm,opal-m64-window> on %s\n",
424 dn->full_name);
425 return;
426 }
427
428 res = &hose->mem_resources[1];
429 res->name = dn->full_name;
430 res->start = of_translate_address(dn, r + 2);
431 res->end = res->start + of_read_number(r + 4, 2) - 1;
432 res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH);
433 pci_addr = of_read_number(r, 2);
434 hose->mem_offset[1] = res->start - pci_addr;
435
436 phb->ioda.m64_size = resource_size(res);
437 phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe_num;
438 phb->ioda.m64_base = pci_addr;
439
440 pr_info(" MEM64 0x%016llx..0x%016llx -> 0x%016llx\n",
441 res->start, res->end, pci_addr);
442
443 /* Use last M64 BAR to cover M64 window */
444 phb->ioda.m64_bar_idx = 15;
445 if (phb->type == PNV_PHB_IODA1)
446 phb->init_m64 = pnv_ioda1_init_m64;
447 else
448 phb->init_m64 = pnv_ioda2_init_m64;
449 phb->reserve_m64_pe = pnv_ioda_reserve_m64_pe;
450 phb->pick_m64_pe = pnv_ioda_pick_m64_pe;
451 }
452
453 static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no)
454 {
455 struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no];
456 struct pnv_ioda_pe *slave;
457 s64 rc;
458
459 /* Fetch master PE */
460 if (pe->flags & PNV_IODA_PE_SLAVE) {
461 pe = pe->master;
462 if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)))
463 return;
464
465 pe_no = pe->pe_number;
466 }
467
468 /* Freeze master PE */
469 rc = opal_pci_eeh_freeze_set(phb->opal_id,
470 pe_no,
471 OPAL_EEH_ACTION_SET_FREEZE_ALL);
472 if (rc != OPAL_SUCCESS) {
473 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
474 __func__, rc, phb->hose->global_number, pe_no);
475 return;
476 }
477
478 /* Freeze slave PEs */
479 if (!(pe->flags & PNV_IODA_PE_MASTER))
480 return;
481
482 list_for_each_entry(slave, &pe->slaves, list) {
483 rc = opal_pci_eeh_freeze_set(phb->opal_id,
484 slave->pe_number,
485 OPAL_EEH_ACTION_SET_FREEZE_ALL);
486 if (rc != OPAL_SUCCESS)
487 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
488 __func__, rc, phb->hose->global_number,
489 slave->pe_number);
490 }
491 }
492
493 static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt)
494 {
495 struct pnv_ioda_pe *pe, *slave;
496 s64 rc;
497
498 /* Find master PE */
499 pe = &phb->ioda.pe_array[pe_no];
500 if (pe->flags & PNV_IODA_PE_SLAVE) {
501 pe = pe->master;
502 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
503 pe_no = pe->pe_number;
504 }
505
506 /* Clear frozen state for master PE */
507 rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt);
508 if (rc != OPAL_SUCCESS) {
509 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
510 __func__, rc, opt, phb->hose->global_number, pe_no);
511 return -EIO;
512 }
513
514 if (!(pe->flags & PNV_IODA_PE_MASTER))
515 return 0;
516
517 /* Clear frozen state for slave PEs */
518 list_for_each_entry(slave, &pe->slaves, list) {
519 rc = opal_pci_eeh_freeze_clear(phb->opal_id,
520 slave->pe_number,
521 opt);
522 if (rc != OPAL_SUCCESS) {
523 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
524 __func__, rc, opt, phb->hose->global_number,
525 slave->pe_number);
526 return -EIO;
527 }
528 }
529
530 return 0;
531 }
532
533 static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no)
534 {
535 struct pnv_ioda_pe *slave, *pe;
536 u8 fstate, state;
537 __be16 pcierr;
538 s64 rc;
539
540 /* Sanity check on PE number */
541 if (pe_no < 0 || pe_no >= phb->ioda.total_pe_num)
542 return OPAL_EEH_STOPPED_PERM_UNAVAIL;
543
544 /*
545 * Fetch the master PE and the PE instance might be
546 * not initialized yet.
547 */
548 pe = &phb->ioda.pe_array[pe_no];
549 if (pe->flags & PNV_IODA_PE_SLAVE) {
550 pe = pe->master;
551 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
552 pe_no = pe->pe_number;
553 }
554
555 /* Check the master PE */
556 rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no,
557 &state, &pcierr, NULL);
558 if (rc != OPAL_SUCCESS) {
559 pr_warn("%s: Failure %lld getting "
560 "PHB#%x-PE#%x state\n",
561 __func__, rc,
562 phb->hose->global_number, pe_no);
563 return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
564 }
565
566 /* Check the slave PE */
567 if (!(pe->flags & PNV_IODA_PE_MASTER))
568 return state;
569
570 list_for_each_entry(slave, &pe->slaves, list) {
571 rc = opal_pci_eeh_freeze_status(phb->opal_id,
572 slave->pe_number,
573 &fstate,
574 &pcierr,
575 NULL);
576 if (rc != OPAL_SUCCESS) {
577 pr_warn("%s: Failure %lld getting "
578 "PHB#%x-PE#%x state\n",
579 __func__, rc,
580 phb->hose->global_number, slave->pe_number);
581 return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
582 }
583
584 /*
585 * Override the result based on the ascending
586 * priority.
587 */
588 if (fstate > state)
589 state = fstate;
590 }
591
592 return state;
593 }
594
595 /* Currently those 2 are only used when MSIs are enabled, this will change
596 * but in the meantime, we need to protect them to avoid warnings
597 */
598 #ifdef CONFIG_PCI_MSI
599 static struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev)
600 {
601 struct pci_controller *hose = pci_bus_to_host(dev->bus);
602 struct pnv_phb *phb = hose->private_data;
603 struct pci_dn *pdn = pci_get_pdn(dev);
604
605 if (!pdn)
606 return NULL;
607 if (pdn->pe_number == IODA_INVALID_PE)
608 return NULL;
609 return &phb->ioda.pe_array[pdn->pe_number];
610 }
611 #endif /* CONFIG_PCI_MSI */
612
613 static int pnv_ioda_set_one_peltv(struct pnv_phb *phb,
614 struct pnv_ioda_pe *parent,
615 struct pnv_ioda_pe *child,
616 bool is_add)
617 {
618 const char *desc = is_add ? "adding" : "removing";
619 uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN :
620 OPAL_REMOVE_PE_FROM_DOMAIN;
621 struct pnv_ioda_pe *slave;
622 long rc;
623
624 /* Parent PE affects child PE */
625 rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number,
626 child->pe_number, op);
627 if (rc != OPAL_SUCCESS) {
628 pe_warn(child, "OPAL error %ld %s to parent PELTV\n",
629 rc, desc);
630 return -ENXIO;
631 }
632
633 if (!(child->flags & PNV_IODA_PE_MASTER))
634 return 0;
635
636 /* Compound case: parent PE affects slave PEs */
637 list_for_each_entry(slave, &child->slaves, list) {
638 rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number,
639 slave->pe_number, op);
640 if (rc != OPAL_SUCCESS) {
641 pe_warn(slave, "OPAL error %ld %s to parent PELTV\n",
642 rc, desc);
643 return -ENXIO;
644 }
645 }
646
647 return 0;
648 }
649
650 static int pnv_ioda_set_peltv(struct pnv_phb *phb,
651 struct pnv_ioda_pe *pe,
652 bool is_add)
653 {
654 struct pnv_ioda_pe *slave;
655 struct pci_dev *pdev = NULL;
656 int ret;
657
658 /*
659 * Clear PE frozen state. If it's master PE, we need
660 * clear slave PE frozen state as well.
661 */
662 if (is_add) {
663 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
664 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
665 if (pe->flags & PNV_IODA_PE_MASTER) {
666 list_for_each_entry(slave, &pe->slaves, list)
667 opal_pci_eeh_freeze_clear(phb->opal_id,
668 slave->pe_number,
669 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
670 }
671 }
672
673 /*
674 * Associate PE in PELT. We need add the PE into the
675 * corresponding PELT-V as well. Otherwise, the error
676 * originated from the PE might contribute to other
677 * PEs.
678 */
679 ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add);
680 if (ret)
681 return ret;
682
683 /* For compound PEs, any one affects all of them */
684 if (pe->flags & PNV_IODA_PE_MASTER) {
685 list_for_each_entry(slave, &pe->slaves, list) {
686 ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add);
687 if (ret)
688 return ret;
689 }
690 }
691
692 if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS))
693 pdev = pe->pbus->self;
694 else if (pe->flags & PNV_IODA_PE_DEV)
695 pdev = pe->pdev->bus->self;
696 #ifdef CONFIG_PCI_IOV
697 else if (pe->flags & PNV_IODA_PE_VF)
698 pdev = pe->parent_dev;
699 #endif /* CONFIG_PCI_IOV */
700 while (pdev) {
701 struct pci_dn *pdn = pci_get_pdn(pdev);
702 struct pnv_ioda_pe *parent;
703
704 if (pdn && pdn->pe_number != IODA_INVALID_PE) {
705 parent = &phb->ioda.pe_array[pdn->pe_number];
706 ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add);
707 if (ret)
708 return ret;
709 }
710
711 pdev = pdev->bus->self;
712 }
713
714 return 0;
715 }
716
717 #ifdef CONFIG_PCI_IOV
718 static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
719 {
720 struct pci_dev *parent;
721 uint8_t bcomp, dcomp, fcomp;
722 int64_t rc;
723 long rid_end, rid;
724
725 /* Currently, we just deconfigure VF PE. Bus PE will always there.*/
726 if (pe->pbus) {
727 int count;
728
729 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
730 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
731 parent = pe->pbus->self;
732 if (pe->flags & PNV_IODA_PE_BUS_ALL)
733 count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
734 else
735 count = 1;
736
737 switch(count) {
738 case 1: bcomp = OpalPciBusAll; break;
739 case 2: bcomp = OpalPciBus7Bits; break;
740 case 4: bcomp = OpalPciBus6Bits; break;
741 case 8: bcomp = OpalPciBus5Bits; break;
742 case 16: bcomp = OpalPciBus4Bits; break;
743 case 32: bcomp = OpalPciBus3Bits; break;
744 default:
745 dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
746 count);
747 /* Do an exact match only */
748 bcomp = OpalPciBusAll;
749 }
750 rid_end = pe->rid + (count << 8);
751 } else {
752 if (pe->flags & PNV_IODA_PE_VF)
753 parent = pe->parent_dev;
754 else
755 parent = pe->pdev->bus->self;
756 bcomp = OpalPciBusAll;
757 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
758 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
759 rid_end = pe->rid + 1;
760 }
761
762 /* Clear the reverse map */
763 for (rid = pe->rid; rid < rid_end; rid++)
764 phb->ioda.pe_rmap[rid] = 0;
765
766 /* Release from all parents PELT-V */
767 while (parent) {
768 struct pci_dn *pdn = pci_get_pdn(parent);
769 if (pdn && pdn->pe_number != IODA_INVALID_PE) {
770 rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number,
771 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN);
772 /* XXX What to do in case of error ? */
773 }
774 parent = parent->bus->self;
775 }
776
777 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
778 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
779
780 /* Disassociate PE in PELT */
781 rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number,
782 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN);
783 if (rc)
784 pe_warn(pe, "OPAL error %ld remove self from PELTV\n", rc);
785 rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
786 bcomp, dcomp, fcomp, OPAL_UNMAP_PE);
787 if (rc)
788 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
789
790 pe->pbus = NULL;
791 pe->pdev = NULL;
792 pe->parent_dev = NULL;
793
794 return 0;
795 }
796 #endif /* CONFIG_PCI_IOV */
797
798 static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
799 {
800 struct pci_dev *parent;
801 uint8_t bcomp, dcomp, fcomp;
802 long rc, rid_end, rid;
803
804 /* Bus validation ? */
805 if (pe->pbus) {
806 int count;
807
808 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
809 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
810 parent = pe->pbus->self;
811 if (pe->flags & PNV_IODA_PE_BUS_ALL)
812 count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
813 else
814 count = 1;
815
816 switch(count) {
817 case 1: bcomp = OpalPciBusAll; break;
818 case 2: bcomp = OpalPciBus7Bits; break;
819 case 4: bcomp = OpalPciBus6Bits; break;
820 case 8: bcomp = OpalPciBus5Bits; break;
821 case 16: bcomp = OpalPciBus4Bits; break;
822 case 32: bcomp = OpalPciBus3Bits; break;
823 default:
824 dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
825 count);
826 /* Do an exact match only */
827 bcomp = OpalPciBusAll;
828 }
829 rid_end = pe->rid + (count << 8);
830 } else {
831 #ifdef CONFIG_PCI_IOV
832 if (pe->flags & PNV_IODA_PE_VF)
833 parent = pe->parent_dev;
834 else
835 #endif /* CONFIG_PCI_IOV */
836 parent = pe->pdev->bus->self;
837 bcomp = OpalPciBusAll;
838 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
839 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
840 rid_end = pe->rid + 1;
841 }
842
843 /*
844 * Associate PE in PELT. We need add the PE into the
845 * corresponding PELT-V as well. Otherwise, the error
846 * originated from the PE might contribute to other
847 * PEs.
848 */
849 rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
850 bcomp, dcomp, fcomp, OPAL_MAP_PE);
851 if (rc) {
852 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
853 return -ENXIO;
854 }
855
856 /*
857 * Configure PELTV. NPUs don't have a PELTV table so skip
858 * configuration on them.
859 */
860 if (phb->type != PNV_PHB_NPU)
861 pnv_ioda_set_peltv(phb, pe, true);
862
863 /* Setup reverse map */
864 for (rid = pe->rid; rid < rid_end; rid++)
865 phb->ioda.pe_rmap[rid] = pe->pe_number;
866
867 /* Setup one MVTs on IODA1 */
868 if (phb->type != PNV_PHB_IODA1) {
869 pe->mve_number = 0;
870 goto out;
871 }
872
873 pe->mve_number = pe->pe_number;
874 rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number);
875 if (rc != OPAL_SUCCESS) {
876 pe_err(pe, "OPAL error %ld setting up MVE %d\n",
877 rc, pe->mve_number);
878 pe->mve_number = -1;
879 } else {
880 rc = opal_pci_set_mve_enable(phb->opal_id,
881 pe->mve_number, OPAL_ENABLE_MVE);
882 if (rc) {
883 pe_err(pe, "OPAL error %ld enabling MVE %d\n",
884 rc, pe->mve_number);
885 pe->mve_number = -1;
886 }
887 }
888
889 out:
890 return 0;
891 }
892
893 #ifdef CONFIG_PCI_IOV
894 static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset)
895 {
896 struct pci_dn *pdn = pci_get_pdn(dev);
897 int i;
898 struct resource *res, res2;
899 resource_size_t size;
900 u16 num_vfs;
901
902 if (!dev->is_physfn)
903 return -EINVAL;
904
905 /*
906 * "offset" is in VFs. The M64 windows are sized so that when they
907 * are segmented, each segment is the same size as the IOV BAR.
908 * Each segment is in a separate PE, and the high order bits of the
909 * address are the PE number. Therefore, each VF's BAR is in a
910 * separate PE, and changing the IOV BAR start address changes the
911 * range of PEs the VFs are in.
912 */
913 num_vfs = pdn->num_vfs;
914 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
915 res = &dev->resource[i + PCI_IOV_RESOURCES];
916 if (!res->flags || !res->parent)
917 continue;
918
919 /*
920 * The actual IOV BAR range is determined by the start address
921 * and the actual size for num_vfs VFs BAR. This check is to
922 * make sure that after shifting, the range will not overlap
923 * with another device.
924 */
925 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
926 res2.flags = res->flags;
927 res2.start = res->start + (size * offset);
928 res2.end = res2.start + (size * num_vfs) - 1;
929
930 if (res2.end > res->end) {
931 dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n",
932 i, &res2, res, num_vfs, offset);
933 return -EBUSY;
934 }
935 }
936
937 /*
938 * After doing so, there would be a "hole" in the /proc/iomem when
939 * offset is a positive value. It looks like the device return some
940 * mmio back to the system, which actually no one could use it.
941 */
942 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
943 res = &dev->resource[i + PCI_IOV_RESOURCES];
944 if (!res->flags || !res->parent)
945 continue;
946
947 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
948 res2 = *res;
949 res->start += size * offset;
950
951 dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (%sabling %d VFs shifted by %d)\n",
952 i, &res2, res, (offset > 0) ? "En" : "Dis",
953 num_vfs, offset);
954 pci_update_resource(dev, i + PCI_IOV_RESOURCES);
955 }
956 return 0;
957 }
958 #endif /* CONFIG_PCI_IOV */
959
960 static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev)
961 {
962 struct pci_controller *hose = pci_bus_to_host(dev->bus);
963 struct pnv_phb *phb = hose->private_data;
964 struct pci_dn *pdn = pci_get_pdn(dev);
965 struct pnv_ioda_pe *pe;
966
967 if (!pdn) {
968 pr_err("%s: Device tree node not associated properly\n",
969 pci_name(dev));
970 return NULL;
971 }
972 if (pdn->pe_number != IODA_INVALID_PE)
973 return NULL;
974
975 pe = pnv_ioda_alloc_pe(phb);
976 if (!pe) {
977 pr_warning("%s: Not enough PE# available, disabling device\n",
978 pci_name(dev));
979 return NULL;
980 }
981
982 /* NOTE: We get only one ref to the pci_dev for the pdn, not for the
983 * pointer in the PE data structure, both should be destroyed at the
984 * same time. However, this needs to be looked at more closely again
985 * once we actually start removing things (Hotplug, SR-IOV, ...)
986 *
987 * At some point we want to remove the PDN completely anyways
988 */
989 pci_dev_get(dev);
990 pdn->pcidev = dev;
991 pdn->pe_number = pe->pe_number;
992 pe->flags = PNV_IODA_PE_DEV;
993 pe->pdev = dev;
994 pe->pbus = NULL;
995 pe->mve_number = -1;
996 pe->rid = dev->bus->number << 8 | pdn->devfn;
997
998 pe_info(pe, "Associated device to PE\n");
999
1000 if (pnv_ioda_configure_pe(phb, pe)) {
1001 /* XXX What do we do here ? */
1002 pnv_ioda_free_pe(pe);
1003 pdn->pe_number = IODA_INVALID_PE;
1004 pe->pdev = NULL;
1005 pci_dev_put(dev);
1006 return NULL;
1007 }
1008
1009 return pe;
1010 }
1011
1012 static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe)
1013 {
1014 struct pci_dev *dev;
1015
1016 list_for_each_entry(dev, &bus->devices, bus_list) {
1017 struct pci_dn *pdn = pci_get_pdn(dev);
1018
1019 if (pdn == NULL) {
1020 pr_warn("%s: No device node associated with device !\n",
1021 pci_name(dev));
1022 continue;
1023 }
1024 pdn->pcidev = dev;
1025 pdn->pe_number = pe->pe_number;
1026 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
1027 pnv_ioda_setup_same_PE(dev->subordinate, pe);
1028 }
1029 }
1030
1031 /*
1032 * There're 2 types of PCI bus sensitive PEs: One that is compromised of
1033 * single PCI bus. Another one that contains the primary PCI bus and its
1034 * subordinate PCI devices and buses. The second type of PE is normally
1035 * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports.
1036 */
1037 static struct pnv_ioda_pe *pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all)
1038 {
1039 struct pci_controller *hose = pci_bus_to_host(bus);
1040 struct pnv_phb *phb = hose->private_data;
1041 struct pnv_ioda_pe *pe = NULL;
1042
1043 /* Check if PE is determined by M64 */
1044 if (phb->pick_m64_pe)
1045 pe = phb->pick_m64_pe(bus, all);
1046
1047 /* The PE number isn't pinned by M64 */
1048 if (!pe)
1049 pe = pnv_ioda_alloc_pe(phb);
1050
1051 if (!pe) {
1052 pr_warning("%s: Not enough PE# available for PCI bus %04x:%02x\n",
1053 __func__, pci_domain_nr(bus), bus->number);
1054 return NULL;
1055 }
1056
1057 pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS);
1058 pe->pbus = bus;
1059 pe->pdev = NULL;
1060 pe->mve_number = -1;
1061 pe->rid = bus->busn_res.start << 8;
1062
1063 if (all)
1064 pe_info(pe, "Secondary bus %d..%d associated with PE#%d\n",
1065 bus->busn_res.start, bus->busn_res.end, pe->pe_number);
1066 else
1067 pe_info(pe, "Secondary bus %d associated with PE#%d\n",
1068 bus->busn_res.start, pe->pe_number);
1069
1070 if (pnv_ioda_configure_pe(phb, pe)) {
1071 /* XXX What do we do here ? */
1072 pnv_ioda_free_pe(pe);
1073 pe->pbus = NULL;
1074 return NULL;
1075 }
1076
1077 /* Associate it with all child devices */
1078 pnv_ioda_setup_same_PE(bus, pe);
1079
1080 /* Put PE to the list */
1081 list_add_tail(&pe->list, &phb->ioda.pe_list);
1082
1083 return pe;
1084 }
1085
1086 static struct pnv_ioda_pe *pnv_ioda_setup_npu_PE(struct pci_dev *npu_pdev)
1087 {
1088 int pe_num, found_pe = false, rc;
1089 long rid;
1090 struct pnv_ioda_pe *pe;
1091 struct pci_dev *gpu_pdev;
1092 struct pci_dn *npu_pdn;
1093 struct pci_controller *hose = pci_bus_to_host(npu_pdev->bus);
1094 struct pnv_phb *phb = hose->private_data;
1095
1096 /*
1097 * Due to a hardware errata PE#0 on the NPU is reserved for
1098 * error handling. This means we only have three PEs remaining
1099 * which need to be assigned to four links, implying some
1100 * links must share PEs.
1101 *
1102 * To achieve this we assign PEs such that NPUs linking the
1103 * same GPU get assigned the same PE.
1104 */
1105 gpu_pdev = pnv_pci_get_gpu_dev(npu_pdev);
1106 for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) {
1107 pe = &phb->ioda.pe_array[pe_num];
1108 if (!pe->pdev)
1109 continue;
1110
1111 if (pnv_pci_get_gpu_dev(pe->pdev) == gpu_pdev) {
1112 /*
1113 * This device has the same peer GPU so should
1114 * be assigned the same PE as the existing
1115 * peer NPU.
1116 */
1117 dev_info(&npu_pdev->dev,
1118 "Associating to existing PE %d\n", pe_num);
1119 pci_dev_get(npu_pdev);
1120 npu_pdn = pci_get_pdn(npu_pdev);
1121 rid = npu_pdev->bus->number << 8 | npu_pdn->devfn;
1122 npu_pdn->pcidev = npu_pdev;
1123 npu_pdn->pe_number = pe_num;
1124 phb->ioda.pe_rmap[rid] = pe->pe_number;
1125
1126 /* Map the PE to this link */
1127 rc = opal_pci_set_pe(phb->opal_id, pe_num, rid,
1128 OpalPciBusAll,
1129 OPAL_COMPARE_RID_DEVICE_NUMBER,
1130 OPAL_COMPARE_RID_FUNCTION_NUMBER,
1131 OPAL_MAP_PE);
1132 WARN_ON(rc != OPAL_SUCCESS);
1133 found_pe = true;
1134 break;
1135 }
1136 }
1137
1138 if (!found_pe)
1139 /*
1140 * Could not find an existing PE so allocate a new
1141 * one.
1142 */
1143 return pnv_ioda_setup_dev_PE(npu_pdev);
1144 else
1145 return pe;
1146 }
1147
1148 static void pnv_ioda_setup_npu_PEs(struct pci_bus *bus)
1149 {
1150 struct pci_dev *pdev;
1151
1152 list_for_each_entry(pdev, &bus->devices, bus_list)
1153 pnv_ioda_setup_npu_PE(pdev);
1154 }
1155
1156 static void pnv_ioda_setup_PEs(struct pci_bus *bus)
1157 {
1158 struct pci_dev *dev;
1159
1160 pnv_ioda_setup_bus_PE(bus, false);
1161
1162 list_for_each_entry(dev, &bus->devices, bus_list) {
1163 if (dev->subordinate) {
1164 if (pci_pcie_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE)
1165 pnv_ioda_setup_bus_PE(dev->subordinate, true);
1166 else
1167 pnv_ioda_setup_PEs(dev->subordinate);
1168 }
1169 }
1170 }
1171
1172 /*
1173 * Configure PEs so that the downstream PCI buses and devices
1174 * could have their associated PE#. Unfortunately, we didn't
1175 * figure out the way to identify the PLX bridge yet. So we
1176 * simply put the PCI bus and the subordinate behind the root
1177 * port to PE# here. The game rule here is expected to be changed
1178 * as soon as we can detected PLX bridge correctly.
1179 */
1180 static void pnv_pci_ioda_setup_PEs(void)
1181 {
1182 struct pci_controller *hose, *tmp;
1183 struct pnv_phb *phb;
1184
1185 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1186 phb = hose->private_data;
1187
1188 /* M64 layout might affect PE allocation */
1189 if (phb->reserve_m64_pe)
1190 phb->reserve_m64_pe(hose->bus, NULL, true);
1191
1192 /*
1193 * On NPU PHB, we expect separate PEs for individual PCI
1194 * functions. PCI bus dependent PEs are required for the
1195 * remaining types of PHBs.
1196 */
1197 if (phb->type == PNV_PHB_NPU) {
1198 /* PE#0 is needed for error reporting */
1199 pnv_ioda_reserve_pe(phb, 0);
1200 pnv_ioda_setup_npu_PEs(hose->bus);
1201 } else
1202 pnv_ioda_setup_PEs(hose->bus);
1203 }
1204 }
1205
1206 #ifdef CONFIG_PCI_IOV
1207 static int pnv_pci_vf_release_m64(struct pci_dev *pdev, u16 num_vfs)
1208 {
1209 struct pci_bus *bus;
1210 struct pci_controller *hose;
1211 struct pnv_phb *phb;
1212 struct pci_dn *pdn;
1213 int i, j;
1214 int m64_bars;
1215
1216 bus = pdev->bus;
1217 hose = pci_bus_to_host(bus);
1218 phb = hose->private_data;
1219 pdn = pci_get_pdn(pdev);
1220
1221 if (pdn->m64_single_mode)
1222 m64_bars = num_vfs;
1223 else
1224 m64_bars = 1;
1225
1226 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++)
1227 for (j = 0; j < m64_bars; j++) {
1228 if (pdn->m64_map[j][i] == IODA_INVALID_M64)
1229 continue;
1230 opal_pci_phb_mmio_enable(phb->opal_id,
1231 OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 0);
1232 clear_bit(pdn->m64_map[j][i], &phb->ioda.m64_bar_alloc);
1233 pdn->m64_map[j][i] = IODA_INVALID_M64;
1234 }
1235
1236 kfree(pdn->m64_map);
1237 return 0;
1238 }
1239
1240 static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs)
1241 {
1242 struct pci_bus *bus;
1243 struct pci_controller *hose;
1244 struct pnv_phb *phb;
1245 struct pci_dn *pdn;
1246 unsigned int win;
1247 struct resource *res;
1248 int i, j;
1249 int64_t rc;
1250 int total_vfs;
1251 resource_size_t size, start;
1252 int pe_num;
1253 int m64_bars;
1254
1255 bus = pdev->bus;
1256 hose = pci_bus_to_host(bus);
1257 phb = hose->private_data;
1258 pdn = pci_get_pdn(pdev);
1259 total_vfs = pci_sriov_get_totalvfs(pdev);
1260
1261 if (pdn->m64_single_mode)
1262 m64_bars = num_vfs;
1263 else
1264 m64_bars = 1;
1265
1266 pdn->m64_map = kmalloc(sizeof(*pdn->m64_map) * m64_bars, GFP_KERNEL);
1267 if (!pdn->m64_map)
1268 return -ENOMEM;
1269 /* Initialize the m64_map to IODA_INVALID_M64 */
1270 for (i = 0; i < m64_bars ; i++)
1271 for (j = 0; j < PCI_SRIOV_NUM_BARS; j++)
1272 pdn->m64_map[i][j] = IODA_INVALID_M64;
1273
1274
1275 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
1276 res = &pdev->resource[i + PCI_IOV_RESOURCES];
1277 if (!res->flags || !res->parent)
1278 continue;
1279
1280 for (j = 0; j < m64_bars; j++) {
1281 do {
1282 win = find_next_zero_bit(&phb->ioda.m64_bar_alloc,
1283 phb->ioda.m64_bar_idx + 1, 0);
1284
1285 if (win >= phb->ioda.m64_bar_idx + 1)
1286 goto m64_failed;
1287 } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc));
1288
1289 pdn->m64_map[j][i] = win;
1290
1291 if (pdn->m64_single_mode) {
1292 size = pci_iov_resource_size(pdev,
1293 PCI_IOV_RESOURCES + i);
1294 start = res->start + size * j;
1295 } else {
1296 size = resource_size(res);
1297 start = res->start;
1298 }
1299
1300 /* Map the M64 here */
1301 if (pdn->m64_single_mode) {
1302 pe_num = pdn->pe_num_map[j];
1303 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
1304 pe_num, OPAL_M64_WINDOW_TYPE,
1305 pdn->m64_map[j][i], 0);
1306 }
1307
1308 rc = opal_pci_set_phb_mem_window(phb->opal_id,
1309 OPAL_M64_WINDOW_TYPE,
1310 pdn->m64_map[j][i],
1311 start,
1312 0, /* unused */
1313 size);
1314
1315
1316 if (rc != OPAL_SUCCESS) {
1317 dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n",
1318 win, rc);
1319 goto m64_failed;
1320 }
1321
1322 if (pdn->m64_single_mode)
1323 rc = opal_pci_phb_mmio_enable(phb->opal_id,
1324 OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 2);
1325 else
1326 rc = opal_pci_phb_mmio_enable(phb->opal_id,
1327 OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 1);
1328
1329 if (rc != OPAL_SUCCESS) {
1330 dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n",
1331 win, rc);
1332 goto m64_failed;
1333 }
1334 }
1335 }
1336 return 0;
1337
1338 m64_failed:
1339 pnv_pci_vf_release_m64(pdev, num_vfs);
1340 return -EBUSY;
1341 }
1342
1343 static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group,
1344 int num);
1345 static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable);
1346
1347 static void pnv_pci_ioda2_release_dma_pe(struct pci_dev *dev, struct pnv_ioda_pe *pe)
1348 {
1349 struct iommu_table *tbl;
1350 int64_t rc;
1351
1352 tbl = pe->table_group.tables[0];
1353 rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0);
1354 if (rc)
1355 pe_warn(pe, "OPAL error %ld release DMA window\n", rc);
1356
1357 pnv_pci_ioda2_set_bypass(pe, false);
1358 if (pe->table_group.group) {
1359 iommu_group_put(pe->table_group.group);
1360 BUG_ON(pe->table_group.group);
1361 }
1362 pnv_pci_ioda2_table_free_pages(tbl);
1363 iommu_free_table(tbl, of_node_full_name(dev->dev.of_node));
1364 }
1365
1366 static void pnv_ioda_release_vf_PE(struct pci_dev *pdev)
1367 {
1368 struct pci_bus *bus;
1369 struct pci_controller *hose;
1370 struct pnv_phb *phb;
1371 struct pnv_ioda_pe *pe, *pe_n;
1372 struct pci_dn *pdn;
1373
1374 bus = pdev->bus;
1375 hose = pci_bus_to_host(bus);
1376 phb = hose->private_data;
1377 pdn = pci_get_pdn(pdev);
1378
1379 if (!pdev->is_physfn)
1380 return;
1381
1382 list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) {
1383 if (pe->parent_dev != pdev)
1384 continue;
1385
1386 pnv_pci_ioda2_release_dma_pe(pdev, pe);
1387
1388 /* Remove from list */
1389 mutex_lock(&phb->ioda.pe_list_mutex);
1390 list_del(&pe->list);
1391 mutex_unlock(&phb->ioda.pe_list_mutex);
1392
1393 pnv_ioda_deconfigure_pe(phb, pe);
1394
1395 pnv_ioda_free_pe(pe);
1396 }
1397 }
1398
1399 void pnv_pci_sriov_disable(struct pci_dev *pdev)
1400 {
1401 struct pci_bus *bus;
1402 struct pci_controller *hose;
1403 struct pnv_phb *phb;
1404 struct pnv_ioda_pe *pe;
1405 struct pci_dn *pdn;
1406 struct pci_sriov *iov;
1407 u16 num_vfs, i;
1408
1409 bus = pdev->bus;
1410 hose = pci_bus_to_host(bus);
1411 phb = hose->private_data;
1412 pdn = pci_get_pdn(pdev);
1413 iov = pdev->sriov;
1414 num_vfs = pdn->num_vfs;
1415
1416 /* Release VF PEs */
1417 pnv_ioda_release_vf_PE(pdev);
1418
1419 if (phb->type == PNV_PHB_IODA2) {
1420 if (!pdn->m64_single_mode)
1421 pnv_pci_vf_resource_shift(pdev, -*pdn->pe_num_map);
1422
1423 /* Release M64 windows */
1424 pnv_pci_vf_release_m64(pdev, num_vfs);
1425
1426 /* Release PE numbers */
1427 if (pdn->m64_single_mode) {
1428 for (i = 0; i < num_vfs; i++) {
1429 if (pdn->pe_num_map[i] == IODA_INVALID_PE)
1430 continue;
1431
1432 pe = &phb->ioda.pe_array[pdn->pe_num_map[i]];
1433 pnv_ioda_free_pe(pe);
1434 }
1435 } else
1436 bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1437 /* Releasing pe_num_map */
1438 kfree(pdn->pe_num_map);
1439 }
1440 }
1441
1442 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
1443 struct pnv_ioda_pe *pe);
1444 static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs)
1445 {
1446 struct pci_bus *bus;
1447 struct pci_controller *hose;
1448 struct pnv_phb *phb;
1449 struct pnv_ioda_pe *pe;
1450 int pe_num;
1451 u16 vf_index;
1452 struct pci_dn *pdn;
1453
1454 bus = pdev->bus;
1455 hose = pci_bus_to_host(bus);
1456 phb = hose->private_data;
1457 pdn = pci_get_pdn(pdev);
1458
1459 if (!pdev->is_physfn)
1460 return;
1461
1462 /* Reserve PE for each VF */
1463 for (vf_index = 0; vf_index < num_vfs; vf_index++) {
1464 if (pdn->m64_single_mode)
1465 pe_num = pdn->pe_num_map[vf_index];
1466 else
1467 pe_num = *pdn->pe_num_map + vf_index;
1468
1469 pe = &phb->ioda.pe_array[pe_num];
1470 pe->pe_number = pe_num;
1471 pe->phb = phb;
1472 pe->flags = PNV_IODA_PE_VF;
1473 pe->pbus = NULL;
1474 pe->parent_dev = pdev;
1475 pe->mve_number = -1;
1476 pe->rid = (pci_iov_virtfn_bus(pdev, vf_index) << 8) |
1477 pci_iov_virtfn_devfn(pdev, vf_index);
1478
1479 pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%d\n",
1480 hose->global_number, pdev->bus->number,
1481 PCI_SLOT(pci_iov_virtfn_devfn(pdev, vf_index)),
1482 PCI_FUNC(pci_iov_virtfn_devfn(pdev, vf_index)), pe_num);
1483
1484 if (pnv_ioda_configure_pe(phb, pe)) {
1485 /* XXX What do we do here ? */
1486 pnv_ioda_free_pe(pe);
1487 pe->pdev = NULL;
1488 continue;
1489 }
1490
1491 /* Put PE to the list */
1492 mutex_lock(&phb->ioda.pe_list_mutex);
1493 list_add_tail(&pe->list, &phb->ioda.pe_list);
1494 mutex_unlock(&phb->ioda.pe_list_mutex);
1495
1496 pnv_pci_ioda2_setup_dma_pe(phb, pe);
1497 }
1498 }
1499
1500 int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
1501 {
1502 struct pci_bus *bus;
1503 struct pci_controller *hose;
1504 struct pnv_phb *phb;
1505 struct pnv_ioda_pe *pe;
1506 struct pci_dn *pdn;
1507 int ret;
1508 u16 i;
1509
1510 bus = pdev->bus;
1511 hose = pci_bus_to_host(bus);
1512 phb = hose->private_data;
1513 pdn = pci_get_pdn(pdev);
1514
1515 if (phb->type == PNV_PHB_IODA2) {
1516 if (!pdn->vfs_expanded) {
1517 dev_info(&pdev->dev, "don't support this SRIOV device"
1518 " with non 64bit-prefetchable IOV BAR\n");
1519 return -ENOSPC;
1520 }
1521
1522 /*
1523 * When M64 BARs functions in Single PE mode, the number of VFs
1524 * could be enabled must be less than the number of M64 BARs.
1525 */
1526 if (pdn->m64_single_mode && num_vfs > phb->ioda.m64_bar_idx) {
1527 dev_info(&pdev->dev, "Not enough M64 BAR for VFs\n");
1528 return -EBUSY;
1529 }
1530
1531 /* Allocating pe_num_map */
1532 if (pdn->m64_single_mode)
1533 pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map) * num_vfs,
1534 GFP_KERNEL);
1535 else
1536 pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map), GFP_KERNEL);
1537
1538 if (!pdn->pe_num_map)
1539 return -ENOMEM;
1540
1541 if (pdn->m64_single_mode)
1542 for (i = 0; i < num_vfs; i++)
1543 pdn->pe_num_map[i] = IODA_INVALID_PE;
1544
1545 /* Calculate available PE for required VFs */
1546 if (pdn->m64_single_mode) {
1547 for (i = 0; i < num_vfs; i++) {
1548 pe = pnv_ioda_alloc_pe(phb);
1549 if (!pe) {
1550 ret = -EBUSY;
1551 goto m64_failed;
1552 }
1553
1554 pdn->pe_num_map[i] = pe->pe_number;
1555 }
1556 } else {
1557 mutex_lock(&phb->ioda.pe_alloc_mutex);
1558 *pdn->pe_num_map = bitmap_find_next_zero_area(
1559 phb->ioda.pe_alloc, phb->ioda.total_pe_num,
1560 0, num_vfs, 0);
1561 if (*pdn->pe_num_map >= phb->ioda.total_pe_num) {
1562 mutex_unlock(&phb->ioda.pe_alloc_mutex);
1563 dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs);
1564 kfree(pdn->pe_num_map);
1565 return -EBUSY;
1566 }
1567 bitmap_set(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1568 mutex_unlock(&phb->ioda.pe_alloc_mutex);
1569 }
1570 pdn->num_vfs = num_vfs;
1571
1572 /* Assign M64 window accordingly */
1573 ret = pnv_pci_vf_assign_m64(pdev, num_vfs);
1574 if (ret) {
1575 dev_info(&pdev->dev, "Not enough M64 window resources\n");
1576 goto m64_failed;
1577 }
1578
1579 /*
1580 * When using one M64 BAR to map one IOV BAR, we need to shift
1581 * the IOV BAR according to the PE# allocated to the VFs.
1582 * Otherwise, the PE# for the VF will conflict with others.
1583 */
1584 if (!pdn->m64_single_mode) {
1585 ret = pnv_pci_vf_resource_shift(pdev, *pdn->pe_num_map);
1586 if (ret)
1587 goto m64_failed;
1588 }
1589 }
1590
1591 /* Setup VF PEs */
1592 pnv_ioda_setup_vf_PE(pdev, num_vfs);
1593
1594 return 0;
1595
1596 m64_failed:
1597 if (pdn->m64_single_mode) {
1598 for (i = 0; i < num_vfs; i++) {
1599 if (pdn->pe_num_map[i] == IODA_INVALID_PE)
1600 continue;
1601
1602 pe = &phb->ioda.pe_array[pdn->pe_num_map[i]];
1603 pnv_ioda_free_pe(pe);
1604 }
1605 } else
1606 bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1607
1608 /* Releasing pe_num_map */
1609 kfree(pdn->pe_num_map);
1610
1611 return ret;
1612 }
1613
1614 int pcibios_sriov_disable(struct pci_dev *pdev)
1615 {
1616 pnv_pci_sriov_disable(pdev);
1617
1618 /* Release PCI data */
1619 remove_dev_pci_data(pdev);
1620 return 0;
1621 }
1622
1623 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
1624 {
1625 /* Allocate PCI data */
1626 add_dev_pci_data(pdev);
1627
1628 return pnv_pci_sriov_enable(pdev, num_vfs);
1629 }
1630 #endif /* CONFIG_PCI_IOV */
1631
1632 static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev)
1633 {
1634 struct pci_dn *pdn = pci_get_pdn(pdev);
1635 struct pnv_ioda_pe *pe;
1636
1637 /*
1638 * The function can be called while the PE#
1639 * hasn't been assigned. Do nothing for the
1640 * case.
1641 */
1642 if (!pdn || pdn->pe_number == IODA_INVALID_PE)
1643 return;
1644
1645 pe = &phb->ioda.pe_array[pdn->pe_number];
1646 WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops);
1647 set_dma_offset(&pdev->dev, pe->tce_bypass_base);
1648 set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]);
1649 /*
1650 * Note: iommu_add_device() will fail here as
1651 * for physical PE: the device is already added by now;
1652 * for virtual PE: sysfs entries are not ready yet and
1653 * tce_iommu_bus_notifier will add the device to a group later.
1654 */
1655 }
1656
1657 static int pnv_pci_ioda_dma_set_mask(struct pci_dev *pdev, u64 dma_mask)
1658 {
1659 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
1660 struct pnv_phb *phb = hose->private_data;
1661 struct pci_dn *pdn = pci_get_pdn(pdev);
1662 struct pnv_ioda_pe *pe;
1663 uint64_t top;
1664 bool bypass = false;
1665
1666 if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
1667 return -ENODEV;;
1668
1669 pe = &phb->ioda.pe_array[pdn->pe_number];
1670 if (pe->tce_bypass_enabled) {
1671 top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1;
1672 bypass = (dma_mask >= top);
1673 }
1674
1675 if (bypass) {
1676 dev_info(&pdev->dev, "Using 64-bit DMA iommu bypass\n");
1677 set_dma_ops(&pdev->dev, &dma_direct_ops);
1678 } else {
1679 dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n");
1680 set_dma_ops(&pdev->dev, &dma_iommu_ops);
1681 }
1682 *pdev->dev.dma_mask = dma_mask;
1683
1684 /* Update peer npu devices */
1685 pnv_npu_try_dma_set_bypass(pdev, bypass);
1686
1687 return 0;
1688 }
1689
1690 static u64 pnv_pci_ioda_dma_get_required_mask(struct pci_dev *pdev)
1691 {
1692 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
1693 struct pnv_phb *phb = hose->private_data;
1694 struct pci_dn *pdn = pci_get_pdn(pdev);
1695 struct pnv_ioda_pe *pe;
1696 u64 end, mask;
1697
1698 if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
1699 return 0;
1700
1701 pe = &phb->ioda.pe_array[pdn->pe_number];
1702 if (!pe->tce_bypass_enabled)
1703 return __dma_get_required_mask(&pdev->dev);
1704
1705
1706 end = pe->tce_bypass_base + memblock_end_of_DRAM();
1707 mask = 1ULL << (fls64(end) - 1);
1708 mask += mask - 1;
1709
1710 return mask;
1711 }
1712
1713 static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe,
1714 struct pci_bus *bus)
1715 {
1716 struct pci_dev *dev;
1717
1718 list_for_each_entry(dev, &bus->devices, bus_list) {
1719 set_iommu_table_base(&dev->dev, pe->table_group.tables[0]);
1720 set_dma_offset(&dev->dev, pe->tce_bypass_base);
1721 iommu_add_device(&dev->dev);
1722
1723 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
1724 pnv_ioda_setup_bus_dma(pe, dev->subordinate);
1725 }
1726 }
1727
1728 static void pnv_pci_ioda1_tce_invalidate(struct iommu_table *tbl,
1729 unsigned long index, unsigned long npages, bool rm)
1730 {
1731 struct iommu_table_group_link *tgl = list_first_entry_or_null(
1732 &tbl->it_group_list, struct iommu_table_group_link,
1733 next);
1734 struct pnv_ioda_pe *pe = container_of(tgl->table_group,
1735 struct pnv_ioda_pe, table_group);
1736 __be64 __iomem *invalidate = rm ?
1737 (__be64 __iomem *)pe->phb->ioda.tce_inval_reg_phys :
1738 pe->phb->ioda.tce_inval_reg;
1739 unsigned long start, end, inc;
1740 const unsigned shift = tbl->it_page_shift;
1741
1742 start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset);
1743 end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset +
1744 npages - 1);
1745
1746 /* BML uses this case for p6/p7/galaxy2: Shift addr and put in node */
1747 if (tbl->it_busno) {
1748 start <<= shift;
1749 end <<= shift;
1750 inc = 128ull << shift;
1751 start |= tbl->it_busno;
1752 end |= tbl->it_busno;
1753 } else if (tbl->it_type & TCE_PCI_SWINV_PAIR) {
1754 /* p7ioc-style invalidation, 2 TCEs per write */
1755 start |= (1ull << 63);
1756 end |= (1ull << 63);
1757 inc = 16;
1758 } else {
1759 /* Default (older HW) */
1760 inc = 128;
1761 }
1762
1763 end |= inc - 1; /* round up end to be different than start */
1764
1765 mb(); /* Ensure above stores are visible */
1766 while (start <= end) {
1767 if (rm)
1768 __raw_rm_writeq(cpu_to_be64(start), invalidate);
1769 else
1770 __raw_writeq(cpu_to_be64(start), invalidate);
1771 start += inc;
1772 }
1773
1774 /*
1775 * The iommu layer will do another mb() for us on build()
1776 * and we don't care on free()
1777 */
1778 }
1779
1780 static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index,
1781 long npages, unsigned long uaddr,
1782 enum dma_data_direction direction,
1783 struct dma_attrs *attrs)
1784 {
1785 int ret = pnv_tce_build(tbl, index, npages, uaddr, direction,
1786 attrs);
1787
1788 if (!ret && (tbl->it_type & TCE_PCI_SWINV_CREATE))
1789 pnv_pci_ioda1_tce_invalidate(tbl, index, npages, false);
1790
1791 return ret;
1792 }
1793
1794 #ifdef CONFIG_IOMMU_API
1795 static int pnv_ioda1_tce_xchg(struct iommu_table *tbl, long index,
1796 unsigned long *hpa, enum dma_data_direction *direction)
1797 {
1798 long ret = pnv_tce_xchg(tbl, index, hpa, direction);
1799
1800 if (!ret && (tbl->it_type &
1801 (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE)))
1802 pnv_pci_ioda1_tce_invalidate(tbl, index, 1, false);
1803
1804 return ret;
1805 }
1806 #endif
1807
1808 static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index,
1809 long npages)
1810 {
1811 pnv_tce_free(tbl, index, npages);
1812
1813 if (tbl->it_type & TCE_PCI_SWINV_FREE)
1814 pnv_pci_ioda1_tce_invalidate(tbl, index, npages, false);
1815 }
1816
1817 static struct iommu_table_ops pnv_ioda1_iommu_ops = {
1818 .set = pnv_ioda1_tce_build,
1819 #ifdef CONFIG_IOMMU_API
1820 .exchange = pnv_ioda1_tce_xchg,
1821 #endif
1822 .clear = pnv_ioda1_tce_free,
1823 .get = pnv_tce_get,
1824 };
1825
1826 #define TCE_KILL_INVAL_ALL PPC_BIT(0)
1827 #define TCE_KILL_INVAL_PE PPC_BIT(1)
1828 #define TCE_KILL_INVAL_TCE PPC_BIT(2)
1829
1830 void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm)
1831 {
1832 const unsigned long val = TCE_KILL_INVAL_ALL;
1833
1834 mb(); /* Ensure previous TCE table stores are visible */
1835 if (rm)
1836 __raw_rm_writeq(cpu_to_be64(val),
1837 (__be64 __iomem *)
1838 phb->ioda.tce_inval_reg_phys);
1839 else
1840 __raw_writeq(cpu_to_be64(val), phb->ioda.tce_inval_reg);
1841 }
1842
1843 static inline void pnv_pci_ioda2_tce_invalidate_pe(struct pnv_ioda_pe *pe)
1844 {
1845 /* 01xb - invalidate TCEs that match the specified PE# */
1846 unsigned long val = TCE_KILL_INVAL_PE | (pe->pe_number & 0xFF);
1847 struct pnv_phb *phb = pe->phb;
1848 struct pnv_ioda_pe *npe;
1849 int i;
1850
1851 if (!phb->ioda.tce_inval_reg)
1852 return;
1853
1854 mb(); /* Ensure above stores are visible */
1855 __raw_writeq(cpu_to_be64(val), phb->ioda.tce_inval_reg);
1856
1857 if (pe->flags & PNV_IODA_PE_PEER)
1858 for (i = 0; i < PNV_IODA_MAX_PEER_PES; i++) {
1859 npe = pe->peers[i];
1860 if (!npe || npe->phb->type != PNV_PHB_NPU)
1861 continue;
1862
1863 pnv_pci_ioda2_tce_invalidate_entire(npe->phb, false);
1864 }
1865 }
1866
1867 static void pnv_pci_ioda2_do_tce_invalidate(unsigned pe_number, bool rm,
1868 __be64 __iomem *invalidate, unsigned shift,
1869 unsigned long index, unsigned long npages)
1870 {
1871 unsigned long start, end, inc;
1872
1873 /* We'll invalidate DMA address in PE scope */
1874 start = TCE_KILL_INVAL_TCE;
1875 start |= (pe_number & 0xFF);
1876 end = start;
1877
1878 /* Figure out the start, end and step */
1879 start |= (index << shift);
1880 end |= ((index + npages - 1) << shift);
1881 inc = (0x1ull << shift);
1882 mb();
1883
1884 while (start <= end) {
1885 if (rm)
1886 __raw_rm_writeq(cpu_to_be64(start), invalidate);
1887 else
1888 __raw_writeq(cpu_to_be64(start), invalidate);
1889 start += inc;
1890 }
1891 }
1892
1893 static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl,
1894 unsigned long index, unsigned long npages, bool rm)
1895 {
1896 struct iommu_table_group_link *tgl;
1897
1898 list_for_each_entry_rcu(tgl, &tbl->it_group_list, next) {
1899 struct pnv_ioda_pe *npe;
1900 struct pnv_ioda_pe *pe = container_of(tgl->table_group,
1901 struct pnv_ioda_pe, table_group);
1902 __be64 __iomem *invalidate = rm ?
1903 (__be64 __iomem *)pe->phb->ioda.tce_inval_reg_phys :
1904 pe->phb->ioda.tce_inval_reg;
1905 int i;
1906
1907 pnv_pci_ioda2_do_tce_invalidate(pe->pe_number, rm,
1908 invalidate, tbl->it_page_shift,
1909 index, npages);
1910
1911 if (pe->flags & PNV_IODA_PE_PEER)
1912 /*
1913 * The NVLink hardware does not support TCE kill
1914 * per TCE entry so we have to invalidate
1915 * the entire cache for it.
1916 */
1917 for (i = 0; i < PNV_IODA_MAX_PEER_PES; i++) {
1918 npe = pe->peers[i];
1919 if (!npe || npe->phb->type != PNV_PHB_NPU ||
1920 !npe->phb->ioda.tce_inval_reg)
1921 continue;
1922
1923 pnv_pci_ioda2_tce_invalidate_entire(npe->phb,
1924 rm);
1925 }
1926 }
1927 }
1928
1929 static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index,
1930 long npages, unsigned long uaddr,
1931 enum dma_data_direction direction,
1932 struct dma_attrs *attrs)
1933 {
1934 int ret = pnv_tce_build(tbl, index, npages, uaddr, direction,
1935 attrs);
1936
1937 if (!ret && (tbl->it_type & TCE_PCI_SWINV_CREATE))
1938 pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false);
1939
1940 return ret;
1941 }
1942
1943 #ifdef CONFIG_IOMMU_API
1944 static int pnv_ioda2_tce_xchg(struct iommu_table *tbl, long index,
1945 unsigned long *hpa, enum dma_data_direction *direction)
1946 {
1947 long ret = pnv_tce_xchg(tbl, index, hpa, direction);
1948
1949 if (!ret && (tbl->it_type &
1950 (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE)))
1951 pnv_pci_ioda2_tce_invalidate(tbl, index, 1, false);
1952
1953 return ret;
1954 }
1955 #endif
1956
1957 static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index,
1958 long npages)
1959 {
1960 pnv_tce_free(tbl, index, npages);
1961
1962 if (tbl->it_type & TCE_PCI_SWINV_FREE)
1963 pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false);
1964 }
1965
1966 static void pnv_ioda2_table_free(struct iommu_table *tbl)
1967 {
1968 pnv_pci_ioda2_table_free_pages(tbl);
1969 iommu_free_table(tbl, "pnv");
1970 }
1971
1972 static struct iommu_table_ops pnv_ioda2_iommu_ops = {
1973 .set = pnv_ioda2_tce_build,
1974 #ifdef CONFIG_IOMMU_API
1975 .exchange = pnv_ioda2_tce_xchg,
1976 #endif
1977 .clear = pnv_ioda2_tce_free,
1978 .get = pnv_tce_get,
1979 .free = pnv_ioda2_table_free,
1980 };
1981
1982 static int pnv_pci_ioda_dev_dma_weight(struct pci_dev *dev, void *data)
1983 {
1984 unsigned int *weight = (unsigned int *)data;
1985
1986 /* This is quite simplistic. The "base" weight of a device
1987 * is 10. 0 means no DMA is to be accounted for it.
1988 */
1989 if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL)
1990 return 0;
1991
1992 if (dev->class == PCI_CLASS_SERIAL_USB_UHCI ||
1993 dev->class == PCI_CLASS_SERIAL_USB_OHCI ||
1994 dev->class == PCI_CLASS_SERIAL_USB_EHCI)
1995 *weight += 3;
1996 else if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID)
1997 *weight += 15;
1998 else
1999 *weight += 10;
2000
2001 return 0;
2002 }
2003
2004 static unsigned int pnv_pci_ioda_pe_dma_weight(struct pnv_ioda_pe *pe)
2005 {
2006 unsigned int weight = 0;
2007
2008 /* SRIOV VF has same DMA32 weight as its PF */
2009 #ifdef CONFIG_PCI_IOV
2010 if ((pe->flags & PNV_IODA_PE_VF) && pe->parent_dev) {
2011 pnv_pci_ioda_dev_dma_weight(pe->parent_dev, &weight);
2012 return weight;
2013 }
2014 #endif
2015
2016 if ((pe->flags & PNV_IODA_PE_DEV) && pe->pdev) {
2017 pnv_pci_ioda_dev_dma_weight(pe->pdev, &weight);
2018 } else if ((pe->flags & PNV_IODA_PE_BUS) && pe->pbus) {
2019 struct pci_dev *pdev;
2020
2021 list_for_each_entry(pdev, &pe->pbus->devices, bus_list)
2022 pnv_pci_ioda_dev_dma_weight(pdev, &weight);
2023 } else if ((pe->flags & PNV_IODA_PE_BUS_ALL) && pe->pbus) {
2024 pci_walk_bus(pe->pbus, pnv_pci_ioda_dev_dma_weight, &weight);
2025 }
2026
2027 return weight;
2028 }
2029
2030 static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb,
2031 struct pnv_ioda_pe *pe)
2032 {
2033
2034 struct page *tce_mem = NULL;
2035 struct iommu_table *tbl;
2036 unsigned int weight, total_weight = 0;
2037 unsigned int tce32_segsz, base, segs, avail, i;
2038 int64_t rc;
2039 void *addr;
2040
2041 /* XXX FIXME: Handle 64-bit only DMA devices */
2042 /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */
2043 /* XXX FIXME: Allocate multi-level tables on PHB3 */
2044 weight = pnv_pci_ioda_pe_dma_weight(pe);
2045 if (!weight)
2046 return;
2047
2048 pci_walk_bus(phb->hose->bus, pnv_pci_ioda_dev_dma_weight,
2049 &total_weight);
2050 segs = (weight * phb->ioda.dma32_count) / total_weight;
2051 if (!segs)
2052 segs = 1;
2053
2054 /*
2055 * Allocate contiguous DMA32 segments. We begin with the expected
2056 * number of segments. With one more attempt, the number of DMA32
2057 * segments to be allocated is decreased by one until one segment
2058 * is allocated successfully.
2059 */
2060 do {
2061 for (base = 0; base <= phb->ioda.dma32_count - segs; base++) {
2062 for (avail = 0, i = base; i < base + segs; i++) {
2063 if (phb->ioda.dma32_segmap[i] ==
2064 IODA_INVALID_PE)
2065 avail++;
2066 }
2067
2068 if (avail == segs)
2069 goto found;
2070 }
2071 } while (--segs);
2072
2073 if (!segs) {
2074 pe_warn(pe, "No available DMA32 segments\n");
2075 return;
2076 }
2077
2078 found:
2079 tbl = pnv_pci_table_alloc(phb->hose->node);
2080 iommu_register_group(&pe->table_group, phb->hose->global_number,
2081 pe->pe_number);
2082 pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group);
2083
2084 /* Grab a 32-bit TCE table */
2085 pe_info(pe, "DMA weight %d (%d), assigned (%d) %d DMA32 segments\n",
2086 weight, total_weight, base, segs);
2087 pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n",
2088 base * PNV_IODA1_DMA32_SEGSIZE,
2089 (base + segs) * PNV_IODA1_DMA32_SEGSIZE - 1);
2090
2091 /* XXX Currently, we allocate one big contiguous table for the
2092 * TCEs. We only really need one chunk per 256M of TCE space
2093 * (ie per segment) but that's an optimization for later, it
2094 * requires some added smarts with our get/put_tce implementation
2095 *
2096 * Each TCE page is 4KB in size and each TCE entry occupies 8
2097 * bytes
2098 */
2099 tce32_segsz = PNV_IODA1_DMA32_SEGSIZE >> (IOMMU_PAGE_SHIFT_4K - 3);
2100 tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL,
2101 get_order(tce32_segsz * segs));
2102 if (!tce_mem) {
2103 pe_err(pe, " Failed to allocate a 32-bit TCE memory\n");
2104 goto fail;
2105 }
2106 addr = page_address(tce_mem);
2107 memset(addr, 0, tce32_segsz * segs);
2108
2109 /* Configure HW */
2110 for (i = 0; i < segs; i++) {
2111 rc = opal_pci_map_pe_dma_window(phb->opal_id,
2112 pe->pe_number,
2113 base + i, 1,
2114 __pa(addr) + tce32_segsz * i,
2115 tce32_segsz, IOMMU_PAGE_SIZE_4K);
2116 if (rc) {
2117 pe_err(pe, " Failed to configure 32-bit TCE table,"
2118 " err %ld\n", rc);
2119 goto fail;
2120 }
2121 }
2122
2123 /* Setup DMA32 segment mapping */
2124 for (i = base; i < base + segs; i++)
2125 phb->ioda.dma32_segmap[i] = pe->pe_number;
2126
2127 /* Setup linux iommu table */
2128 pnv_pci_setup_iommu_table(tbl, addr, tce32_segsz * segs,
2129 base * PNV_IODA1_DMA32_SEGSIZE,
2130 IOMMU_PAGE_SHIFT_4K);
2131
2132 /* OPAL variant of P7IOC SW invalidated TCEs */
2133 if (phb->ioda.tce_inval_reg)
2134 tbl->it_type |= (TCE_PCI_SWINV_CREATE |
2135 TCE_PCI_SWINV_FREE |
2136 TCE_PCI_SWINV_PAIR);
2137
2138 tbl->it_ops = &pnv_ioda1_iommu_ops;
2139 pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift;
2140 pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift;
2141 iommu_init_table(tbl, phb->hose->node);
2142
2143 if (pe->flags & PNV_IODA_PE_DEV) {
2144 /*
2145 * Setting table base here only for carrying iommu_group
2146 * further down to let iommu_add_device() do the job.
2147 * pnv_pci_ioda_dma_dev_setup will override it later anyway.
2148 */
2149 set_iommu_table_base(&pe->pdev->dev, tbl);
2150 iommu_add_device(&pe->pdev->dev);
2151 } else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
2152 pnv_ioda_setup_bus_dma(pe, pe->pbus);
2153
2154 return;
2155 fail:
2156 /* XXX Failure: Try to fallback to 64-bit only ? */
2157 if (tce_mem)
2158 __free_pages(tce_mem, get_order(tce32_segsz * segs));
2159 if (tbl) {
2160 pnv_pci_unlink_table_and_group(tbl, &pe->table_group);
2161 iommu_free_table(tbl, "pnv");
2162 }
2163 }
2164
2165 static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group,
2166 int num, struct iommu_table *tbl)
2167 {
2168 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2169 table_group);
2170 struct pnv_phb *phb = pe->phb;
2171 int64_t rc;
2172 const unsigned long size = tbl->it_indirect_levels ?
2173 tbl->it_level_size : tbl->it_size;
2174 const __u64 start_addr = tbl->it_offset << tbl->it_page_shift;
2175 const __u64 win_size = tbl->it_size << tbl->it_page_shift;
2176
2177 pe_info(pe, "Setting up window#%d %llx..%llx pg=%x\n", num,
2178 start_addr, start_addr + win_size - 1,
2179 IOMMU_PAGE_SIZE(tbl));
2180
2181 /*
2182 * Map TCE table through TVT. The TVE index is the PE number
2183 * shifted by 1 bit for 32-bits DMA space.
2184 */
2185 rc = opal_pci_map_pe_dma_window(phb->opal_id,
2186 pe->pe_number,
2187 (pe->pe_number << 1) + num,
2188 tbl->it_indirect_levels + 1,
2189 __pa(tbl->it_base),
2190 size << 3,
2191 IOMMU_PAGE_SIZE(tbl));
2192 if (rc) {
2193 pe_err(pe, "Failed to configure TCE table, err %ld\n", rc);
2194 return rc;
2195 }
2196
2197 pnv_pci_link_table_and_group(phb->hose->node, num,
2198 tbl, &pe->table_group);
2199 pnv_pci_ioda2_tce_invalidate_pe(pe);
2200
2201 return 0;
2202 }
2203
2204 static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable)
2205 {
2206 uint16_t window_id = (pe->pe_number << 1 ) + 1;
2207 int64_t rc;
2208
2209 pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis");
2210 if (enable) {
2211 phys_addr_t top = memblock_end_of_DRAM();
2212
2213 top = roundup_pow_of_two(top);
2214 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
2215 pe->pe_number,
2216 window_id,
2217 pe->tce_bypass_base,
2218 top);
2219 } else {
2220 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
2221 pe->pe_number,
2222 window_id,
2223 pe->tce_bypass_base,
2224 0);
2225 }
2226 if (rc)
2227 pe_err(pe, "OPAL error %lld configuring bypass window\n", rc);
2228 else
2229 pe->tce_bypass_enabled = enable;
2230 }
2231
2232 static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset,
2233 __u32 page_shift, __u64 window_size, __u32 levels,
2234 struct iommu_table *tbl);
2235
2236 static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group,
2237 int num, __u32 page_shift, __u64 window_size, __u32 levels,
2238 struct iommu_table **ptbl)
2239 {
2240 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2241 table_group);
2242 int nid = pe->phb->hose->node;
2243 __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start;
2244 long ret;
2245 struct iommu_table *tbl;
2246
2247 tbl = pnv_pci_table_alloc(nid);
2248 if (!tbl)
2249 return -ENOMEM;
2250
2251 ret = pnv_pci_ioda2_table_alloc_pages(nid,
2252 bus_offset, page_shift, window_size,
2253 levels, tbl);
2254 if (ret) {
2255 iommu_free_table(tbl, "pnv");
2256 return ret;
2257 }
2258
2259 tbl->it_ops = &pnv_ioda2_iommu_ops;
2260 if (pe->phb->ioda.tce_inval_reg)
2261 tbl->it_type |= (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE);
2262
2263 *ptbl = tbl;
2264
2265 return 0;
2266 }
2267
2268 static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe)
2269 {
2270 struct iommu_table *tbl = NULL;
2271 long rc;
2272
2273 /*
2274 * crashkernel= specifies the kdump kernel's maximum memory at
2275 * some offset and there is no guaranteed the result is a power
2276 * of 2, which will cause errors later.
2277 */
2278 const u64 max_memory = __rounddown_pow_of_two(memory_hotplug_max());
2279
2280 /*
2281 * In memory constrained environments, e.g. kdump kernel, the
2282 * DMA window can be larger than available memory, which will
2283 * cause errors later.
2284 */
2285 const u64 window_size = min((u64)pe->table_group.tce32_size, max_memory);
2286
2287 rc = pnv_pci_ioda2_create_table(&pe->table_group, 0,
2288 IOMMU_PAGE_SHIFT_4K,
2289 window_size,
2290 POWERNV_IOMMU_DEFAULT_LEVELS, &tbl);
2291 if (rc) {
2292 pe_err(pe, "Failed to create 32-bit TCE table, err %ld",
2293 rc);
2294 return rc;
2295 }
2296
2297 iommu_init_table(tbl, pe->phb->hose->node);
2298
2299 rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl);
2300 if (rc) {
2301 pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n",
2302 rc);
2303 pnv_ioda2_table_free(tbl);
2304 return rc;
2305 }
2306
2307 if (!pnv_iommu_bypass_disabled)
2308 pnv_pci_ioda2_set_bypass(pe, true);
2309
2310 /* OPAL variant of PHB3 invalidated TCEs */
2311 if (pe->phb->ioda.tce_inval_reg)
2312 tbl->it_type |= (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE);
2313
2314 /*
2315 * Setting table base here only for carrying iommu_group
2316 * further down to let iommu_add_device() do the job.
2317 * pnv_pci_ioda_dma_dev_setup will override it later anyway.
2318 */
2319 if (pe->flags & PNV_IODA_PE_DEV)
2320 set_iommu_table_base(&pe->pdev->dev, tbl);
2321
2322 return 0;
2323 }
2324
2325 #if defined(CONFIG_IOMMU_API) || defined(CONFIG_PCI_IOV)
2326 static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group,
2327 int num)
2328 {
2329 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2330 table_group);
2331 struct pnv_phb *phb = pe->phb;
2332 long ret;
2333
2334 pe_info(pe, "Removing DMA window #%d\n", num);
2335
2336 ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
2337 (pe->pe_number << 1) + num,
2338 0/* levels */, 0/* table address */,
2339 0/* table size */, 0/* page size */);
2340 if (ret)
2341 pe_warn(pe, "Unmapping failed, ret = %ld\n", ret);
2342 else
2343 pnv_pci_ioda2_tce_invalidate_pe(pe);
2344
2345 pnv_pci_unlink_table_and_group(table_group->tables[num], table_group);
2346
2347 return ret;
2348 }
2349 #endif
2350
2351 #ifdef CONFIG_IOMMU_API
2352 static unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift,
2353 __u64 window_size, __u32 levels)
2354 {
2355 unsigned long bytes = 0;
2356 const unsigned window_shift = ilog2(window_size);
2357 unsigned entries_shift = window_shift - page_shift;
2358 unsigned table_shift = entries_shift + 3;
2359 unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift);
2360 unsigned long direct_table_size;
2361
2362 if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) ||
2363 (window_size > memory_hotplug_max()) ||
2364 !is_power_of_2(window_size))
2365 return 0;
2366
2367 /* Calculate a direct table size from window_size and levels */
2368 entries_shift = (entries_shift + levels - 1) / levels;
2369 table_shift = entries_shift + 3;
2370 table_shift = max_t(unsigned, table_shift, PAGE_SHIFT);
2371 direct_table_size = 1UL << table_shift;
2372
2373 for ( ; levels; --levels) {
2374 bytes += _ALIGN_UP(tce_table_size, direct_table_size);
2375
2376 tce_table_size /= direct_table_size;
2377 tce_table_size <<= 3;
2378 tce_table_size = _ALIGN_UP(tce_table_size, direct_table_size);
2379 }
2380
2381 return bytes;
2382 }
2383
2384 static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group)
2385 {
2386 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2387 table_group);
2388 /* Store @tbl as pnv_pci_ioda2_unset_window() resets it */
2389 struct iommu_table *tbl = pe->table_group.tables[0];
2390
2391 pnv_pci_ioda2_set_bypass(pe, false);
2392 pnv_pci_ioda2_unset_window(&pe->table_group, 0);
2393 pnv_ioda2_table_free(tbl);
2394 }
2395
2396 static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group)
2397 {
2398 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2399 table_group);
2400
2401 pnv_pci_ioda2_setup_default_config(pe);
2402 }
2403
2404 static struct iommu_table_group_ops pnv_pci_ioda2_ops = {
2405 .get_table_size = pnv_pci_ioda2_get_table_size,
2406 .create_table = pnv_pci_ioda2_create_table,
2407 .set_window = pnv_pci_ioda2_set_window,
2408 .unset_window = pnv_pci_ioda2_unset_window,
2409 .take_ownership = pnv_ioda2_take_ownership,
2410 .release_ownership = pnv_ioda2_release_ownership,
2411 };
2412 #endif
2413
2414 static void pnv_pci_ioda_setup_opal_tce_kill(struct pnv_phb *phb)
2415 {
2416 const __be64 *swinvp;
2417
2418 /* OPAL variant of PHB3 invalidated TCEs */
2419 swinvp = of_get_property(phb->hose->dn, "ibm,opal-tce-kill", NULL);
2420 if (!swinvp)
2421 return;
2422
2423 phb->ioda.tce_inval_reg_phys = be64_to_cpup(swinvp);
2424 phb->ioda.tce_inval_reg = ioremap(phb->ioda.tce_inval_reg_phys, 8);
2425 }
2426
2427 static __be64 *pnv_pci_ioda2_table_do_alloc_pages(int nid, unsigned shift,
2428 unsigned levels, unsigned long limit,
2429 unsigned long *current_offset, unsigned long *total_allocated)
2430 {
2431 struct page *tce_mem = NULL;
2432 __be64 *addr, *tmp;
2433 unsigned order = max_t(unsigned, shift, PAGE_SHIFT) - PAGE_SHIFT;
2434 unsigned long allocated = 1UL << (order + PAGE_SHIFT);
2435 unsigned entries = 1UL << (shift - 3);
2436 long i;
2437
2438 tce_mem = alloc_pages_node(nid, GFP_KERNEL, order);
2439 if (!tce_mem) {
2440 pr_err("Failed to allocate a TCE memory, order=%d\n", order);
2441 return NULL;
2442 }
2443 addr = page_address(tce_mem);
2444 memset(addr, 0, allocated);
2445 *total_allocated += allocated;
2446
2447 --levels;
2448 if (!levels) {
2449 *current_offset += allocated;
2450 return addr;
2451 }
2452
2453 for (i = 0; i < entries; ++i) {
2454 tmp = pnv_pci_ioda2_table_do_alloc_pages(nid, shift,
2455 levels, limit, current_offset, total_allocated);
2456 if (!tmp)
2457 break;
2458
2459 addr[i] = cpu_to_be64(__pa(tmp) |
2460 TCE_PCI_READ | TCE_PCI_WRITE);
2461
2462 if (*current_offset >= limit)
2463 break;
2464 }
2465
2466 return addr;
2467 }
2468
2469 static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr,
2470 unsigned long size, unsigned level);
2471
2472 static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset,
2473 __u32 page_shift, __u64 window_size, __u32 levels,
2474 struct iommu_table *tbl)
2475 {
2476 void *addr;
2477 unsigned long offset = 0, level_shift, total_allocated = 0;
2478 const unsigned window_shift = ilog2(window_size);
2479 unsigned entries_shift = window_shift - page_shift;
2480 unsigned table_shift = max_t(unsigned, entries_shift + 3, PAGE_SHIFT);
2481 const unsigned long tce_table_size = 1UL << table_shift;
2482
2483 if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS))
2484 return -EINVAL;
2485
2486 if ((window_size > memory_hotplug_max()) || !is_power_of_2(window_size))
2487 return -EINVAL;
2488
2489 /* Adjust direct table size from window_size and levels */
2490 entries_shift = (entries_shift + levels - 1) / levels;
2491 level_shift = entries_shift + 3;
2492 level_shift = max_t(unsigned, level_shift, PAGE_SHIFT);
2493
2494 /* Allocate TCE table */
2495 addr = pnv_pci_ioda2_table_do_alloc_pages(nid, level_shift,
2496 levels, tce_table_size, &offset, &total_allocated);
2497
2498 /* addr==NULL means that the first level allocation failed */
2499 if (!addr)
2500 return -ENOMEM;
2501
2502 /*
2503 * First level was allocated but some lower level failed as
2504 * we did not allocate as much as we wanted,
2505 * release partially allocated table.
2506 */
2507 if (offset < tce_table_size) {
2508 pnv_pci_ioda2_table_do_free_pages(addr,
2509 1ULL << (level_shift - 3), levels - 1);
2510 return -ENOMEM;
2511 }
2512
2513 /* Setup linux iommu table */
2514 pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, bus_offset,
2515 page_shift);
2516 tbl->it_level_size = 1ULL << (level_shift - 3);
2517 tbl->it_indirect_levels = levels - 1;
2518 tbl->it_allocated_size = total_allocated;
2519
2520 pr_devel("Created TCE table: ws=%08llx ts=%lx @%08llx\n",
2521 window_size, tce_table_size, bus_offset);
2522
2523 return 0;
2524 }
2525
2526 static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr,
2527 unsigned long size, unsigned level)
2528 {
2529 const unsigned long addr_ul = (unsigned long) addr &
2530 ~(TCE_PCI_READ | TCE_PCI_WRITE);
2531
2532 if (level) {
2533 long i;
2534 u64 *tmp = (u64 *) addr_ul;
2535
2536 for (i = 0; i < size; ++i) {
2537 unsigned long hpa = be64_to_cpu(tmp[i]);
2538
2539 if (!(hpa & (TCE_PCI_READ | TCE_PCI_WRITE)))
2540 continue;
2541
2542 pnv_pci_ioda2_table_do_free_pages(__va(hpa), size,
2543 level - 1);
2544 }
2545 }
2546
2547 free_pages(addr_ul, get_order(size << 3));
2548 }
2549
2550 static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl)
2551 {
2552 const unsigned long size = tbl->it_indirect_levels ?
2553 tbl->it_level_size : tbl->it_size;
2554
2555 if (!tbl->it_size)
2556 return;
2557
2558 pnv_pci_ioda2_table_do_free_pages((__be64 *)tbl->it_base, size,
2559 tbl->it_indirect_levels);
2560 }
2561
2562 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
2563 struct pnv_ioda_pe *pe)
2564 {
2565 int64_t rc;
2566
2567 /* TVE #1 is selected by PCI address bit 59 */
2568 pe->tce_bypass_base = 1ull << 59;
2569
2570 iommu_register_group(&pe->table_group, phb->hose->global_number,
2571 pe->pe_number);
2572
2573 /* The PE will reserve all possible 32-bits space */
2574 pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n",
2575 phb->ioda.m32_pci_base);
2576
2577 /* Setup linux iommu table */
2578 pe->table_group.tce32_start = 0;
2579 pe->table_group.tce32_size = phb->ioda.m32_pci_base;
2580 pe->table_group.max_dynamic_windows_supported =
2581 IOMMU_TABLE_GROUP_MAX_TABLES;
2582 pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS;
2583 pe->table_group.pgsizes = SZ_4K | SZ_64K | SZ_16M;
2584 #ifdef CONFIG_IOMMU_API
2585 pe->table_group.ops = &pnv_pci_ioda2_ops;
2586 #endif
2587
2588 rc = pnv_pci_ioda2_setup_default_config(pe);
2589 if (rc)
2590 return;
2591
2592 if (pe->flags & PNV_IODA_PE_DEV)
2593 iommu_add_device(&pe->pdev->dev);
2594 else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
2595 pnv_ioda_setup_bus_dma(pe, pe->pbus);
2596 }
2597
2598 static void pnv_ioda_setup_dma(struct pnv_phb *phb)
2599 {
2600 struct pci_controller *hose = phb->hose;
2601 struct pnv_ioda_pe *pe;
2602 unsigned int weight;
2603
2604 /* If we have more PE# than segments available, hand out one
2605 * per PE until we run out and let the rest fail. If not,
2606 * then we assign at least one segment per PE, plus more based
2607 * on the amount of devices under that PE
2608 */
2609 pr_info("PCI: Domain %04x has %d available 32-bit DMA segments\n",
2610 hose->global_number, phb->ioda.dma32_count);
2611
2612 pnv_pci_ioda_setup_opal_tce_kill(phb);
2613
2614 /* Walk our PE list and configure their DMA segments */
2615 list_for_each_entry(pe, &phb->ioda.pe_list, list) {
2616 weight = pnv_pci_ioda_pe_dma_weight(pe);
2617 if (!weight)
2618 continue;
2619
2620 /*
2621 * For IODA2 compliant PHB3, we needn't care about the weight.
2622 * The all available 32-bits DMA space will be assigned to
2623 * the specific PE.
2624 */
2625 if (phb->type == PNV_PHB_IODA1) {
2626 pnv_pci_ioda1_setup_dma_pe(phb, pe);
2627 } else if (phb->type == PNV_PHB_IODA2) {
2628 pe_info(pe, "Assign DMA32 space\n");
2629 pnv_pci_ioda2_setup_dma_pe(phb, pe);
2630 } else if (phb->type == PNV_PHB_NPU) {
2631 /*
2632 * We initialise the DMA space for an NPU PHB
2633 * after setup of the PHB is complete as we
2634 * point the NPU TVT to the the same location
2635 * as the PHB3 TVT.
2636 */
2637 }
2638 }
2639 }
2640
2641 #ifdef CONFIG_PCI_MSI
2642 static void pnv_ioda2_msi_eoi(struct irq_data *d)
2643 {
2644 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
2645 struct irq_chip *chip = irq_data_get_irq_chip(d);
2646 struct pnv_phb *phb = container_of(chip, struct pnv_phb,
2647 ioda.irq_chip);
2648 int64_t rc;
2649
2650 rc = opal_pci_msi_eoi(phb->opal_id, hw_irq);
2651 WARN_ON_ONCE(rc);
2652
2653 icp_native_eoi(d);
2654 }
2655
2656
2657 static void set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq)
2658 {
2659 struct irq_data *idata;
2660 struct irq_chip *ichip;
2661
2662 if (phb->type != PNV_PHB_IODA2)
2663 return;
2664
2665 if (!phb->ioda.irq_chip_init) {
2666 /*
2667 * First time we setup an MSI IRQ, we need to setup the
2668 * corresponding IRQ chip to route correctly.
2669 */
2670 idata = irq_get_irq_data(virq);
2671 ichip = irq_data_get_irq_chip(idata);
2672 phb->ioda.irq_chip_init = 1;
2673 phb->ioda.irq_chip = *ichip;
2674 phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi;
2675 }
2676 irq_set_chip(virq, &phb->ioda.irq_chip);
2677 }
2678
2679 #ifdef CONFIG_CXL_BASE
2680
2681 struct device_node *pnv_pci_get_phb_node(struct pci_dev *dev)
2682 {
2683 struct pci_controller *hose = pci_bus_to_host(dev->bus);
2684
2685 return of_node_get(hose->dn);
2686 }
2687 EXPORT_SYMBOL(pnv_pci_get_phb_node);
2688
2689 int pnv_phb_to_cxl_mode(struct pci_dev *dev, uint64_t mode)
2690 {
2691 struct pci_controller *hose = pci_bus_to_host(dev->bus);
2692 struct pnv_phb *phb = hose->private_data;
2693 struct pnv_ioda_pe *pe;
2694 int rc;
2695
2696 pe = pnv_ioda_get_pe(dev);
2697 if (!pe)
2698 return -ENODEV;
2699
2700 pe_info(pe, "Switching PHB to CXL\n");
2701
2702 rc = opal_pci_set_phb_cxl_mode(phb->opal_id, mode, pe->pe_number);
2703 if (rc)
2704 dev_err(&dev->dev, "opal_pci_set_phb_cxl_mode failed: %i\n", rc);
2705
2706 return rc;
2707 }
2708 EXPORT_SYMBOL(pnv_phb_to_cxl_mode);
2709
2710 /* Find PHB for cxl dev and allocate MSI hwirqs?
2711 * Returns the absolute hardware IRQ number
2712 */
2713 int pnv_cxl_alloc_hwirqs(struct pci_dev *dev, int num)
2714 {
2715 struct pci_controller *hose = pci_bus_to_host(dev->bus);
2716 struct pnv_phb *phb = hose->private_data;
2717 int hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, num);
2718
2719 if (hwirq < 0) {
2720 dev_warn(&dev->dev, "Failed to find a free MSI\n");
2721 return -ENOSPC;
2722 }
2723
2724 return phb->msi_base + hwirq;
2725 }
2726 EXPORT_SYMBOL(pnv_cxl_alloc_hwirqs);
2727
2728 void pnv_cxl_release_hwirqs(struct pci_dev *dev, int hwirq, int num)
2729 {
2730 struct pci_controller *hose = pci_bus_to_host(dev->bus);
2731 struct pnv_phb *phb = hose->private_data;
2732
2733 msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq - phb->msi_base, num);
2734 }
2735 EXPORT_SYMBOL(pnv_cxl_release_hwirqs);
2736
2737 void pnv_cxl_release_hwirq_ranges(struct cxl_irq_ranges *irqs,
2738 struct pci_dev *dev)
2739 {
2740 struct pci_controller *hose = pci_bus_to_host(dev->bus);
2741 struct pnv_phb *phb = hose->private_data;
2742 int i, hwirq;
2743
2744 for (i = 1; i < CXL_IRQ_RANGES; i++) {
2745 if (!irqs->range[i])
2746 continue;
2747 pr_devel("cxl release irq range 0x%x: offset: 0x%lx limit: %ld\n",
2748 i, irqs->offset[i],
2749 irqs->range[i]);
2750 hwirq = irqs->offset[i] - phb->msi_base;
2751 msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq,
2752 irqs->range[i]);
2753 }
2754 }
2755 EXPORT_SYMBOL(pnv_cxl_release_hwirq_ranges);
2756
2757 int pnv_cxl_alloc_hwirq_ranges(struct cxl_irq_ranges *irqs,
2758 struct pci_dev *dev, int num)
2759 {
2760 struct pci_controller *hose = pci_bus_to_host(dev->bus);
2761 struct pnv_phb *phb = hose->private_data;
2762 int i, hwirq, try;
2763
2764 memset(irqs, 0, sizeof(struct cxl_irq_ranges));
2765
2766 /* 0 is reserved for the multiplexed PSL DSI interrupt */
2767 for (i = 1; i < CXL_IRQ_RANGES && num; i++) {
2768 try = num;
2769 while (try) {
2770 hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, try);
2771 if (hwirq >= 0)
2772 break;
2773 try /= 2;
2774 }
2775 if (!try)
2776 goto fail;
2777
2778 irqs->offset[i] = phb->msi_base + hwirq;
2779 irqs->range[i] = try;
2780 pr_devel("cxl alloc irq range 0x%x: offset: 0x%lx limit: %li\n",
2781 i, irqs->offset[i], irqs->range[i]);
2782 num -= try;
2783 }
2784 if (num)
2785 goto fail;
2786
2787 return 0;
2788 fail:
2789 pnv_cxl_release_hwirq_ranges(irqs, dev);
2790 return -ENOSPC;
2791 }
2792 EXPORT_SYMBOL(pnv_cxl_alloc_hwirq_ranges);
2793
2794 int pnv_cxl_get_irq_count(struct pci_dev *dev)
2795 {
2796 struct pci_controller *hose = pci_bus_to_host(dev->bus);
2797 struct pnv_phb *phb = hose->private_data;
2798
2799 return phb->msi_bmp.irq_count;
2800 }
2801 EXPORT_SYMBOL(pnv_cxl_get_irq_count);
2802
2803 int pnv_cxl_ioda_msi_setup(struct pci_dev *dev, unsigned int hwirq,
2804 unsigned int virq)
2805 {
2806 struct pci_controller *hose = pci_bus_to_host(dev->bus);
2807 struct pnv_phb *phb = hose->private_data;
2808 unsigned int xive_num = hwirq - phb->msi_base;
2809 struct pnv_ioda_pe *pe;
2810 int rc;
2811
2812 if (!(pe = pnv_ioda_get_pe(dev)))
2813 return -ENODEV;
2814
2815 /* Assign XIVE to PE */
2816 rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num);
2817 if (rc) {
2818 pe_warn(pe, "%s: OPAL error %d setting msi_base 0x%x "
2819 "hwirq 0x%x XIVE 0x%x PE\n",
2820 pci_name(dev), rc, phb->msi_base, hwirq, xive_num);
2821 return -EIO;
2822 }
2823 set_msi_irq_chip(phb, virq);
2824
2825 return 0;
2826 }
2827 EXPORT_SYMBOL(pnv_cxl_ioda_msi_setup);
2828 #endif
2829
2830 static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev,
2831 unsigned int hwirq, unsigned int virq,
2832 unsigned int is_64, struct msi_msg *msg)
2833 {
2834 struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev);
2835 unsigned int xive_num = hwirq - phb->msi_base;
2836 __be32 data;
2837 int rc;
2838
2839 /* No PE assigned ? bail out ... no MSI for you ! */
2840 if (pe == NULL)
2841 return -ENXIO;
2842
2843 /* Check if we have an MVE */
2844 if (pe->mve_number < 0)
2845 return -ENXIO;
2846
2847 /* Force 32-bit MSI on some broken devices */
2848 if (dev->no_64bit_msi)
2849 is_64 = 0;
2850
2851 /* Assign XIVE to PE */
2852 rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num);
2853 if (rc) {
2854 pr_warn("%s: OPAL error %d setting XIVE %d PE\n",
2855 pci_name(dev), rc, xive_num);
2856 return -EIO;
2857 }
2858
2859 if (is_64) {
2860 __be64 addr64;
2861
2862 rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1,
2863 &addr64, &data);
2864 if (rc) {
2865 pr_warn("%s: OPAL error %d getting 64-bit MSI data\n",
2866 pci_name(dev), rc);
2867 return -EIO;
2868 }
2869 msg->address_hi = be64_to_cpu(addr64) >> 32;
2870 msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful;
2871 } else {
2872 __be32 addr32;
2873
2874 rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1,
2875 &addr32, &data);
2876 if (rc) {
2877 pr_warn("%s: OPAL error %d getting 32-bit MSI data\n",
2878 pci_name(dev), rc);
2879 return -EIO;
2880 }
2881 msg->address_hi = 0;
2882 msg->address_lo = be32_to_cpu(addr32);
2883 }
2884 msg->data = be32_to_cpu(data);
2885
2886 set_msi_irq_chip(phb, virq);
2887
2888 pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d),"
2889 " address=%x_%08x data=%x PE# %d\n",
2890 pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num,
2891 msg->address_hi, msg->address_lo, data, pe->pe_number);
2892
2893 return 0;
2894 }
2895
2896 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb)
2897 {
2898 unsigned int count;
2899 const __be32 *prop = of_get_property(phb->hose->dn,
2900 "ibm,opal-msi-ranges", NULL);
2901 if (!prop) {
2902 /* BML Fallback */
2903 prop = of_get_property(phb->hose->dn, "msi-ranges", NULL);
2904 }
2905 if (!prop)
2906 return;
2907
2908 phb->msi_base = be32_to_cpup(prop);
2909 count = be32_to_cpup(prop + 1);
2910 if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) {
2911 pr_err("PCI %d: Failed to allocate MSI bitmap !\n",
2912 phb->hose->global_number);
2913 return;
2914 }
2915
2916 phb->msi_setup = pnv_pci_ioda_msi_setup;
2917 phb->msi32_support = 1;
2918 pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n",
2919 count, phb->msi_base);
2920 }
2921 #else
2922 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { }
2923 #endif /* CONFIG_PCI_MSI */
2924
2925 #ifdef CONFIG_PCI_IOV
2926 static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev)
2927 {
2928 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
2929 struct pnv_phb *phb = hose->private_data;
2930 const resource_size_t gate = phb->ioda.m64_segsize >> 2;
2931 struct resource *res;
2932 int i;
2933 resource_size_t size, total_vf_bar_sz;
2934 struct pci_dn *pdn;
2935 int mul, total_vfs;
2936
2937 if (!pdev->is_physfn || pdev->is_added)
2938 return;
2939
2940 pdn = pci_get_pdn(pdev);
2941 pdn->vfs_expanded = 0;
2942 pdn->m64_single_mode = false;
2943
2944 total_vfs = pci_sriov_get_totalvfs(pdev);
2945 mul = phb->ioda.total_pe_num;
2946 total_vf_bar_sz = 0;
2947
2948 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
2949 res = &pdev->resource[i + PCI_IOV_RESOURCES];
2950 if (!res->flags || res->parent)
2951 continue;
2952 if (!pnv_pci_is_mem_pref_64(res->flags)) {
2953 dev_warn(&pdev->dev, "Don't support SR-IOV with"
2954 " non M64 VF BAR%d: %pR. \n",
2955 i, res);
2956 goto truncate_iov;
2957 }
2958
2959 total_vf_bar_sz += pci_iov_resource_size(pdev,
2960 i + PCI_IOV_RESOURCES);
2961
2962 /*
2963 * If bigger than quarter of M64 segment size, just round up
2964 * power of two.
2965 *
2966 * Generally, one M64 BAR maps one IOV BAR. To avoid conflict
2967 * with other devices, IOV BAR size is expanded to be
2968 * (total_pe * VF_BAR_size). When VF_BAR_size is half of M64
2969 * segment size , the expanded size would equal to half of the
2970 * whole M64 space size, which will exhaust the M64 Space and
2971 * limit the system flexibility. This is a design decision to
2972 * set the boundary to quarter of the M64 segment size.
2973 */
2974 if (total_vf_bar_sz > gate) {
2975 mul = roundup_pow_of_two(total_vfs);
2976 dev_info(&pdev->dev,
2977 "VF BAR Total IOV size %llx > %llx, roundup to %d VFs\n",
2978 total_vf_bar_sz, gate, mul);
2979 pdn->m64_single_mode = true;
2980 break;
2981 }
2982 }
2983
2984 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
2985 res = &pdev->resource[i + PCI_IOV_RESOURCES];
2986 if (!res->flags || res->parent)
2987 continue;
2988
2989 size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES);
2990 /*
2991 * On PHB3, the minimum size alignment of M64 BAR in single
2992 * mode is 32MB.
2993 */
2994 if (pdn->m64_single_mode && (size < SZ_32M))
2995 goto truncate_iov;
2996 dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res);
2997 res->end = res->start + size * mul - 1;
2998 dev_dbg(&pdev->dev, " %pR\n", res);
2999 dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)",
3000 i, res, mul);
3001 }
3002 pdn->vfs_expanded = mul;
3003
3004 return;
3005
3006 truncate_iov:
3007 /* To save MMIO space, IOV BAR is truncated. */
3008 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
3009 res = &pdev->resource[i + PCI_IOV_RESOURCES];
3010 res->flags = 0;
3011 res->end = res->start - 1;
3012 }
3013 }
3014 #endif /* CONFIG_PCI_IOV */
3015
3016 static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe,
3017 struct resource *res)
3018 {
3019 struct pnv_phb *phb = pe->phb;
3020 struct pci_bus_region region;
3021 int index;
3022 int64_t rc;
3023
3024 if (!res || !res->flags || res->start > res->end)
3025 return;
3026
3027 if (res->flags & IORESOURCE_IO) {
3028 region.start = res->start - phb->ioda.io_pci_base;
3029 region.end = res->end - phb->ioda.io_pci_base;
3030 index = region.start / phb->ioda.io_segsize;
3031
3032 while (index < phb->ioda.total_pe_num &&
3033 region.start <= region.end) {
3034 phb->ioda.io_segmap[index] = pe->pe_number;
3035 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3036 pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index);
3037 if (rc != OPAL_SUCCESS) {
3038 pr_err("%s: Error %lld mapping IO segment#%d to PE#%d\n",
3039 __func__, rc, index, pe->pe_number);
3040 break;
3041 }
3042
3043 region.start += phb->ioda.io_segsize;
3044 index++;
3045 }
3046 } else if ((res->flags & IORESOURCE_MEM) &&
3047 !pnv_pci_is_mem_pref_64(res->flags)) {
3048 region.start = res->start -
3049 phb->hose->mem_offset[0] -
3050 phb->ioda.m32_pci_base;
3051 region.end = res->end -
3052 phb->hose->mem_offset[0] -
3053 phb->ioda.m32_pci_base;
3054 index = region.start / phb->ioda.m32_segsize;
3055
3056 while (index < phb->ioda.total_pe_num &&
3057 region.start <= region.end) {
3058 phb->ioda.m32_segmap[index] = pe->pe_number;
3059 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3060 pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index);
3061 if (rc != OPAL_SUCCESS) {
3062 pr_err("%s: Error %lld mapping M32 segment#%d to PE#%d",
3063 __func__, rc, index, pe->pe_number);
3064 break;
3065 }
3066
3067 region.start += phb->ioda.m32_segsize;
3068 index++;
3069 }
3070 }
3071 }
3072
3073 /*
3074 * This function is supposed to be called on basis of PE from top
3075 * to bottom style. So the the I/O or MMIO segment assigned to
3076 * parent PE could be overrided by its child PEs if necessary.
3077 */
3078 static void pnv_ioda_setup_pe_seg(struct pnv_ioda_pe *pe)
3079 {
3080 struct pci_dev *pdev;
3081 int i;
3082
3083 /*
3084 * NOTE: We only care PCI bus based PE for now. For PCI
3085 * device based PE, for example SRIOV sensitive VF should
3086 * be figured out later.
3087 */
3088 BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)));
3089
3090 list_for_each_entry(pdev, &pe->pbus->devices, bus_list) {
3091 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
3092 pnv_ioda_setup_pe_res(pe, &pdev->resource[i]);
3093
3094 /*
3095 * If the PE contains all subordinate PCI buses, the
3096 * windows of the child bridges should be mapped to
3097 * the PE as well.
3098 */
3099 if (!(pe->flags & PNV_IODA_PE_BUS_ALL) || !pci_is_bridge(pdev))
3100 continue;
3101 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
3102 pnv_ioda_setup_pe_res(pe,
3103 &pdev->resource[PCI_BRIDGE_RESOURCES + i]);
3104 }
3105 }
3106
3107 static void pnv_pci_ioda_setup_seg(void)
3108 {
3109 struct pci_controller *tmp, *hose;
3110 struct pnv_phb *phb;
3111 struct pnv_ioda_pe *pe;
3112
3113 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
3114 phb = hose->private_data;
3115
3116 /* NPU PHB does not support IO or MMIO segmentation */
3117 if (phb->type == PNV_PHB_NPU)
3118 continue;
3119
3120 list_for_each_entry(pe, &phb->ioda.pe_list, list) {
3121 pnv_ioda_setup_pe_seg(pe);
3122 }
3123 }
3124 }
3125
3126 static void pnv_pci_ioda_setup_DMA(void)
3127 {
3128 struct pci_controller *hose, *tmp;
3129 struct pnv_phb *phb;
3130
3131 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
3132 pnv_ioda_setup_dma(hose->private_data);
3133
3134 /* Mark the PHB initialization done */
3135 phb = hose->private_data;
3136 phb->initialized = 1;
3137 }
3138 }
3139
3140 static void pnv_pci_ioda_create_dbgfs(void)
3141 {
3142 #ifdef CONFIG_DEBUG_FS
3143 struct pci_controller *hose, *tmp;
3144 struct pnv_phb *phb;
3145 char name[16];
3146
3147 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
3148 phb = hose->private_data;
3149
3150 sprintf(name, "PCI%04x", hose->global_number);
3151 phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root);
3152 if (!phb->dbgfs)
3153 pr_warning("%s: Error on creating debugfs on PHB#%x\n",
3154 __func__, hose->global_number);
3155 }
3156 #endif /* CONFIG_DEBUG_FS */
3157 }
3158
3159 static void pnv_npu_ioda_fixup(void)
3160 {
3161 bool enable_bypass;
3162 struct pci_controller *hose, *tmp;
3163 struct pnv_phb *phb;
3164 struct pnv_ioda_pe *pe;
3165 unsigned int weight;
3166
3167 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
3168 phb = hose->private_data;
3169 if (phb->type != PNV_PHB_NPU)
3170 continue;
3171
3172 list_for_each_entry(pe, &phb->ioda.pe_list, list) {
3173 weight = pnv_pci_ioda_pe_dma_weight(pe);
3174 if (WARN_ON(!weight))
3175 continue;
3176
3177 enable_bypass = dma_get_mask(&pe->pdev->dev) ==
3178 DMA_BIT_MASK(64);
3179 pnv_npu_init_dma_pe(pe);
3180 }
3181 }
3182 }
3183
3184 static void pnv_pci_ioda_fixup(void)
3185 {
3186 pnv_pci_ioda_setup_PEs();
3187 pnv_pci_ioda_setup_seg();
3188 pnv_pci_ioda_setup_DMA();
3189
3190 pnv_pci_ioda_create_dbgfs();
3191
3192 #ifdef CONFIG_EEH
3193 eeh_init();
3194 eeh_addr_cache_build();
3195 #endif
3196
3197 /* Link NPU IODA tables to their PCI devices. */
3198 pnv_npu_ioda_fixup();
3199 }
3200
3201 /*
3202 * Returns the alignment for I/O or memory windows for P2P
3203 * bridges. That actually depends on how PEs are segmented.
3204 * For now, we return I/O or M32 segment size for PE sensitive
3205 * P2P bridges. Otherwise, the default values (4KiB for I/O,
3206 * 1MiB for memory) will be returned.
3207 *
3208 * The current PCI bus might be put into one PE, which was
3209 * create against the parent PCI bridge. For that case, we
3210 * needn't enlarge the alignment so that we can save some
3211 * resources.
3212 */
3213 static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus,
3214 unsigned long type)
3215 {
3216 struct pci_dev *bridge;
3217 struct pci_controller *hose = pci_bus_to_host(bus);
3218 struct pnv_phb *phb = hose->private_data;
3219 int num_pci_bridges = 0;
3220
3221 bridge = bus->self;
3222 while (bridge) {
3223 if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) {
3224 num_pci_bridges++;
3225 if (num_pci_bridges >= 2)
3226 return 1;
3227 }
3228
3229 bridge = bridge->bus->self;
3230 }
3231
3232 /* We fail back to M32 if M64 isn't supported */
3233 if (phb->ioda.m64_segsize &&
3234 pnv_pci_is_mem_pref_64(type))
3235 return phb->ioda.m64_segsize;
3236 if (type & IORESOURCE_MEM)
3237 return phb->ioda.m32_segsize;
3238
3239 return phb->ioda.io_segsize;
3240 }
3241
3242 #ifdef CONFIG_PCI_IOV
3243 static resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev,
3244 int resno)
3245 {
3246 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
3247 struct pnv_phb *phb = hose->private_data;
3248 struct pci_dn *pdn = pci_get_pdn(pdev);
3249 resource_size_t align;
3250
3251 /*
3252 * On PowerNV platform, IOV BAR is mapped by M64 BAR to enable the
3253 * SR-IOV. While from hardware perspective, the range mapped by M64
3254 * BAR should be size aligned.
3255 *
3256 * When IOV BAR is mapped with M64 BAR in Single PE mode, the extra
3257 * powernv-specific hardware restriction is gone. But if just use the
3258 * VF BAR size as the alignment, PF BAR / VF BAR may be allocated with
3259 * in one segment of M64 #15, which introduces the PE conflict between
3260 * PF and VF. Based on this, the minimum alignment of an IOV BAR is
3261 * m64_segsize.
3262 *
3263 * This function returns the total IOV BAR size if M64 BAR is in
3264 * Shared PE mode or just VF BAR size if not.
3265 * If the M64 BAR is in Single PE mode, return the VF BAR size or
3266 * M64 segment size if IOV BAR size is less.
3267 */
3268 align = pci_iov_resource_size(pdev, resno);
3269 if (!pdn->vfs_expanded)
3270 return align;
3271 if (pdn->m64_single_mode)
3272 return max(align, (resource_size_t)phb->ioda.m64_segsize);
3273
3274 return pdn->vfs_expanded * align;
3275 }
3276 #endif /* CONFIG_PCI_IOV */
3277
3278 /* Prevent enabling devices for which we couldn't properly
3279 * assign a PE
3280 */
3281 static bool pnv_pci_enable_device_hook(struct pci_dev *dev)
3282 {
3283 struct pci_controller *hose = pci_bus_to_host(dev->bus);
3284 struct pnv_phb *phb = hose->private_data;
3285 struct pci_dn *pdn;
3286
3287 /* The function is probably called while the PEs have
3288 * not be created yet. For example, resource reassignment
3289 * during PCI probe period. We just skip the check if
3290 * PEs isn't ready.
3291 */
3292 if (!phb->initialized)
3293 return true;
3294
3295 pdn = pci_get_pdn(dev);
3296 if (!pdn || pdn->pe_number == IODA_INVALID_PE)
3297 return false;
3298
3299 return true;
3300 }
3301
3302 static void pnv_pci_ioda_shutdown(struct pci_controller *hose)
3303 {
3304 struct pnv_phb *phb = hose->private_data;
3305
3306 opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE,
3307 OPAL_ASSERT_RESET);
3308 }
3309
3310 static const struct pci_controller_ops pnv_pci_ioda_controller_ops = {
3311 .dma_dev_setup = pnv_pci_dma_dev_setup,
3312 .dma_bus_setup = pnv_pci_dma_bus_setup,
3313 #ifdef CONFIG_PCI_MSI
3314 .setup_msi_irqs = pnv_setup_msi_irqs,
3315 .teardown_msi_irqs = pnv_teardown_msi_irqs,
3316 #endif
3317 .enable_device_hook = pnv_pci_enable_device_hook,
3318 .window_alignment = pnv_pci_window_alignment,
3319 .reset_secondary_bus = pnv_pci_reset_secondary_bus,
3320 .dma_set_mask = pnv_pci_ioda_dma_set_mask,
3321 .dma_get_required_mask = pnv_pci_ioda_dma_get_required_mask,
3322 .shutdown = pnv_pci_ioda_shutdown,
3323 };
3324
3325 static int pnv_npu_dma_set_mask(struct pci_dev *npdev, u64 dma_mask)
3326 {
3327 dev_err_once(&npdev->dev,
3328 "%s operation unsupported for NVLink devices\n",
3329 __func__);
3330 return -EPERM;
3331 }
3332
3333 static const struct pci_controller_ops pnv_npu_ioda_controller_ops = {
3334 .dma_dev_setup = pnv_pci_dma_dev_setup,
3335 #ifdef CONFIG_PCI_MSI
3336 .setup_msi_irqs = pnv_setup_msi_irqs,
3337 .teardown_msi_irqs = pnv_teardown_msi_irqs,
3338 #endif
3339 .enable_device_hook = pnv_pci_enable_device_hook,
3340 .window_alignment = pnv_pci_window_alignment,
3341 .reset_secondary_bus = pnv_pci_reset_secondary_bus,
3342 .dma_set_mask = pnv_npu_dma_set_mask,
3343 .shutdown = pnv_pci_ioda_shutdown,
3344 };
3345
3346 static void __init pnv_pci_init_ioda_phb(struct device_node *np,
3347 u64 hub_id, int ioda_type)
3348 {
3349 struct pci_controller *hose;
3350 struct pnv_phb *phb;
3351 unsigned long size, m64map_off, m32map_off, pemap_off;
3352 unsigned long iomap_off = 0, dma32map_off = 0;
3353 const __be64 *prop64;
3354 const __be32 *prop32;
3355 int len;
3356 unsigned int segno;
3357 u64 phb_id;
3358 void *aux;
3359 long rc;
3360
3361 pr_info("Initializing IODA%d OPAL PHB %s\n", ioda_type, np->full_name);
3362
3363 prop64 = of_get_property(np, "ibm,opal-phbid", NULL);
3364 if (!prop64) {
3365 pr_err(" Missing \"ibm,opal-phbid\" property !\n");
3366 return;
3367 }
3368 phb_id = be64_to_cpup(prop64);
3369 pr_debug(" PHB-ID : 0x%016llx\n", phb_id);
3370
3371 phb = memblock_virt_alloc(sizeof(struct pnv_phb), 0);
3372
3373 /* Allocate PCI controller */
3374 phb->hose = hose = pcibios_alloc_controller(np);
3375 if (!phb->hose) {
3376 pr_err(" Can't allocate PCI controller for %s\n",
3377 np->full_name);
3378 memblock_free(__pa(phb), sizeof(struct pnv_phb));
3379 return;
3380 }
3381
3382 spin_lock_init(&phb->lock);
3383 prop32 = of_get_property(np, "bus-range", &len);
3384 if (prop32 && len == 8) {
3385 hose->first_busno = be32_to_cpu(prop32[0]);
3386 hose->last_busno = be32_to_cpu(prop32[1]);
3387 } else {
3388 pr_warn(" Broken <bus-range> on %s\n", np->full_name);
3389 hose->first_busno = 0;
3390 hose->last_busno = 0xff;
3391 }
3392 hose->private_data = phb;
3393 phb->hub_id = hub_id;
3394 phb->opal_id = phb_id;
3395 phb->type = ioda_type;
3396 mutex_init(&phb->ioda.pe_alloc_mutex);
3397
3398 /* Detect specific models for error handling */
3399 if (of_device_is_compatible(np, "ibm,p7ioc-pciex"))
3400 phb->model = PNV_PHB_MODEL_P7IOC;
3401 else if (of_device_is_compatible(np, "ibm,power8-pciex"))
3402 phb->model = PNV_PHB_MODEL_PHB3;
3403 else if (of_device_is_compatible(np, "ibm,power8-npu-pciex"))
3404 phb->model = PNV_PHB_MODEL_NPU;
3405 else
3406 phb->model = PNV_PHB_MODEL_UNKNOWN;
3407
3408 /* Parse 32-bit and IO ranges (if any) */
3409 pci_process_bridge_OF_ranges(hose, np, !hose->global_number);
3410
3411 /* Get registers */
3412 phb->regs = of_iomap(np, 0);
3413 if (phb->regs == NULL)
3414 pr_err(" Failed to map registers !\n");
3415
3416 /* Initialize more IODA stuff */
3417 phb->ioda.total_pe_num = 1;
3418 prop32 = of_get_property(np, "ibm,opal-num-pes", NULL);
3419 if (prop32)
3420 phb->ioda.total_pe_num = be32_to_cpup(prop32);
3421 prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL);
3422 if (prop32)
3423 phb->ioda.reserved_pe_idx = be32_to_cpup(prop32);
3424
3425 /* Parse 64-bit MMIO range */
3426 pnv_ioda_parse_m64_window(phb);
3427
3428 phb->ioda.m32_size = resource_size(&hose->mem_resources[0]);
3429 /* FW Has already off top 64k of M32 space (MSI space) */
3430 phb->ioda.m32_size += 0x10000;
3431
3432 phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe_num;
3433 phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0];
3434 phb->ioda.io_size = hose->pci_io_size;
3435 phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe_num;
3436 phb->ioda.io_pci_base = 0; /* XXX calculate this ? */
3437
3438 /* Calculate how many 32-bit TCE segments we have */
3439 phb->ioda.dma32_count = phb->ioda.m32_pci_base /
3440 PNV_IODA1_DMA32_SEGSIZE;
3441
3442 /* Allocate aux data & arrays. We don't have IO ports on PHB3 */
3443 size = _ALIGN_UP(phb->ioda.total_pe_num / 8, sizeof(unsigned long));
3444 m64map_off = size;
3445 size += phb->ioda.total_pe_num * sizeof(phb->ioda.m64_segmap[0]);
3446 m32map_off = size;
3447 size += phb->ioda.total_pe_num * sizeof(phb->ioda.m32_segmap[0]);
3448 if (phb->type == PNV_PHB_IODA1) {
3449 iomap_off = size;
3450 size += phb->ioda.total_pe_num * sizeof(phb->ioda.io_segmap[0]);
3451 dma32map_off = size;
3452 size += phb->ioda.dma32_count *
3453 sizeof(phb->ioda.dma32_segmap[0]);
3454 }
3455 pemap_off = size;
3456 size += phb->ioda.total_pe_num * sizeof(struct pnv_ioda_pe);
3457 aux = memblock_virt_alloc(size, 0);
3458 phb->ioda.pe_alloc = aux;
3459 phb->ioda.m64_segmap = aux + m64map_off;
3460 phb->ioda.m32_segmap = aux + m32map_off;
3461 for (segno = 0; segno < phb->ioda.total_pe_num; segno++) {
3462 phb->ioda.m64_segmap[segno] = IODA_INVALID_PE;
3463 phb->ioda.m32_segmap[segno] = IODA_INVALID_PE;
3464 }
3465 if (phb->type == PNV_PHB_IODA1) {
3466 phb->ioda.io_segmap = aux + iomap_off;
3467 for (segno = 0; segno < phb->ioda.total_pe_num; segno++)
3468 phb->ioda.io_segmap[segno] = IODA_INVALID_PE;
3469
3470 phb->ioda.dma32_segmap = aux + dma32map_off;
3471 for (segno = 0; segno < phb->ioda.dma32_count; segno++)
3472 phb->ioda.dma32_segmap[segno] = IODA_INVALID_PE;
3473 }
3474 phb->ioda.pe_array = aux + pemap_off;
3475 set_bit(phb->ioda.reserved_pe_idx, phb->ioda.pe_alloc);
3476
3477 INIT_LIST_HEAD(&phb->ioda.pe_list);
3478 mutex_init(&phb->ioda.pe_list_mutex);
3479
3480 /* Calculate how many 32-bit TCE segments we have */
3481 phb->ioda.dma32_count = phb->ioda.m32_pci_base /
3482 PNV_IODA1_DMA32_SEGSIZE;
3483
3484 #if 0 /* We should really do that ... */
3485 rc = opal_pci_set_phb_mem_window(opal->phb_id,
3486 window_type,
3487 window_num,
3488 starting_real_address,
3489 starting_pci_address,
3490 segment_size);
3491 #endif
3492
3493 pr_info(" %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n",
3494 phb->ioda.total_pe_num, phb->ioda.reserved_pe_idx,
3495 phb->ioda.m32_size, phb->ioda.m32_segsize);
3496 if (phb->ioda.m64_size)
3497 pr_info(" M64: 0x%lx [segment=0x%lx]\n",
3498 phb->ioda.m64_size, phb->ioda.m64_segsize);
3499 if (phb->ioda.io_size)
3500 pr_info(" IO: 0x%x [segment=0x%x]\n",
3501 phb->ioda.io_size, phb->ioda.io_segsize);
3502
3503
3504 phb->hose->ops = &pnv_pci_ops;
3505 phb->get_pe_state = pnv_ioda_get_pe_state;
3506 phb->freeze_pe = pnv_ioda_freeze_pe;
3507 phb->unfreeze_pe = pnv_ioda_unfreeze_pe;
3508
3509 /* Setup MSI support */
3510 pnv_pci_init_ioda_msis(phb);
3511
3512 /*
3513 * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here
3514 * to let the PCI core do resource assignment. It's supposed
3515 * that the PCI core will do correct I/O and MMIO alignment
3516 * for the P2P bridge bars so that each PCI bus (excluding
3517 * the child P2P bridges) can form individual PE.
3518 */
3519 ppc_md.pcibios_fixup = pnv_pci_ioda_fixup;
3520
3521 if (phb->type == PNV_PHB_NPU) {
3522 hose->controller_ops = pnv_npu_ioda_controller_ops;
3523 } else {
3524 phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup;
3525 hose->controller_ops = pnv_pci_ioda_controller_ops;
3526 }
3527
3528 #ifdef CONFIG_PCI_IOV
3529 ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov_resources;
3530 ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment;
3531 #endif
3532
3533 pci_add_flags(PCI_REASSIGN_ALL_RSRC);
3534
3535 /* Reset IODA tables to a clean state */
3536 rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET);
3537 if (rc)
3538 pr_warning(" OPAL Error %ld performing IODA table reset !\n", rc);
3539
3540 /* If we're running in kdump kerenl, the previous kerenl never
3541 * shutdown PCI devices correctly. We already got IODA table
3542 * cleaned out. So we have to issue PHB reset to stop all PCI
3543 * transactions from previous kerenl.
3544 */
3545 if (is_kdump_kernel()) {
3546 pr_info(" Issue PHB reset ...\n");
3547 pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL);
3548 pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE);
3549 }
3550
3551 /* Remove M64 resource if we can't configure it successfully */
3552 if (!phb->init_m64 || phb->init_m64(phb))
3553 hose->mem_resources[1].flags = 0;
3554 }
3555
3556 void __init pnv_pci_init_ioda2_phb(struct device_node *np)
3557 {
3558 pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2);
3559 }
3560
3561 void __init pnv_pci_init_npu_phb(struct device_node *np)
3562 {
3563 pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU);
3564 }
3565
3566 void __init pnv_pci_init_ioda_hub(struct device_node *np)
3567 {
3568 struct device_node *phbn;
3569 const __be64 *prop64;
3570 u64 hub_id;
3571
3572 pr_info("Probing IODA IO-Hub %s\n", np->full_name);
3573
3574 prop64 = of_get_property(np, "ibm,opal-hubid", NULL);
3575 if (!prop64) {
3576 pr_err(" Missing \"ibm,opal-hubid\" property !\n");
3577 return;
3578 }
3579 hub_id = be64_to_cpup(prop64);
3580 pr_devel(" HUB-ID : 0x%016llx\n", hub_id);
3581
3582 /* Count child PHBs */
3583 for_each_child_of_node(np, phbn) {
3584 /* Look for IODA1 PHBs */
3585 if (of_device_is_compatible(phbn, "ibm,ioda-phb"))
3586 pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1);
3587 }
3588 }
Linux kernel - Deliverables
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