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Merge branch 'sched-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[deliverable/linux.git] / arch / powerpc / platforms / powernv / pci-ioda.c
1 /*
2 * Support PCI/PCIe on PowerNV platforms
3 *
4 * Copyright 2011 Benjamin Herrenschmidt, IBM Corp.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12 #undef DEBUG
13
14 #include <linux/kernel.h>
15 #include <linux/pci.h>
16 #include <linux/crash_dump.h>
17 #include <linux/debugfs.h>
18 #include <linux/delay.h>
19 #include <linux/string.h>
20 #include <linux/init.h>
21 #include <linux/bootmem.h>
22 #include <linux/irq.h>
23 #include <linux/io.h>
24 #include <linux/msi.h>
25 #include <linux/memblock.h>
26 #include <linux/iommu.h>
27 #include <linux/rculist.h>
28 #include <linux/sizes.h>
29
30 #include <asm/sections.h>
31 #include <asm/io.h>
32 #include <asm/prom.h>
33 #include <asm/pci-bridge.h>
34 #include <asm/machdep.h>
35 #include <asm/msi_bitmap.h>
36 #include <asm/ppc-pci.h>
37 #include <asm/opal.h>
38 #include <asm/iommu.h>
39 #include <asm/tce.h>
40 #include <asm/xics.h>
41 #include <asm/debug.h>
42 #include <asm/firmware.h>
43 #include <asm/pnv-pci.h>
44 #include <asm/mmzone.h>
45
46 #include <misc/cxl-base.h>
47
48 #include "powernv.h"
49 #include "pci.h"
50
51 /* 256M DMA window, 4K TCE pages, 8 bytes TCE */
52 #define TCE32_TABLE_SIZE ((0x10000000 / 0x1000) * 8)
53
54 #define POWERNV_IOMMU_DEFAULT_LEVELS 1
55 #define POWERNV_IOMMU_MAX_LEVELS 5
56
57 static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl);
58
59 static void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level,
60 const char *fmt, ...)
61 {
62 struct va_format vaf;
63 va_list args;
64 char pfix[32];
65
66 va_start(args, fmt);
67
68 vaf.fmt = fmt;
69 vaf.va = &args;
70
71 if (pe->flags & PNV_IODA_PE_DEV)
72 strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix));
73 else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
74 sprintf(pfix, "%04x:%02x ",
75 pci_domain_nr(pe->pbus), pe->pbus->number);
76 #ifdef CONFIG_PCI_IOV
77 else if (pe->flags & PNV_IODA_PE_VF)
78 sprintf(pfix, "%04x:%02x:%2x.%d",
79 pci_domain_nr(pe->parent_dev->bus),
80 (pe->rid & 0xff00) >> 8,
81 PCI_SLOT(pe->rid), PCI_FUNC(pe->rid));
82 #endif /* CONFIG_PCI_IOV*/
83
84 printk("%spci %s: [PE# %.3d] %pV",
85 level, pfix, pe->pe_number, &vaf);
86
87 va_end(args);
88 }
89
90 #define pe_err(pe, fmt, ...) \
91 pe_level_printk(pe, KERN_ERR, fmt, ##__VA_ARGS__)
92 #define pe_warn(pe, fmt, ...) \
93 pe_level_printk(pe, KERN_WARNING, fmt, ##__VA_ARGS__)
94 #define pe_info(pe, fmt, ...) \
95 pe_level_printk(pe, KERN_INFO, fmt, ##__VA_ARGS__)
96
97 static bool pnv_iommu_bypass_disabled __read_mostly;
98
99 static int __init iommu_setup(char *str)
100 {
101 if (!str)
102 return -EINVAL;
103
104 while (*str) {
105 if (!strncmp(str, "nobypass", 8)) {
106 pnv_iommu_bypass_disabled = true;
107 pr_info("PowerNV: IOMMU bypass window disabled.\n");
108 break;
109 }
110 str += strcspn(str, ",");
111 if (*str == ',')
112 str++;
113 }
114
115 return 0;
116 }
117 early_param("iommu", iommu_setup);
118
119 static inline bool pnv_pci_is_mem_pref_64(unsigned long flags)
120 {
121 return ((flags & (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH)) ==
122 (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH));
123 }
124
125 static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no)
126 {
127 if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe)) {
128 pr_warn("%s: Invalid PE %d on PHB#%x\n",
129 __func__, pe_no, phb->hose->global_number);
130 return;
131 }
132
133 if (test_and_set_bit(pe_no, phb->ioda.pe_alloc))
134 pr_debug("%s: PE %d was reserved on PHB#%x\n",
135 __func__, pe_no, phb->hose->global_number);
136
137 phb->ioda.pe_array[pe_no].phb = phb;
138 phb->ioda.pe_array[pe_no].pe_number = pe_no;
139 }
140
141 static int pnv_ioda_alloc_pe(struct pnv_phb *phb)
142 {
143 unsigned long pe;
144
145 do {
146 pe = find_next_zero_bit(phb->ioda.pe_alloc,
147 phb->ioda.total_pe, 0);
148 if (pe >= phb->ioda.total_pe)
149 return IODA_INVALID_PE;
150 } while(test_and_set_bit(pe, phb->ioda.pe_alloc));
151
152 phb->ioda.pe_array[pe].phb = phb;
153 phb->ioda.pe_array[pe].pe_number = pe;
154 return pe;
155 }
156
157 static void pnv_ioda_free_pe(struct pnv_phb *phb, int pe)
158 {
159 WARN_ON(phb->ioda.pe_array[pe].pdev);
160
161 memset(&phb->ioda.pe_array[pe], 0, sizeof(struct pnv_ioda_pe));
162 clear_bit(pe, phb->ioda.pe_alloc);
163 }
164
165 /* The default M64 BAR is shared by all PEs */
166 static int pnv_ioda2_init_m64(struct pnv_phb *phb)
167 {
168 const char *desc;
169 struct resource *r;
170 s64 rc;
171
172 /* Configure the default M64 BAR */
173 rc = opal_pci_set_phb_mem_window(phb->opal_id,
174 OPAL_M64_WINDOW_TYPE,
175 phb->ioda.m64_bar_idx,
176 phb->ioda.m64_base,
177 0, /* unused */
178 phb->ioda.m64_size);
179 if (rc != OPAL_SUCCESS) {
180 desc = "configuring";
181 goto fail;
182 }
183
184 /* Enable the default M64 BAR */
185 rc = opal_pci_phb_mmio_enable(phb->opal_id,
186 OPAL_M64_WINDOW_TYPE,
187 phb->ioda.m64_bar_idx,
188 OPAL_ENABLE_M64_SPLIT);
189 if (rc != OPAL_SUCCESS) {
190 desc = "enabling";
191 goto fail;
192 }
193
194 /* Mark the M64 BAR assigned */
195 set_bit(phb->ioda.m64_bar_idx, &phb->ioda.m64_bar_alloc);
196
197 /*
198 * Strip off the segment used by the reserved PE, which is
199 * expected to be 0 or last one of PE capabicity.
200 */
201 r = &phb->hose->mem_resources[1];
202 if (phb->ioda.reserved_pe == 0)
203 r->start += phb->ioda.m64_segsize;
204 else if (phb->ioda.reserved_pe == (phb->ioda.total_pe - 1))
205 r->end -= phb->ioda.m64_segsize;
206 else
207 pr_warn(" Cannot strip M64 segment for reserved PE#%d\n",
208 phb->ioda.reserved_pe);
209
210 return 0;
211
212 fail:
213 pr_warn(" Failure %lld %s M64 BAR#%d\n",
214 rc, desc, phb->ioda.m64_bar_idx);
215 opal_pci_phb_mmio_enable(phb->opal_id,
216 OPAL_M64_WINDOW_TYPE,
217 phb->ioda.m64_bar_idx,
218 OPAL_DISABLE_M64);
219 return -EIO;
220 }
221
222 static void pnv_ioda2_reserve_dev_m64_pe(struct pci_dev *pdev,
223 unsigned long *pe_bitmap)
224 {
225 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
226 struct pnv_phb *phb = hose->private_data;
227 struct resource *r;
228 resource_size_t base, sgsz, start, end;
229 int segno, i;
230
231 base = phb->ioda.m64_base;
232 sgsz = phb->ioda.m64_segsize;
233 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
234 r = &pdev->resource[i];
235 if (!r->parent || !pnv_pci_is_mem_pref_64(r->flags))
236 continue;
237
238 start = _ALIGN_DOWN(r->start - base, sgsz);
239 end = _ALIGN_UP(r->end - base, sgsz);
240 for (segno = start / sgsz; segno < end / sgsz; segno++) {
241 if (pe_bitmap)
242 set_bit(segno, pe_bitmap);
243 else
244 pnv_ioda_reserve_pe(phb, segno);
245 }
246 }
247 }
248
249 static void pnv_ioda2_reserve_m64_pe(struct pci_bus *bus,
250 unsigned long *pe_bitmap,
251 bool all)
252 {
253 struct pci_dev *pdev;
254
255 list_for_each_entry(pdev, &bus->devices, bus_list) {
256 pnv_ioda2_reserve_dev_m64_pe(pdev, pe_bitmap);
257
258 if (all && pdev->subordinate)
259 pnv_ioda2_reserve_m64_pe(pdev->subordinate,
260 pe_bitmap, all);
261 }
262 }
263
264 static int pnv_ioda2_pick_m64_pe(struct pci_bus *bus, bool all)
265 {
266 struct pci_controller *hose = pci_bus_to_host(bus);
267 struct pnv_phb *phb = hose->private_data;
268 struct pnv_ioda_pe *master_pe, *pe;
269 unsigned long size, *pe_alloc;
270 int i;
271
272 /* Root bus shouldn't use M64 */
273 if (pci_is_root_bus(bus))
274 return IODA_INVALID_PE;
275
276 /* Allocate bitmap */
277 size = _ALIGN_UP(phb->ioda.total_pe / 8, sizeof(unsigned long));
278 pe_alloc = kzalloc(size, GFP_KERNEL);
279 if (!pe_alloc) {
280 pr_warn("%s: Out of memory !\n",
281 __func__);
282 return IODA_INVALID_PE;
283 }
284
285 /* Figure out reserved PE numbers by the PE */
286 pnv_ioda2_reserve_m64_pe(bus, pe_alloc, all);
287
288 /*
289 * the current bus might not own M64 window and that's all
290 * contributed by its child buses. For the case, we needn't
291 * pick M64 dependent PE#.
292 */
293 if (bitmap_empty(pe_alloc, phb->ioda.total_pe)) {
294 kfree(pe_alloc);
295 return IODA_INVALID_PE;
296 }
297
298 /*
299 * Figure out the master PE and put all slave PEs to master
300 * PE's list to form compound PE.
301 */
302 master_pe = NULL;
303 i = -1;
304 while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe, i + 1)) <
305 phb->ioda.total_pe) {
306 pe = &phb->ioda.pe_array[i];
307
308 if (!master_pe) {
309 pe->flags |= PNV_IODA_PE_MASTER;
310 INIT_LIST_HEAD(&pe->slaves);
311 master_pe = pe;
312 } else {
313 pe->flags |= PNV_IODA_PE_SLAVE;
314 pe->master = master_pe;
315 list_add_tail(&pe->list, &master_pe->slaves);
316 }
317 }
318
319 kfree(pe_alloc);
320 return master_pe->pe_number;
321 }
322
323 static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb)
324 {
325 struct pci_controller *hose = phb->hose;
326 struct device_node *dn = hose->dn;
327 struct resource *res;
328 const u32 *r;
329 u64 pci_addr;
330
331 /* FIXME: Support M64 for P7IOC */
332 if (phb->type != PNV_PHB_IODA2) {
333 pr_info(" Not support M64 window\n");
334 return;
335 }
336
337 if (!firmware_has_feature(FW_FEATURE_OPAL)) {
338 pr_info(" Firmware too old to support M64 window\n");
339 return;
340 }
341
342 r = of_get_property(dn, "ibm,opal-m64-window", NULL);
343 if (!r) {
344 pr_info(" No <ibm,opal-m64-window> on %s\n",
345 dn->full_name);
346 return;
347 }
348
349 res = &hose->mem_resources[1];
350 res->name = dn->full_name;
351 res->start = of_translate_address(dn, r + 2);
352 res->end = res->start + of_read_number(r + 4, 2) - 1;
353 res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH);
354 pci_addr = of_read_number(r, 2);
355 hose->mem_offset[1] = res->start - pci_addr;
356
357 phb->ioda.m64_size = resource_size(res);
358 phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe;
359 phb->ioda.m64_base = pci_addr;
360
361 pr_info(" MEM64 0x%016llx..0x%016llx -> 0x%016llx\n",
362 res->start, res->end, pci_addr);
363
364 /* Use last M64 BAR to cover M64 window */
365 phb->ioda.m64_bar_idx = 15;
366 phb->init_m64 = pnv_ioda2_init_m64;
367 phb->reserve_m64_pe = pnv_ioda2_reserve_m64_pe;
368 phb->pick_m64_pe = pnv_ioda2_pick_m64_pe;
369 }
370
371 static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no)
372 {
373 struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no];
374 struct pnv_ioda_pe *slave;
375 s64 rc;
376
377 /* Fetch master PE */
378 if (pe->flags & PNV_IODA_PE_SLAVE) {
379 pe = pe->master;
380 if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)))
381 return;
382
383 pe_no = pe->pe_number;
384 }
385
386 /* Freeze master PE */
387 rc = opal_pci_eeh_freeze_set(phb->opal_id,
388 pe_no,
389 OPAL_EEH_ACTION_SET_FREEZE_ALL);
390 if (rc != OPAL_SUCCESS) {
391 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
392 __func__, rc, phb->hose->global_number, pe_no);
393 return;
394 }
395
396 /* Freeze slave PEs */
397 if (!(pe->flags & PNV_IODA_PE_MASTER))
398 return;
399
400 list_for_each_entry(slave, &pe->slaves, list) {
401 rc = opal_pci_eeh_freeze_set(phb->opal_id,
402 slave->pe_number,
403 OPAL_EEH_ACTION_SET_FREEZE_ALL);
404 if (rc != OPAL_SUCCESS)
405 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
406 __func__, rc, phb->hose->global_number,
407 slave->pe_number);
408 }
409 }
410
411 static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt)
412 {
413 struct pnv_ioda_pe *pe, *slave;
414 s64 rc;
415
416 /* Find master PE */
417 pe = &phb->ioda.pe_array[pe_no];
418 if (pe->flags & PNV_IODA_PE_SLAVE) {
419 pe = pe->master;
420 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
421 pe_no = pe->pe_number;
422 }
423
424 /* Clear frozen state for master PE */
425 rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt);
426 if (rc != OPAL_SUCCESS) {
427 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
428 __func__, rc, opt, phb->hose->global_number, pe_no);
429 return -EIO;
430 }
431
432 if (!(pe->flags & PNV_IODA_PE_MASTER))
433 return 0;
434
435 /* Clear frozen state for slave PEs */
436 list_for_each_entry(slave, &pe->slaves, list) {
437 rc = opal_pci_eeh_freeze_clear(phb->opal_id,
438 slave->pe_number,
439 opt);
440 if (rc != OPAL_SUCCESS) {
441 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
442 __func__, rc, opt, phb->hose->global_number,
443 slave->pe_number);
444 return -EIO;
445 }
446 }
447
448 return 0;
449 }
450
451 static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no)
452 {
453 struct pnv_ioda_pe *slave, *pe;
454 u8 fstate, state;
455 __be16 pcierr;
456 s64 rc;
457
458 /* Sanity check on PE number */
459 if (pe_no < 0 || pe_no >= phb->ioda.total_pe)
460 return OPAL_EEH_STOPPED_PERM_UNAVAIL;
461
462 /*
463 * Fetch the master PE and the PE instance might be
464 * not initialized yet.
465 */
466 pe = &phb->ioda.pe_array[pe_no];
467 if (pe->flags & PNV_IODA_PE_SLAVE) {
468 pe = pe->master;
469 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
470 pe_no = pe->pe_number;
471 }
472
473 /* Check the master PE */
474 rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no,
475 &state, &pcierr, NULL);
476 if (rc != OPAL_SUCCESS) {
477 pr_warn("%s: Failure %lld getting "
478 "PHB#%x-PE#%x state\n",
479 __func__, rc,
480 phb->hose->global_number, pe_no);
481 return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
482 }
483
484 /* Check the slave PE */
485 if (!(pe->flags & PNV_IODA_PE_MASTER))
486 return state;
487
488 list_for_each_entry(slave, &pe->slaves, list) {
489 rc = opal_pci_eeh_freeze_status(phb->opal_id,
490 slave->pe_number,
491 &fstate,
492 &pcierr,
493 NULL);
494 if (rc != OPAL_SUCCESS) {
495 pr_warn("%s: Failure %lld getting "
496 "PHB#%x-PE#%x state\n",
497 __func__, rc,
498 phb->hose->global_number, slave->pe_number);
499 return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
500 }
501
502 /*
503 * Override the result based on the ascending
504 * priority.
505 */
506 if (fstate > state)
507 state = fstate;
508 }
509
510 return state;
511 }
512
513 /* Currently those 2 are only used when MSIs are enabled, this will change
514 * but in the meantime, we need to protect them to avoid warnings
515 */
516 #ifdef CONFIG_PCI_MSI
517 static struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev)
518 {
519 struct pci_controller *hose = pci_bus_to_host(dev->bus);
520 struct pnv_phb *phb = hose->private_data;
521 struct pci_dn *pdn = pci_get_pdn(dev);
522
523 if (!pdn)
524 return NULL;
525 if (pdn->pe_number == IODA_INVALID_PE)
526 return NULL;
527 return &phb->ioda.pe_array[pdn->pe_number];
528 }
529 #endif /* CONFIG_PCI_MSI */
530
531 static int pnv_ioda_set_one_peltv(struct pnv_phb *phb,
532 struct pnv_ioda_pe *parent,
533 struct pnv_ioda_pe *child,
534 bool is_add)
535 {
536 const char *desc = is_add ? "adding" : "removing";
537 uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN :
538 OPAL_REMOVE_PE_FROM_DOMAIN;
539 struct pnv_ioda_pe *slave;
540 long rc;
541
542 /* Parent PE affects child PE */
543 rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number,
544 child->pe_number, op);
545 if (rc != OPAL_SUCCESS) {
546 pe_warn(child, "OPAL error %ld %s to parent PELTV\n",
547 rc, desc);
548 return -ENXIO;
549 }
550
551 if (!(child->flags & PNV_IODA_PE_MASTER))
552 return 0;
553
554 /* Compound case: parent PE affects slave PEs */
555 list_for_each_entry(slave, &child->slaves, list) {
556 rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number,
557 slave->pe_number, op);
558 if (rc != OPAL_SUCCESS) {
559 pe_warn(slave, "OPAL error %ld %s to parent PELTV\n",
560 rc, desc);
561 return -ENXIO;
562 }
563 }
564
565 return 0;
566 }
567
568 static int pnv_ioda_set_peltv(struct pnv_phb *phb,
569 struct pnv_ioda_pe *pe,
570 bool is_add)
571 {
572 struct pnv_ioda_pe *slave;
573 struct pci_dev *pdev = NULL;
574 int ret;
575
576 /*
577 * Clear PE frozen state. If it's master PE, we need
578 * clear slave PE frozen state as well.
579 */
580 if (is_add) {
581 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
582 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
583 if (pe->flags & PNV_IODA_PE_MASTER) {
584 list_for_each_entry(slave, &pe->slaves, list)
585 opal_pci_eeh_freeze_clear(phb->opal_id,
586 slave->pe_number,
587 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
588 }
589 }
590
591 /*
592 * Associate PE in PELT. We need add the PE into the
593 * corresponding PELT-V as well. Otherwise, the error
594 * originated from the PE might contribute to other
595 * PEs.
596 */
597 ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add);
598 if (ret)
599 return ret;
600
601 /* For compound PEs, any one affects all of them */
602 if (pe->flags & PNV_IODA_PE_MASTER) {
603 list_for_each_entry(slave, &pe->slaves, list) {
604 ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add);
605 if (ret)
606 return ret;
607 }
608 }
609
610 if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS))
611 pdev = pe->pbus->self;
612 else if (pe->flags & PNV_IODA_PE_DEV)
613 pdev = pe->pdev->bus->self;
614 #ifdef CONFIG_PCI_IOV
615 else if (pe->flags & PNV_IODA_PE_VF)
616 pdev = pe->parent_dev;
617 #endif /* CONFIG_PCI_IOV */
618 while (pdev) {
619 struct pci_dn *pdn = pci_get_pdn(pdev);
620 struct pnv_ioda_pe *parent;
621
622 if (pdn && pdn->pe_number != IODA_INVALID_PE) {
623 parent = &phb->ioda.pe_array[pdn->pe_number];
624 ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add);
625 if (ret)
626 return ret;
627 }
628
629 pdev = pdev->bus->self;
630 }
631
632 return 0;
633 }
634
635 #ifdef CONFIG_PCI_IOV
636 static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
637 {
638 struct pci_dev *parent;
639 uint8_t bcomp, dcomp, fcomp;
640 int64_t rc;
641 long rid_end, rid;
642
643 /* Currently, we just deconfigure VF PE. Bus PE will always there.*/
644 if (pe->pbus) {
645 int count;
646
647 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
648 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
649 parent = pe->pbus->self;
650 if (pe->flags & PNV_IODA_PE_BUS_ALL)
651 count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
652 else
653 count = 1;
654
655 switch(count) {
656 case 1: bcomp = OpalPciBusAll; break;
657 case 2: bcomp = OpalPciBus7Bits; break;
658 case 4: bcomp = OpalPciBus6Bits; break;
659 case 8: bcomp = OpalPciBus5Bits; break;
660 case 16: bcomp = OpalPciBus4Bits; break;
661 case 32: bcomp = OpalPciBus3Bits; break;
662 default:
663 dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
664 count);
665 /* Do an exact match only */
666 bcomp = OpalPciBusAll;
667 }
668 rid_end = pe->rid + (count << 8);
669 } else {
670 if (pe->flags & PNV_IODA_PE_VF)
671 parent = pe->parent_dev;
672 else
673 parent = pe->pdev->bus->self;
674 bcomp = OpalPciBusAll;
675 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
676 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
677 rid_end = pe->rid + 1;
678 }
679
680 /* Clear the reverse map */
681 for (rid = pe->rid; rid < rid_end; rid++)
682 phb->ioda.pe_rmap[rid] = 0;
683
684 /* Release from all parents PELT-V */
685 while (parent) {
686 struct pci_dn *pdn = pci_get_pdn(parent);
687 if (pdn && pdn->pe_number != IODA_INVALID_PE) {
688 rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number,
689 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN);
690 /* XXX What to do in case of error ? */
691 }
692 parent = parent->bus->self;
693 }
694
695 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
696 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
697
698 /* Disassociate PE in PELT */
699 rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number,
700 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN);
701 if (rc)
702 pe_warn(pe, "OPAL error %ld remove self from PELTV\n", rc);
703 rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
704 bcomp, dcomp, fcomp, OPAL_UNMAP_PE);
705 if (rc)
706 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
707
708 pe->pbus = NULL;
709 pe->pdev = NULL;
710 pe->parent_dev = NULL;
711
712 return 0;
713 }
714 #endif /* CONFIG_PCI_IOV */
715
716 static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
717 {
718 struct pci_dev *parent;
719 uint8_t bcomp, dcomp, fcomp;
720 long rc, rid_end, rid;
721
722 /* Bus validation ? */
723 if (pe->pbus) {
724 int count;
725
726 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
727 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
728 parent = pe->pbus->self;
729 if (pe->flags & PNV_IODA_PE_BUS_ALL)
730 count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
731 else
732 count = 1;
733
734 switch(count) {
735 case 1: bcomp = OpalPciBusAll; break;
736 case 2: bcomp = OpalPciBus7Bits; break;
737 case 4: bcomp = OpalPciBus6Bits; break;
738 case 8: bcomp = OpalPciBus5Bits; break;
739 case 16: bcomp = OpalPciBus4Bits; break;
740 case 32: bcomp = OpalPciBus3Bits; break;
741 default:
742 dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
743 count);
744 /* Do an exact match only */
745 bcomp = OpalPciBusAll;
746 }
747 rid_end = pe->rid + (count << 8);
748 } else {
749 #ifdef CONFIG_PCI_IOV
750 if (pe->flags & PNV_IODA_PE_VF)
751 parent = pe->parent_dev;
752 else
753 #endif /* CONFIG_PCI_IOV */
754 parent = pe->pdev->bus->self;
755 bcomp = OpalPciBusAll;
756 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
757 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
758 rid_end = pe->rid + 1;
759 }
760
761 /*
762 * Associate PE in PELT. We need add the PE into the
763 * corresponding PELT-V as well. Otherwise, the error
764 * originated from the PE might contribute to other
765 * PEs.
766 */
767 rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
768 bcomp, dcomp, fcomp, OPAL_MAP_PE);
769 if (rc) {
770 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
771 return -ENXIO;
772 }
773
774 /*
775 * Configure PELTV. NPUs don't have a PELTV table so skip
776 * configuration on them.
777 */
778 if (phb->type != PNV_PHB_NPU)
779 pnv_ioda_set_peltv(phb, pe, true);
780
781 /* Setup reverse map */
782 for (rid = pe->rid; rid < rid_end; rid++)
783 phb->ioda.pe_rmap[rid] = pe->pe_number;
784
785 /* Setup one MVTs on IODA1 */
786 if (phb->type != PNV_PHB_IODA1) {
787 pe->mve_number = 0;
788 goto out;
789 }
790
791 pe->mve_number = pe->pe_number;
792 rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number);
793 if (rc != OPAL_SUCCESS) {
794 pe_err(pe, "OPAL error %ld setting up MVE %d\n",
795 rc, pe->mve_number);
796 pe->mve_number = -1;
797 } else {
798 rc = opal_pci_set_mve_enable(phb->opal_id,
799 pe->mve_number, OPAL_ENABLE_MVE);
800 if (rc) {
801 pe_err(pe, "OPAL error %ld enabling MVE %d\n",
802 rc, pe->mve_number);
803 pe->mve_number = -1;
804 }
805 }
806
807 out:
808 return 0;
809 }
810
811 static void pnv_ioda_link_pe_by_weight(struct pnv_phb *phb,
812 struct pnv_ioda_pe *pe)
813 {
814 struct pnv_ioda_pe *lpe;
815
816 list_for_each_entry(lpe, &phb->ioda.pe_dma_list, dma_link) {
817 if (lpe->dma_weight < pe->dma_weight) {
818 list_add_tail(&pe->dma_link, &lpe->dma_link);
819 return;
820 }
821 }
822 list_add_tail(&pe->dma_link, &phb->ioda.pe_dma_list);
823 }
824
825 static unsigned int pnv_ioda_dma_weight(struct pci_dev *dev)
826 {
827 /* This is quite simplistic. The "base" weight of a device
828 * is 10. 0 means no DMA is to be accounted for it.
829 */
830
831 /* If it's a bridge, no DMA */
832 if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL)
833 return 0;
834
835 /* Reduce the weight of slow USB controllers */
836 if (dev->class == PCI_CLASS_SERIAL_USB_UHCI ||
837 dev->class == PCI_CLASS_SERIAL_USB_OHCI ||
838 dev->class == PCI_CLASS_SERIAL_USB_EHCI)
839 return 3;
840
841 /* Increase the weight of RAID (includes Obsidian) */
842 if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID)
843 return 15;
844
845 /* Default */
846 return 10;
847 }
848
849 #ifdef CONFIG_PCI_IOV
850 static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset)
851 {
852 struct pci_dn *pdn = pci_get_pdn(dev);
853 int i;
854 struct resource *res, res2;
855 resource_size_t size;
856 u16 num_vfs;
857
858 if (!dev->is_physfn)
859 return -EINVAL;
860
861 /*
862 * "offset" is in VFs. The M64 windows are sized so that when they
863 * are segmented, each segment is the same size as the IOV BAR.
864 * Each segment is in a separate PE, and the high order bits of the
865 * address are the PE number. Therefore, each VF's BAR is in a
866 * separate PE, and changing the IOV BAR start address changes the
867 * range of PEs the VFs are in.
868 */
869 num_vfs = pdn->num_vfs;
870 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
871 res = &dev->resource[i + PCI_IOV_RESOURCES];
872 if (!res->flags || !res->parent)
873 continue;
874
875 /*
876 * The actual IOV BAR range is determined by the start address
877 * and the actual size for num_vfs VFs BAR. This check is to
878 * make sure that after shifting, the range will not overlap
879 * with another device.
880 */
881 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
882 res2.flags = res->flags;
883 res2.start = res->start + (size * offset);
884 res2.end = res2.start + (size * num_vfs) - 1;
885
886 if (res2.end > res->end) {
887 dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n",
888 i, &res2, res, num_vfs, offset);
889 return -EBUSY;
890 }
891 }
892
893 /*
894 * After doing so, there would be a "hole" in the /proc/iomem when
895 * offset is a positive value. It looks like the device return some
896 * mmio back to the system, which actually no one could use it.
897 */
898 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
899 res = &dev->resource[i + PCI_IOV_RESOURCES];
900 if (!res->flags || !res->parent)
901 continue;
902
903 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
904 res2 = *res;
905 res->start += size * offset;
906
907 dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (%sabling %d VFs shifted by %d)\n",
908 i, &res2, res, (offset > 0) ? "En" : "Dis",
909 num_vfs, offset);
910 pci_update_resource(dev, i + PCI_IOV_RESOURCES);
911 }
912 return 0;
913 }
914 #endif /* CONFIG_PCI_IOV */
915
916 static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev)
917 {
918 struct pci_controller *hose = pci_bus_to_host(dev->bus);
919 struct pnv_phb *phb = hose->private_data;
920 struct pci_dn *pdn = pci_get_pdn(dev);
921 struct pnv_ioda_pe *pe;
922 int pe_num;
923
924 if (!pdn) {
925 pr_err("%s: Device tree node not associated properly\n",
926 pci_name(dev));
927 return NULL;
928 }
929 if (pdn->pe_number != IODA_INVALID_PE)
930 return NULL;
931
932 pe_num = pnv_ioda_alloc_pe(phb);
933 if (pe_num == IODA_INVALID_PE) {
934 pr_warning("%s: Not enough PE# available, disabling device\n",
935 pci_name(dev));
936 return NULL;
937 }
938
939 /* NOTE: We get only one ref to the pci_dev for the pdn, not for the
940 * pointer in the PE data structure, both should be destroyed at the
941 * same time. However, this needs to be looked at more closely again
942 * once we actually start removing things (Hotplug, SR-IOV, ...)
943 *
944 * At some point we want to remove the PDN completely anyways
945 */
946 pe = &phb->ioda.pe_array[pe_num];
947 pci_dev_get(dev);
948 pdn->pcidev = dev;
949 pdn->pe_number = pe_num;
950 pe->flags = PNV_IODA_PE_DEV;
951 pe->pdev = dev;
952 pe->pbus = NULL;
953 pe->tce32_seg = -1;
954 pe->mve_number = -1;
955 pe->rid = dev->bus->number << 8 | pdn->devfn;
956
957 pe_info(pe, "Associated device to PE\n");
958
959 if (pnv_ioda_configure_pe(phb, pe)) {
960 /* XXX What do we do here ? */
961 if (pe_num)
962 pnv_ioda_free_pe(phb, pe_num);
963 pdn->pe_number = IODA_INVALID_PE;
964 pe->pdev = NULL;
965 pci_dev_put(dev);
966 return NULL;
967 }
968
969 /* Assign a DMA weight to the device */
970 pe->dma_weight = pnv_ioda_dma_weight(dev);
971 if (pe->dma_weight != 0) {
972 phb->ioda.dma_weight += pe->dma_weight;
973 phb->ioda.dma_pe_count++;
974 }
975
976 /* Link the PE */
977 pnv_ioda_link_pe_by_weight(phb, pe);
978
979 return pe;
980 }
981
982 static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe)
983 {
984 struct pci_dev *dev;
985
986 list_for_each_entry(dev, &bus->devices, bus_list) {
987 struct pci_dn *pdn = pci_get_pdn(dev);
988
989 if (pdn == NULL) {
990 pr_warn("%s: No device node associated with device !\n",
991 pci_name(dev));
992 continue;
993 }
994 pdn->pcidev = dev;
995 pdn->pe_number = pe->pe_number;
996 pe->dma_weight += pnv_ioda_dma_weight(dev);
997 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
998 pnv_ioda_setup_same_PE(dev->subordinate, pe);
999 }
1000 }
1001
1002 /*
1003 * There're 2 types of PCI bus sensitive PEs: One that is compromised of
1004 * single PCI bus. Another one that contains the primary PCI bus and its
1005 * subordinate PCI devices and buses. The second type of PE is normally
1006 * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports.
1007 */
1008 static void pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all)
1009 {
1010 struct pci_controller *hose = pci_bus_to_host(bus);
1011 struct pnv_phb *phb = hose->private_data;
1012 struct pnv_ioda_pe *pe;
1013 int pe_num = IODA_INVALID_PE;
1014
1015 /* Check if PE is determined by M64 */
1016 if (phb->pick_m64_pe)
1017 pe_num = phb->pick_m64_pe(bus, all);
1018
1019 /* The PE number isn't pinned by M64 */
1020 if (pe_num == IODA_INVALID_PE)
1021 pe_num = pnv_ioda_alloc_pe(phb);
1022
1023 if (pe_num == IODA_INVALID_PE) {
1024 pr_warning("%s: Not enough PE# available for PCI bus %04x:%02x\n",
1025 __func__, pci_domain_nr(bus), bus->number);
1026 return;
1027 }
1028
1029 pe = &phb->ioda.pe_array[pe_num];
1030 pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS);
1031 pe->pbus = bus;
1032 pe->pdev = NULL;
1033 pe->tce32_seg = -1;
1034 pe->mve_number = -1;
1035 pe->rid = bus->busn_res.start << 8;
1036 pe->dma_weight = 0;
1037
1038 if (all)
1039 pe_info(pe, "Secondary bus %d..%d associated with PE#%d\n",
1040 bus->busn_res.start, bus->busn_res.end, pe_num);
1041 else
1042 pe_info(pe, "Secondary bus %d associated with PE#%d\n",
1043 bus->busn_res.start, pe_num);
1044
1045 if (pnv_ioda_configure_pe(phb, pe)) {
1046 /* XXX What do we do here ? */
1047 if (pe_num)
1048 pnv_ioda_free_pe(phb, pe_num);
1049 pe->pbus = NULL;
1050 return;
1051 }
1052
1053 /* Associate it with all child devices */
1054 pnv_ioda_setup_same_PE(bus, pe);
1055
1056 /* Put PE to the list */
1057 list_add_tail(&pe->list, &phb->ioda.pe_list);
1058
1059 /* Account for one DMA PE if at least one DMA capable device exist
1060 * below the bridge
1061 */
1062 if (pe->dma_weight != 0) {
1063 phb->ioda.dma_weight += pe->dma_weight;
1064 phb->ioda.dma_pe_count++;
1065 }
1066
1067 /* Link the PE */
1068 pnv_ioda_link_pe_by_weight(phb, pe);
1069 }
1070
1071 static struct pnv_ioda_pe *pnv_ioda_setup_npu_PE(struct pci_dev *npu_pdev)
1072 {
1073 int pe_num, found_pe = false, rc;
1074 long rid;
1075 struct pnv_ioda_pe *pe;
1076 struct pci_dev *gpu_pdev;
1077 struct pci_dn *npu_pdn;
1078 struct pci_controller *hose = pci_bus_to_host(npu_pdev->bus);
1079 struct pnv_phb *phb = hose->private_data;
1080
1081 /*
1082 * Due to a hardware errata PE#0 on the NPU is reserved for
1083 * error handling. This means we only have three PEs remaining
1084 * which need to be assigned to four links, implying some
1085 * links must share PEs.
1086 *
1087 * To achieve this we assign PEs such that NPUs linking the
1088 * same GPU get assigned the same PE.
1089 */
1090 gpu_pdev = pnv_pci_get_gpu_dev(npu_pdev);
1091 for (pe_num = 0; pe_num < phb->ioda.total_pe; pe_num++) {
1092 pe = &phb->ioda.pe_array[pe_num];
1093 if (!pe->pdev)
1094 continue;
1095
1096 if (pnv_pci_get_gpu_dev(pe->pdev) == gpu_pdev) {
1097 /*
1098 * This device has the same peer GPU so should
1099 * be assigned the same PE as the existing
1100 * peer NPU.
1101 */
1102 dev_info(&npu_pdev->dev,
1103 "Associating to existing PE %d\n", pe_num);
1104 pci_dev_get(npu_pdev);
1105 npu_pdn = pci_get_pdn(npu_pdev);
1106 rid = npu_pdev->bus->number << 8 | npu_pdn->devfn;
1107 npu_pdn->pcidev = npu_pdev;
1108 npu_pdn->pe_number = pe_num;
1109 pe->dma_weight += pnv_ioda_dma_weight(npu_pdev);
1110 phb->ioda.pe_rmap[rid] = pe->pe_number;
1111
1112 /* Map the PE to this link */
1113 rc = opal_pci_set_pe(phb->opal_id, pe_num, rid,
1114 OpalPciBusAll,
1115 OPAL_COMPARE_RID_DEVICE_NUMBER,
1116 OPAL_COMPARE_RID_FUNCTION_NUMBER,
1117 OPAL_MAP_PE);
1118 WARN_ON(rc != OPAL_SUCCESS);
1119 found_pe = true;
1120 break;
1121 }
1122 }
1123
1124 if (!found_pe)
1125 /*
1126 * Could not find an existing PE so allocate a new
1127 * one.
1128 */
1129 return pnv_ioda_setup_dev_PE(npu_pdev);
1130 else
1131 return pe;
1132 }
1133
1134 static void pnv_ioda_setup_npu_PEs(struct pci_bus *bus)
1135 {
1136 struct pci_dev *pdev;
1137
1138 list_for_each_entry(pdev, &bus->devices, bus_list)
1139 pnv_ioda_setup_npu_PE(pdev);
1140 }
1141
1142 static void pnv_ioda_setup_PEs(struct pci_bus *bus)
1143 {
1144 struct pci_dev *dev;
1145
1146 pnv_ioda_setup_bus_PE(bus, false);
1147
1148 list_for_each_entry(dev, &bus->devices, bus_list) {
1149 if (dev->subordinate) {
1150 if (pci_pcie_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE)
1151 pnv_ioda_setup_bus_PE(dev->subordinate, true);
1152 else
1153 pnv_ioda_setup_PEs(dev->subordinate);
1154 }
1155 }
1156 }
1157
1158 /*
1159 * Configure PEs so that the downstream PCI buses and devices
1160 * could have their associated PE#. Unfortunately, we didn't
1161 * figure out the way to identify the PLX bridge yet. So we
1162 * simply put the PCI bus and the subordinate behind the root
1163 * port to PE# here. The game rule here is expected to be changed
1164 * as soon as we can detected PLX bridge correctly.
1165 */
1166 static void pnv_pci_ioda_setup_PEs(void)
1167 {
1168 struct pci_controller *hose, *tmp;
1169 struct pnv_phb *phb;
1170
1171 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1172 phb = hose->private_data;
1173
1174 /* M64 layout might affect PE allocation */
1175 if (phb->reserve_m64_pe)
1176 phb->reserve_m64_pe(hose->bus, NULL, true);
1177
1178 /*
1179 * On NPU PHB, we expect separate PEs for individual PCI
1180 * functions. PCI bus dependent PEs are required for the
1181 * remaining types of PHBs.
1182 */
1183 if (phb->type == PNV_PHB_NPU) {
1184 /* PE#0 is needed for error reporting */
1185 pnv_ioda_reserve_pe(phb, 0);
1186 pnv_ioda_setup_npu_PEs(hose->bus);
1187 } else
1188 pnv_ioda_setup_PEs(hose->bus);
1189 }
1190 }
1191
1192 #ifdef CONFIG_PCI_IOV
1193 static int pnv_pci_vf_release_m64(struct pci_dev *pdev, u16 num_vfs)
1194 {
1195 struct pci_bus *bus;
1196 struct pci_controller *hose;
1197 struct pnv_phb *phb;
1198 struct pci_dn *pdn;
1199 int i, j;
1200 int m64_bars;
1201
1202 bus = pdev->bus;
1203 hose = pci_bus_to_host(bus);
1204 phb = hose->private_data;
1205 pdn = pci_get_pdn(pdev);
1206
1207 if (pdn->m64_single_mode)
1208 m64_bars = num_vfs;
1209 else
1210 m64_bars = 1;
1211
1212 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++)
1213 for (j = 0; j < m64_bars; j++) {
1214 if (pdn->m64_map[j][i] == IODA_INVALID_M64)
1215 continue;
1216 opal_pci_phb_mmio_enable(phb->opal_id,
1217 OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 0);
1218 clear_bit(pdn->m64_map[j][i], &phb->ioda.m64_bar_alloc);
1219 pdn->m64_map[j][i] = IODA_INVALID_M64;
1220 }
1221
1222 kfree(pdn->m64_map);
1223 return 0;
1224 }
1225
1226 static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs)
1227 {
1228 struct pci_bus *bus;
1229 struct pci_controller *hose;
1230 struct pnv_phb *phb;
1231 struct pci_dn *pdn;
1232 unsigned int win;
1233 struct resource *res;
1234 int i, j;
1235 int64_t rc;
1236 int total_vfs;
1237 resource_size_t size, start;
1238 int pe_num;
1239 int m64_bars;
1240
1241 bus = pdev->bus;
1242 hose = pci_bus_to_host(bus);
1243 phb = hose->private_data;
1244 pdn = pci_get_pdn(pdev);
1245 total_vfs = pci_sriov_get_totalvfs(pdev);
1246
1247 if (pdn->m64_single_mode)
1248 m64_bars = num_vfs;
1249 else
1250 m64_bars = 1;
1251
1252 pdn->m64_map = kmalloc(sizeof(*pdn->m64_map) * m64_bars, GFP_KERNEL);
1253 if (!pdn->m64_map)
1254 return -ENOMEM;
1255 /* Initialize the m64_map to IODA_INVALID_M64 */
1256 for (i = 0; i < m64_bars ; i++)
1257 for (j = 0; j < PCI_SRIOV_NUM_BARS; j++)
1258 pdn->m64_map[i][j] = IODA_INVALID_M64;
1259
1260
1261 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
1262 res = &pdev->resource[i + PCI_IOV_RESOURCES];
1263 if (!res->flags || !res->parent)
1264 continue;
1265
1266 for (j = 0; j < m64_bars; j++) {
1267 do {
1268 win = find_next_zero_bit(&phb->ioda.m64_bar_alloc,
1269 phb->ioda.m64_bar_idx + 1, 0);
1270
1271 if (win >= phb->ioda.m64_bar_idx + 1)
1272 goto m64_failed;
1273 } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc));
1274
1275 pdn->m64_map[j][i] = win;
1276
1277 if (pdn->m64_single_mode) {
1278 size = pci_iov_resource_size(pdev,
1279 PCI_IOV_RESOURCES + i);
1280 start = res->start + size * j;
1281 } else {
1282 size = resource_size(res);
1283 start = res->start;
1284 }
1285
1286 /* Map the M64 here */
1287 if (pdn->m64_single_mode) {
1288 pe_num = pdn->pe_num_map[j];
1289 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
1290 pe_num, OPAL_M64_WINDOW_TYPE,
1291 pdn->m64_map[j][i], 0);
1292 }
1293
1294 rc = opal_pci_set_phb_mem_window(phb->opal_id,
1295 OPAL_M64_WINDOW_TYPE,
1296 pdn->m64_map[j][i],
1297 start,
1298 0, /* unused */
1299 size);
1300
1301
1302 if (rc != OPAL_SUCCESS) {
1303 dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n",
1304 win, rc);
1305 goto m64_failed;
1306 }
1307
1308 if (pdn->m64_single_mode)
1309 rc = opal_pci_phb_mmio_enable(phb->opal_id,
1310 OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 2);
1311 else
1312 rc = opal_pci_phb_mmio_enable(phb->opal_id,
1313 OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 1);
1314
1315 if (rc != OPAL_SUCCESS) {
1316 dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n",
1317 win, rc);
1318 goto m64_failed;
1319 }
1320 }
1321 }
1322 return 0;
1323
1324 m64_failed:
1325 pnv_pci_vf_release_m64(pdev, num_vfs);
1326 return -EBUSY;
1327 }
1328
1329 static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group,
1330 int num);
1331 static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable);
1332
1333 static void pnv_pci_ioda2_release_dma_pe(struct pci_dev *dev, struct pnv_ioda_pe *pe)
1334 {
1335 struct iommu_table *tbl;
1336 int64_t rc;
1337
1338 tbl = pe->table_group.tables[0];
1339 rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0);
1340 if (rc)
1341 pe_warn(pe, "OPAL error %ld release DMA window\n", rc);
1342
1343 pnv_pci_ioda2_set_bypass(pe, false);
1344 if (pe->table_group.group) {
1345 iommu_group_put(pe->table_group.group);
1346 BUG_ON(pe->table_group.group);
1347 }
1348 pnv_pci_ioda2_table_free_pages(tbl);
1349 iommu_free_table(tbl, of_node_full_name(dev->dev.of_node));
1350 }
1351
1352 static void pnv_ioda_release_vf_PE(struct pci_dev *pdev)
1353 {
1354 struct pci_bus *bus;
1355 struct pci_controller *hose;
1356 struct pnv_phb *phb;
1357 struct pnv_ioda_pe *pe, *pe_n;
1358 struct pci_dn *pdn;
1359
1360 bus = pdev->bus;
1361 hose = pci_bus_to_host(bus);
1362 phb = hose->private_data;
1363 pdn = pci_get_pdn(pdev);
1364
1365 if (!pdev->is_physfn)
1366 return;
1367
1368 list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) {
1369 if (pe->parent_dev != pdev)
1370 continue;
1371
1372 pnv_pci_ioda2_release_dma_pe(pdev, pe);
1373
1374 /* Remove from list */
1375 mutex_lock(&phb->ioda.pe_list_mutex);
1376 list_del(&pe->list);
1377 mutex_unlock(&phb->ioda.pe_list_mutex);
1378
1379 pnv_ioda_deconfigure_pe(phb, pe);
1380
1381 pnv_ioda_free_pe(phb, pe->pe_number);
1382 }
1383 }
1384
1385 void pnv_pci_sriov_disable(struct pci_dev *pdev)
1386 {
1387 struct pci_bus *bus;
1388 struct pci_controller *hose;
1389 struct pnv_phb *phb;
1390 struct pci_dn *pdn;
1391 struct pci_sriov *iov;
1392 u16 num_vfs, i;
1393
1394 bus = pdev->bus;
1395 hose = pci_bus_to_host(bus);
1396 phb = hose->private_data;
1397 pdn = pci_get_pdn(pdev);
1398 iov = pdev->sriov;
1399 num_vfs = pdn->num_vfs;
1400
1401 /* Release VF PEs */
1402 pnv_ioda_release_vf_PE(pdev);
1403
1404 if (phb->type == PNV_PHB_IODA2) {
1405 if (!pdn->m64_single_mode)
1406 pnv_pci_vf_resource_shift(pdev, -*pdn->pe_num_map);
1407
1408 /* Release M64 windows */
1409 pnv_pci_vf_release_m64(pdev, num_vfs);
1410
1411 /* Release PE numbers */
1412 if (pdn->m64_single_mode) {
1413 for (i = 0; i < num_vfs; i++) {
1414 if (pdn->pe_num_map[i] != IODA_INVALID_PE)
1415 pnv_ioda_free_pe(phb, pdn->pe_num_map[i]);
1416 }
1417 } else
1418 bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1419 /* Releasing pe_num_map */
1420 kfree(pdn->pe_num_map);
1421 }
1422 }
1423
1424 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
1425 struct pnv_ioda_pe *pe);
1426 static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs)
1427 {
1428 struct pci_bus *bus;
1429 struct pci_controller *hose;
1430 struct pnv_phb *phb;
1431 struct pnv_ioda_pe *pe;
1432 int pe_num;
1433 u16 vf_index;
1434 struct pci_dn *pdn;
1435
1436 bus = pdev->bus;
1437 hose = pci_bus_to_host(bus);
1438 phb = hose->private_data;
1439 pdn = pci_get_pdn(pdev);
1440
1441 if (!pdev->is_physfn)
1442 return;
1443
1444 /* Reserve PE for each VF */
1445 for (vf_index = 0; vf_index < num_vfs; vf_index++) {
1446 if (pdn->m64_single_mode)
1447 pe_num = pdn->pe_num_map[vf_index];
1448 else
1449 pe_num = *pdn->pe_num_map + vf_index;
1450
1451 pe = &phb->ioda.pe_array[pe_num];
1452 pe->pe_number = pe_num;
1453 pe->phb = phb;
1454 pe->flags = PNV_IODA_PE_VF;
1455 pe->pbus = NULL;
1456 pe->parent_dev = pdev;
1457 pe->tce32_seg = -1;
1458 pe->mve_number = -1;
1459 pe->rid = (pci_iov_virtfn_bus(pdev, vf_index) << 8) |
1460 pci_iov_virtfn_devfn(pdev, vf_index);
1461
1462 pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%d\n",
1463 hose->global_number, pdev->bus->number,
1464 PCI_SLOT(pci_iov_virtfn_devfn(pdev, vf_index)),
1465 PCI_FUNC(pci_iov_virtfn_devfn(pdev, vf_index)), pe_num);
1466
1467 if (pnv_ioda_configure_pe(phb, pe)) {
1468 /* XXX What do we do here ? */
1469 if (pe_num)
1470 pnv_ioda_free_pe(phb, pe_num);
1471 pe->pdev = NULL;
1472 continue;
1473 }
1474
1475 /* Put PE to the list */
1476 mutex_lock(&phb->ioda.pe_list_mutex);
1477 list_add_tail(&pe->list, &phb->ioda.pe_list);
1478 mutex_unlock(&phb->ioda.pe_list_mutex);
1479
1480 pnv_pci_ioda2_setup_dma_pe(phb, pe);
1481 }
1482 }
1483
1484 int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
1485 {
1486 struct pci_bus *bus;
1487 struct pci_controller *hose;
1488 struct pnv_phb *phb;
1489 struct pci_dn *pdn;
1490 int ret;
1491 u16 i;
1492
1493 bus = pdev->bus;
1494 hose = pci_bus_to_host(bus);
1495 phb = hose->private_data;
1496 pdn = pci_get_pdn(pdev);
1497
1498 if (phb->type == PNV_PHB_IODA2) {
1499 if (!pdn->vfs_expanded) {
1500 dev_info(&pdev->dev, "don't support this SRIOV device"
1501 " with non 64bit-prefetchable IOV BAR\n");
1502 return -ENOSPC;
1503 }
1504
1505 /*
1506 * When M64 BARs functions in Single PE mode, the number of VFs
1507 * could be enabled must be less than the number of M64 BARs.
1508 */
1509 if (pdn->m64_single_mode && num_vfs > phb->ioda.m64_bar_idx) {
1510 dev_info(&pdev->dev, "Not enough M64 BAR for VFs\n");
1511 return -EBUSY;
1512 }
1513
1514 /* Allocating pe_num_map */
1515 if (pdn->m64_single_mode)
1516 pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map) * num_vfs,
1517 GFP_KERNEL);
1518 else
1519 pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map), GFP_KERNEL);
1520
1521 if (!pdn->pe_num_map)
1522 return -ENOMEM;
1523
1524 if (pdn->m64_single_mode)
1525 for (i = 0; i < num_vfs; i++)
1526 pdn->pe_num_map[i] = IODA_INVALID_PE;
1527
1528 /* Calculate available PE for required VFs */
1529 if (pdn->m64_single_mode) {
1530 for (i = 0; i < num_vfs; i++) {
1531 pdn->pe_num_map[i] = pnv_ioda_alloc_pe(phb);
1532 if (pdn->pe_num_map[i] == IODA_INVALID_PE) {
1533 ret = -EBUSY;
1534 goto m64_failed;
1535 }
1536 }
1537 } else {
1538 mutex_lock(&phb->ioda.pe_alloc_mutex);
1539 *pdn->pe_num_map = bitmap_find_next_zero_area(
1540 phb->ioda.pe_alloc, phb->ioda.total_pe,
1541 0, num_vfs, 0);
1542 if (*pdn->pe_num_map >= phb->ioda.total_pe) {
1543 mutex_unlock(&phb->ioda.pe_alloc_mutex);
1544 dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs);
1545 kfree(pdn->pe_num_map);
1546 return -EBUSY;
1547 }
1548 bitmap_set(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1549 mutex_unlock(&phb->ioda.pe_alloc_mutex);
1550 }
1551 pdn->num_vfs = num_vfs;
1552
1553 /* Assign M64 window accordingly */
1554 ret = pnv_pci_vf_assign_m64(pdev, num_vfs);
1555 if (ret) {
1556 dev_info(&pdev->dev, "Not enough M64 window resources\n");
1557 goto m64_failed;
1558 }
1559
1560 /*
1561 * When using one M64 BAR to map one IOV BAR, we need to shift
1562 * the IOV BAR according to the PE# allocated to the VFs.
1563 * Otherwise, the PE# for the VF will conflict with others.
1564 */
1565 if (!pdn->m64_single_mode) {
1566 ret = pnv_pci_vf_resource_shift(pdev, *pdn->pe_num_map);
1567 if (ret)
1568 goto m64_failed;
1569 }
1570 }
1571
1572 /* Setup VF PEs */
1573 pnv_ioda_setup_vf_PE(pdev, num_vfs);
1574
1575 return 0;
1576
1577 m64_failed:
1578 if (pdn->m64_single_mode) {
1579 for (i = 0; i < num_vfs; i++) {
1580 if (pdn->pe_num_map[i] != IODA_INVALID_PE)
1581 pnv_ioda_free_pe(phb, pdn->pe_num_map[i]);
1582 }
1583 } else
1584 bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1585
1586 /* Releasing pe_num_map */
1587 kfree(pdn->pe_num_map);
1588
1589 return ret;
1590 }
1591
1592 int pcibios_sriov_disable(struct pci_dev *pdev)
1593 {
1594 pnv_pci_sriov_disable(pdev);
1595
1596 /* Release PCI data */
1597 remove_dev_pci_data(pdev);
1598 return 0;
1599 }
1600
1601 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
1602 {
1603 /* Allocate PCI data */
1604 add_dev_pci_data(pdev);
1605
1606 return pnv_pci_sriov_enable(pdev, num_vfs);
1607 }
1608 #endif /* CONFIG_PCI_IOV */
1609
1610 static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev)
1611 {
1612 struct pci_dn *pdn = pci_get_pdn(pdev);
1613 struct pnv_ioda_pe *pe;
1614
1615 /*
1616 * The function can be called while the PE#
1617 * hasn't been assigned. Do nothing for the
1618 * case.
1619 */
1620 if (!pdn || pdn->pe_number == IODA_INVALID_PE)
1621 return;
1622
1623 pe = &phb->ioda.pe_array[pdn->pe_number];
1624 WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops);
1625 set_dma_offset(&pdev->dev, pe->tce_bypass_base);
1626 set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]);
1627 /*
1628 * Note: iommu_add_device() will fail here as
1629 * for physical PE: the device is already added by now;
1630 * for virtual PE: sysfs entries are not ready yet and
1631 * tce_iommu_bus_notifier will add the device to a group later.
1632 */
1633 }
1634
1635 static int pnv_pci_ioda_dma_set_mask(struct pci_dev *pdev, u64 dma_mask)
1636 {
1637 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
1638 struct pnv_phb *phb = hose->private_data;
1639 struct pci_dn *pdn = pci_get_pdn(pdev);
1640 struct pnv_ioda_pe *pe;
1641 uint64_t top;
1642 bool bypass = false;
1643 struct pci_dev *linked_npu_dev;
1644 int i;
1645
1646 if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
1647 return -ENODEV;;
1648
1649 pe = &phb->ioda.pe_array[pdn->pe_number];
1650 if (pe->tce_bypass_enabled) {
1651 top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1;
1652 bypass = (dma_mask >= top);
1653 }
1654
1655 if (bypass) {
1656 dev_info(&pdev->dev, "Using 64-bit DMA iommu bypass\n");
1657 set_dma_ops(&pdev->dev, &dma_direct_ops);
1658 } else {
1659 dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n");
1660 set_dma_ops(&pdev->dev, &dma_iommu_ops);
1661 }
1662 *pdev->dev.dma_mask = dma_mask;
1663
1664 /* Update peer npu devices */
1665 if (pe->flags & PNV_IODA_PE_PEER)
1666 for (i = 0; i < PNV_IODA_MAX_PEER_PES; i++) {
1667 if (!pe->peers[i])
1668 continue;
1669
1670 linked_npu_dev = pe->peers[i]->pdev;
1671 if (dma_get_mask(&linked_npu_dev->dev) != dma_mask)
1672 dma_set_mask(&linked_npu_dev->dev, dma_mask);
1673 }
1674
1675 return 0;
1676 }
1677
1678 static u64 pnv_pci_ioda_dma_get_required_mask(struct pci_dev *pdev)
1679 {
1680 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
1681 struct pnv_phb *phb = hose->private_data;
1682 struct pci_dn *pdn = pci_get_pdn(pdev);
1683 struct pnv_ioda_pe *pe;
1684 u64 end, mask;
1685
1686 if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
1687 return 0;
1688
1689 pe = &phb->ioda.pe_array[pdn->pe_number];
1690 if (!pe->tce_bypass_enabled)
1691 return __dma_get_required_mask(&pdev->dev);
1692
1693
1694 end = pe->tce_bypass_base + memblock_end_of_DRAM();
1695 mask = 1ULL << (fls64(end) - 1);
1696 mask += mask - 1;
1697
1698 return mask;
1699 }
1700
1701 static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe,
1702 struct pci_bus *bus)
1703 {
1704 struct pci_dev *dev;
1705
1706 list_for_each_entry(dev, &bus->devices, bus_list) {
1707 set_iommu_table_base(&dev->dev, pe->table_group.tables[0]);
1708 set_dma_offset(&dev->dev, pe->tce_bypass_base);
1709 iommu_add_device(&dev->dev);
1710
1711 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
1712 pnv_ioda_setup_bus_dma(pe, dev->subordinate);
1713 }
1714 }
1715
1716 static void pnv_pci_ioda1_tce_invalidate(struct iommu_table *tbl,
1717 unsigned long index, unsigned long npages, bool rm)
1718 {
1719 struct iommu_table_group_link *tgl = list_first_entry_or_null(
1720 &tbl->it_group_list, struct iommu_table_group_link,
1721 next);
1722 struct pnv_ioda_pe *pe = container_of(tgl->table_group,
1723 struct pnv_ioda_pe, table_group);
1724 __be64 __iomem *invalidate = rm ?
1725 (__be64 __iomem *)pe->phb->ioda.tce_inval_reg_phys :
1726 pe->phb->ioda.tce_inval_reg;
1727 unsigned long start, end, inc;
1728 const unsigned shift = tbl->it_page_shift;
1729
1730 start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset);
1731 end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset +
1732 npages - 1);
1733
1734 /* BML uses this case for p6/p7/galaxy2: Shift addr and put in node */
1735 if (tbl->it_busno) {
1736 start <<= shift;
1737 end <<= shift;
1738 inc = 128ull << shift;
1739 start |= tbl->it_busno;
1740 end |= tbl->it_busno;
1741 } else if (tbl->it_type & TCE_PCI_SWINV_PAIR) {
1742 /* p7ioc-style invalidation, 2 TCEs per write */
1743 start |= (1ull << 63);
1744 end |= (1ull << 63);
1745 inc = 16;
1746 } else {
1747 /* Default (older HW) */
1748 inc = 128;
1749 }
1750
1751 end |= inc - 1; /* round up end to be different than start */
1752
1753 mb(); /* Ensure above stores are visible */
1754 while (start <= end) {
1755 if (rm)
1756 __raw_rm_writeq(cpu_to_be64(start), invalidate);
1757 else
1758 __raw_writeq(cpu_to_be64(start), invalidate);
1759 start += inc;
1760 }
1761
1762 /*
1763 * The iommu layer will do another mb() for us on build()
1764 * and we don't care on free()
1765 */
1766 }
1767
1768 static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index,
1769 long npages, unsigned long uaddr,
1770 enum dma_data_direction direction,
1771 struct dma_attrs *attrs)
1772 {
1773 int ret = pnv_tce_build(tbl, index, npages, uaddr, direction,
1774 attrs);
1775
1776 if (!ret && (tbl->it_type & TCE_PCI_SWINV_CREATE))
1777 pnv_pci_ioda1_tce_invalidate(tbl, index, npages, false);
1778
1779 return ret;
1780 }
1781
1782 #ifdef CONFIG_IOMMU_API
1783 static int pnv_ioda1_tce_xchg(struct iommu_table *tbl, long index,
1784 unsigned long *hpa, enum dma_data_direction *direction)
1785 {
1786 long ret = pnv_tce_xchg(tbl, index, hpa, direction);
1787
1788 if (!ret && (tbl->it_type &
1789 (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE)))
1790 pnv_pci_ioda1_tce_invalidate(tbl, index, 1, false);
1791
1792 return ret;
1793 }
1794 #endif
1795
1796 static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index,
1797 long npages)
1798 {
1799 pnv_tce_free(tbl, index, npages);
1800
1801 if (tbl->it_type & TCE_PCI_SWINV_FREE)
1802 pnv_pci_ioda1_tce_invalidate(tbl, index, npages, false);
1803 }
1804
1805 static struct iommu_table_ops pnv_ioda1_iommu_ops = {
1806 .set = pnv_ioda1_tce_build,
1807 #ifdef CONFIG_IOMMU_API
1808 .exchange = pnv_ioda1_tce_xchg,
1809 #endif
1810 .clear = pnv_ioda1_tce_free,
1811 .get = pnv_tce_get,
1812 };
1813
1814 static inline void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_ioda_pe *pe)
1815 {
1816 /* 01xb - invalidate TCEs that match the specified PE# */
1817 unsigned long val = (0x4ull << 60) | (pe->pe_number & 0xFF);
1818 struct pnv_phb *phb = pe->phb;
1819 struct pnv_ioda_pe *npe;
1820 int i;
1821
1822 if (!phb->ioda.tce_inval_reg)
1823 return;
1824
1825 mb(); /* Ensure above stores are visible */
1826 __raw_writeq(cpu_to_be64(val), phb->ioda.tce_inval_reg);
1827
1828 if (pe->flags & PNV_IODA_PE_PEER)
1829 for (i = 0; i < PNV_IODA_MAX_PEER_PES; i++) {
1830 npe = pe->peers[i];
1831 if (!npe || npe->phb->type != PNV_PHB_NPU)
1832 continue;
1833
1834 pnv_npu_tce_invalidate_entire(npe);
1835 }
1836 }
1837
1838 static void pnv_pci_ioda2_do_tce_invalidate(unsigned pe_number, bool rm,
1839 __be64 __iomem *invalidate, unsigned shift,
1840 unsigned long index, unsigned long npages)
1841 {
1842 unsigned long start, end, inc;
1843
1844 /* We'll invalidate DMA address in PE scope */
1845 start = 0x2ull << 60;
1846 start |= (pe_number & 0xFF);
1847 end = start;
1848
1849 /* Figure out the start, end and step */
1850 start |= (index << shift);
1851 end |= ((index + npages - 1) << shift);
1852 inc = (0x1ull << shift);
1853 mb();
1854
1855 while (start <= end) {
1856 if (rm)
1857 __raw_rm_writeq(cpu_to_be64(start), invalidate);
1858 else
1859 __raw_writeq(cpu_to_be64(start), invalidate);
1860 start += inc;
1861 }
1862 }
1863
1864 static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl,
1865 unsigned long index, unsigned long npages, bool rm)
1866 {
1867 struct iommu_table_group_link *tgl;
1868
1869 list_for_each_entry_rcu(tgl, &tbl->it_group_list, next) {
1870 struct pnv_ioda_pe *npe;
1871 struct pnv_ioda_pe *pe = container_of(tgl->table_group,
1872 struct pnv_ioda_pe, table_group);
1873 __be64 __iomem *invalidate = rm ?
1874 (__be64 __iomem *)pe->phb->ioda.tce_inval_reg_phys :
1875 pe->phb->ioda.tce_inval_reg;
1876 int i;
1877
1878 pnv_pci_ioda2_do_tce_invalidate(pe->pe_number, rm,
1879 invalidate, tbl->it_page_shift,
1880 index, npages);
1881
1882 if (pe->flags & PNV_IODA_PE_PEER)
1883 /* Invalidate PEs using the same TCE table */
1884 for (i = 0; i < PNV_IODA_MAX_PEER_PES; i++) {
1885 npe = pe->peers[i];
1886 if (!npe || npe->phb->type != PNV_PHB_NPU)
1887 continue;
1888
1889 pnv_npu_tce_invalidate(npe, tbl, index,
1890 npages, rm);
1891 }
1892 }
1893 }
1894
1895 static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index,
1896 long npages, unsigned long uaddr,
1897 enum dma_data_direction direction,
1898 struct dma_attrs *attrs)
1899 {
1900 int ret = pnv_tce_build(tbl, index, npages, uaddr, direction,
1901 attrs);
1902
1903 if (!ret && (tbl->it_type & TCE_PCI_SWINV_CREATE))
1904 pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false);
1905
1906 return ret;
1907 }
1908
1909 #ifdef CONFIG_IOMMU_API
1910 static int pnv_ioda2_tce_xchg(struct iommu_table *tbl, long index,
1911 unsigned long *hpa, enum dma_data_direction *direction)
1912 {
1913 long ret = pnv_tce_xchg(tbl, index, hpa, direction);
1914
1915 if (!ret && (tbl->it_type &
1916 (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE)))
1917 pnv_pci_ioda2_tce_invalidate(tbl, index, 1, false);
1918
1919 return ret;
1920 }
1921 #endif
1922
1923 static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index,
1924 long npages)
1925 {
1926 pnv_tce_free(tbl, index, npages);
1927
1928 if (tbl->it_type & TCE_PCI_SWINV_FREE)
1929 pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false);
1930 }
1931
1932 static void pnv_ioda2_table_free(struct iommu_table *tbl)
1933 {
1934 pnv_pci_ioda2_table_free_pages(tbl);
1935 iommu_free_table(tbl, "pnv");
1936 }
1937
1938 static struct iommu_table_ops pnv_ioda2_iommu_ops = {
1939 .set = pnv_ioda2_tce_build,
1940 #ifdef CONFIG_IOMMU_API
1941 .exchange = pnv_ioda2_tce_xchg,
1942 #endif
1943 .clear = pnv_ioda2_tce_free,
1944 .get = pnv_tce_get,
1945 .free = pnv_ioda2_table_free,
1946 };
1947
1948 static void pnv_pci_ioda_setup_dma_pe(struct pnv_phb *phb,
1949 struct pnv_ioda_pe *pe, unsigned int base,
1950 unsigned int segs)
1951 {
1952
1953 struct page *tce_mem = NULL;
1954 struct iommu_table *tbl;
1955 unsigned int i;
1956 int64_t rc;
1957 void *addr;
1958
1959 /* XXX FIXME: Handle 64-bit only DMA devices */
1960 /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */
1961 /* XXX FIXME: Allocate multi-level tables on PHB3 */
1962
1963 /* We shouldn't already have a 32-bit DMA associated */
1964 if (WARN_ON(pe->tce32_seg >= 0))
1965 return;
1966
1967 tbl = pnv_pci_table_alloc(phb->hose->node);
1968 iommu_register_group(&pe->table_group, phb->hose->global_number,
1969 pe->pe_number);
1970 pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group);
1971
1972 /* Grab a 32-bit TCE table */
1973 pe->tce32_seg = base;
1974 pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n",
1975 (base << 28), ((base + segs) << 28) - 1);
1976
1977 /* XXX Currently, we allocate one big contiguous table for the
1978 * TCEs. We only really need one chunk per 256M of TCE space
1979 * (ie per segment) but that's an optimization for later, it
1980 * requires some added smarts with our get/put_tce implementation
1981 */
1982 tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL,
1983 get_order(TCE32_TABLE_SIZE * segs));
1984 if (!tce_mem) {
1985 pe_err(pe, " Failed to allocate a 32-bit TCE memory\n");
1986 goto fail;
1987 }
1988 addr = page_address(tce_mem);
1989 memset(addr, 0, TCE32_TABLE_SIZE * segs);
1990
1991 /* Configure HW */
1992 for (i = 0; i < segs; i++) {
1993 rc = opal_pci_map_pe_dma_window(phb->opal_id,
1994 pe->pe_number,
1995 base + i, 1,
1996 __pa(addr) + TCE32_TABLE_SIZE * i,
1997 TCE32_TABLE_SIZE, 0x1000);
1998 if (rc) {
1999 pe_err(pe, " Failed to configure 32-bit TCE table,"
2000 " err %ld\n", rc);
2001 goto fail;
2002 }
2003 }
2004
2005 /* Setup linux iommu table */
2006 pnv_pci_setup_iommu_table(tbl, addr, TCE32_TABLE_SIZE * segs,
2007 base << 28, IOMMU_PAGE_SHIFT_4K);
2008
2009 /* OPAL variant of P7IOC SW invalidated TCEs */
2010 if (phb->ioda.tce_inval_reg)
2011 tbl->it_type |= (TCE_PCI_SWINV_CREATE |
2012 TCE_PCI_SWINV_FREE |
2013 TCE_PCI_SWINV_PAIR);
2014
2015 tbl->it_ops = &pnv_ioda1_iommu_ops;
2016 pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift;
2017 pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift;
2018 iommu_init_table(tbl, phb->hose->node);
2019
2020 if (pe->flags & PNV_IODA_PE_DEV) {
2021 /*
2022 * Setting table base here only for carrying iommu_group
2023 * further down to let iommu_add_device() do the job.
2024 * pnv_pci_ioda_dma_dev_setup will override it later anyway.
2025 */
2026 set_iommu_table_base(&pe->pdev->dev, tbl);
2027 iommu_add_device(&pe->pdev->dev);
2028 } else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
2029 pnv_ioda_setup_bus_dma(pe, pe->pbus);
2030
2031 return;
2032 fail:
2033 /* XXX Failure: Try to fallback to 64-bit only ? */
2034 if (pe->tce32_seg >= 0)
2035 pe->tce32_seg = -1;
2036 if (tce_mem)
2037 __free_pages(tce_mem, get_order(TCE32_TABLE_SIZE * segs));
2038 if (tbl) {
2039 pnv_pci_unlink_table_and_group(tbl, &pe->table_group);
2040 iommu_free_table(tbl, "pnv");
2041 }
2042 }
2043
2044 static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group,
2045 int num, struct iommu_table *tbl)
2046 {
2047 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2048 table_group);
2049 struct pnv_phb *phb = pe->phb;
2050 int64_t rc;
2051 const unsigned long size = tbl->it_indirect_levels ?
2052 tbl->it_level_size : tbl->it_size;
2053 const __u64 start_addr = tbl->it_offset << tbl->it_page_shift;
2054 const __u64 win_size = tbl->it_size << tbl->it_page_shift;
2055
2056 pe_info(pe, "Setting up window#%d %llx..%llx pg=%x\n", num,
2057 start_addr, start_addr + win_size - 1,
2058 IOMMU_PAGE_SIZE(tbl));
2059
2060 /*
2061 * Map TCE table through TVT. The TVE index is the PE number
2062 * shifted by 1 bit for 32-bits DMA space.
2063 */
2064 rc = opal_pci_map_pe_dma_window(phb->opal_id,
2065 pe->pe_number,
2066 (pe->pe_number << 1) + num,
2067 tbl->it_indirect_levels + 1,
2068 __pa(tbl->it_base),
2069 size << 3,
2070 IOMMU_PAGE_SIZE(tbl));
2071 if (rc) {
2072 pe_err(pe, "Failed to configure TCE table, err %ld\n", rc);
2073 return rc;
2074 }
2075
2076 pnv_pci_link_table_and_group(phb->hose->node, num,
2077 tbl, &pe->table_group);
2078 pnv_pci_ioda2_tce_invalidate_entire(pe);
2079
2080 return 0;
2081 }
2082
2083 static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable)
2084 {
2085 uint16_t window_id = (pe->pe_number << 1 ) + 1;
2086 int64_t rc;
2087
2088 pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis");
2089 if (enable) {
2090 phys_addr_t top = memblock_end_of_DRAM();
2091
2092 top = roundup_pow_of_two(top);
2093 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
2094 pe->pe_number,
2095 window_id,
2096 pe->tce_bypass_base,
2097 top);
2098 } else {
2099 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
2100 pe->pe_number,
2101 window_id,
2102 pe->tce_bypass_base,
2103 0);
2104 }
2105 if (rc)
2106 pe_err(pe, "OPAL error %lld configuring bypass window\n", rc);
2107 else
2108 pe->tce_bypass_enabled = enable;
2109 }
2110
2111 static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset,
2112 __u32 page_shift, __u64 window_size, __u32 levels,
2113 struct iommu_table *tbl);
2114
2115 static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group,
2116 int num, __u32 page_shift, __u64 window_size, __u32 levels,
2117 struct iommu_table **ptbl)
2118 {
2119 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2120 table_group);
2121 int nid = pe->phb->hose->node;
2122 __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start;
2123 long ret;
2124 struct iommu_table *tbl;
2125
2126 tbl = pnv_pci_table_alloc(nid);
2127 if (!tbl)
2128 return -ENOMEM;
2129
2130 ret = pnv_pci_ioda2_table_alloc_pages(nid,
2131 bus_offset, page_shift, window_size,
2132 levels, tbl);
2133 if (ret) {
2134 iommu_free_table(tbl, "pnv");
2135 return ret;
2136 }
2137
2138 tbl->it_ops = &pnv_ioda2_iommu_ops;
2139 if (pe->phb->ioda.tce_inval_reg)
2140 tbl->it_type |= (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE);
2141
2142 *ptbl = tbl;
2143
2144 return 0;
2145 }
2146
2147 static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe)
2148 {
2149 struct iommu_table *tbl = NULL;
2150 long rc;
2151
2152 /*
2153 * crashkernel= specifies the kdump kernel's maximum memory at
2154 * some offset and there is no guaranteed the result is a power
2155 * of 2, which will cause errors later.
2156 */
2157 const u64 max_memory = __rounddown_pow_of_two(memory_hotplug_max());
2158
2159 /*
2160 * In memory constrained environments, e.g. kdump kernel, the
2161 * DMA window can be larger than available memory, which will
2162 * cause errors later.
2163 */
2164 const u64 window_size = min((u64)pe->table_group.tce32_size, max_memory);
2165
2166 rc = pnv_pci_ioda2_create_table(&pe->table_group, 0,
2167 IOMMU_PAGE_SHIFT_4K,
2168 window_size,
2169 POWERNV_IOMMU_DEFAULT_LEVELS, &tbl);
2170 if (rc) {
2171 pe_err(pe, "Failed to create 32-bit TCE table, err %ld",
2172 rc);
2173 return rc;
2174 }
2175
2176 iommu_init_table(tbl, pe->phb->hose->node);
2177
2178 rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl);
2179 if (rc) {
2180 pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n",
2181 rc);
2182 pnv_ioda2_table_free(tbl);
2183 return rc;
2184 }
2185
2186 if (!pnv_iommu_bypass_disabled)
2187 pnv_pci_ioda2_set_bypass(pe, true);
2188
2189 /* OPAL variant of PHB3 invalidated TCEs */
2190 if (pe->phb->ioda.tce_inval_reg)
2191 tbl->it_type |= (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE);
2192
2193 /*
2194 * Setting table base here only for carrying iommu_group
2195 * further down to let iommu_add_device() do the job.
2196 * pnv_pci_ioda_dma_dev_setup will override it later anyway.
2197 */
2198 if (pe->flags & PNV_IODA_PE_DEV)
2199 set_iommu_table_base(&pe->pdev->dev, tbl);
2200
2201 return 0;
2202 }
2203
2204 #if defined(CONFIG_IOMMU_API) || defined(CONFIG_PCI_IOV)
2205 static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group,
2206 int num)
2207 {
2208 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2209 table_group);
2210 struct pnv_phb *phb = pe->phb;
2211 long ret;
2212
2213 pe_info(pe, "Removing DMA window #%d\n", num);
2214
2215 ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
2216 (pe->pe_number << 1) + num,
2217 0/* levels */, 0/* table address */,
2218 0/* table size */, 0/* page size */);
2219 if (ret)
2220 pe_warn(pe, "Unmapping failed, ret = %ld\n", ret);
2221 else
2222 pnv_pci_ioda2_tce_invalidate_entire(pe);
2223
2224 pnv_pci_unlink_table_and_group(table_group->tables[num], table_group);
2225
2226 return ret;
2227 }
2228 #endif
2229
2230 #ifdef CONFIG_IOMMU_API
2231 static unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift,
2232 __u64 window_size, __u32 levels)
2233 {
2234 unsigned long bytes = 0;
2235 const unsigned window_shift = ilog2(window_size);
2236 unsigned entries_shift = window_shift - page_shift;
2237 unsigned table_shift = entries_shift + 3;
2238 unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift);
2239 unsigned long direct_table_size;
2240
2241 if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) ||
2242 (window_size > memory_hotplug_max()) ||
2243 !is_power_of_2(window_size))
2244 return 0;
2245
2246 /* Calculate a direct table size from window_size and levels */
2247 entries_shift = (entries_shift + levels - 1) / levels;
2248 table_shift = entries_shift + 3;
2249 table_shift = max_t(unsigned, table_shift, PAGE_SHIFT);
2250 direct_table_size = 1UL << table_shift;
2251
2252 for ( ; levels; --levels) {
2253 bytes += _ALIGN_UP(tce_table_size, direct_table_size);
2254
2255 tce_table_size /= direct_table_size;
2256 tce_table_size <<= 3;
2257 tce_table_size = _ALIGN_UP(tce_table_size, direct_table_size);
2258 }
2259
2260 return bytes;
2261 }
2262
2263 static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group)
2264 {
2265 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2266 table_group);
2267 /* Store @tbl as pnv_pci_ioda2_unset_window() resets it */
2268 struct iommu_table *tbl = pe->table_group.tables[0];
2269
2270 pnv_pci_ioda2_set_bypass(pe, false);
2271 pnv_pci_ioda2_unset_window(&pe->table_group, 0);
2272 pnv_ioda2_table_free(tbl);
2273 }
2274
2275 static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group)
2276 {
2277 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2278 table_group);
2279
2280 pnv_pci_ioda2_setup_default_config(pe);
2281 }
2282
2283 static struct iommu_table_group_ops pnv_pci_ioda2_ops = {
2284 .get_table_size = pnv_pci_ioda2_get_table_size,
2285 .create_table = pnv_pci_ioda2_create_table,
2286 .set_window = pnv_pci_ioda2_set_window,
2287 .unset_window = pnv_pci_ioda2_unset_window,
2288 .take_ownership = pnv_ioda2_take_ownership,
2289 .release_ownership = pnv_ioda2_release_ownership,
2290 };
2291 #endif
2292
2293 static void pnv_pci_ioda_setup_opal_tce_kill(struct pnv_phb *phb)
2294 {
2295 const __be64 *swinvp;
2296
2297 /* OPAL variant of PHB3 invalidated TCEs */
2298 swinvp = of_get_property(phb->hose->dn, "ibm,opal-tce-kill", NULL);
2299 if (!swinvp)
2300 return;
2301
2302 phb->ioda.tce_inval_reg_phys = be64_to_cpup(swinvp);
2303 phb->ioda.tce_inval_reg = ioremap(phb->ioda.tce_inval_reg_phys, 8);
2304 }
2305
2306 static __be64 *pnv_pci_ioda2_table_do_alloc_pages(int nid, unsigned shift,
2307 unsigned levels, unsigned long limit,
2308 unsigned long *current_offset, unsigned long *total_allocated)
2309 {
2310 struct page *tce_mem = NULL;
2311 __be64 *addr, *tmp;
2312 unsigned order = max_t(unsigned, shift, PAGE_SHIFT) - PAGE_SHIFT;
2313 unsigned long allocated = 1UL << (order + PAGE_SHIFT);
2314 unsigned entries = 1UL << (shift - 3);
2315 long i;
2316
2317 tce_mem = alloc_pages_node(nid, GFP_KERNEL, order);
2318 if (!tce_mem) {
2319 pr_err("Failed to allocate a TCE memory, order=%d\n", order);
2320 return NULL;
2321 }
2322 addr = page_address(tce_mem);
2323 memset(addr, 0, allocated);
2324 *total_allocated += allocated;
2325
2326 --levels;
2327 if (!levels) {
2328 *current_offset += allocated;
2329 return addr;
2330 }
2331
2332 for (i = 0; i < entries; ++i) {
2333 tmp = pnv_pci_ioda2_table_do_alloc_pages(nid, shift,
2334 levels, limit, current_offset, total_allocated);
2335 if (!tmp)
2336 break;
2337
2338 addr[i] = cpu_to_be64(__pa(tmp) |
2339 TCE_PCI_READ | TCE_PCI_WRITE);
2340
2341 if (*current_offset >= limit)
2342 break;
2343 }
2344
2345 return addr;
2346 }
2347
2348 static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr,
2349 unsigned long size, unsigned level);
2350
2351 static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset,
2352 __u32 page_shift, __u64 window_size, __u32 levels,
2353 struct iommu_table *tbl)
2354 {
2355 void *addr;
2356 unsigned long offset = 0, level_shift, total_allocated = 0;
2357 const unsigned window_shift = ilog2(window_size);
2358 unsigned entries_shift = window_shift - page_shift;
2359 unsigned table_shift = max_t(unsigned, entries_shift + 3, PAGE_SHIFT);
2360 const unsigned long tce_table_size = 1UL << table_shift;
2361
2362 if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS))
2363 return -EINVAL;
2364
2365 if ((window_size > memory_hotplug_max()) || !is_power_of_2(window_size))
2366 return -EINVAL;
2367
2368 /* Adjust direct table size from window_size and levels */
2369 entries_shift = (entries_shift + levels - 1) / levels;
2370 level_shift = entries_shift + 3;
2371 level_shift = max_t(unsigned, level_shift, PAGE_SHIFT);
2372
2373 /* Allocate TCE table */
2374 addr = pnv_pci_ioda2_table_do_alloc_pages(nid, level_shift,
2375 levels, tce_table_size, &offset, &total_allocated);
2376
2377 /* addr==NULL means that the first level allocation failed */
2378 if (!addr)
2379 return -ENOMEM;
2380
2381 /*
2382 * First level was allocated but some lower level failed as
2383 * we did not allocate as much as we wanted,
2384 * release partially allocated table.
2385 */
2386 if (offset < tce_table_size) {
2387 pnv_pci_ioda2_table_do_free_pages(addr,
2388 1ULL << (level_shift - 3), levels - 1);
2389 return -ENOMEM;
2390 }
2391
2392 /* Setup linux iommu table */
2393 pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, bus_offset,
2394 page_shift);
2395 tbl->it_level_size = 1ULL << (level_shift - 3);
2396 tbl->it_indirect_levels = levels - 1;
2397 tbl->it_allocated_size = total_allocated;
2398
2399 pr_devel("Created TCE table: ws=%08llx ts=%lx @%08llx\n",
2400 window_size, tce_table_size, bus_offset);
2401
2402 return 0;
2403 }
2404
2405 static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr,
2406 unsigned long size, unsigned level)
2407 {
2408 const unsigned long addr_ul = (unsigned long) addr &
2409 ~(TCE_PCI_READ | TCE_PCI_WRITE);
2410
2411 if (level) {
2412 long i;
2413 u64 *tmp = (u64 *) addr_ul;
2414
2415 for (i = 0; i < size; ++i) {
2416 unsigned long hpa = be64_to_cpu(tmp[i]);
2417
2418 if (!(hpa & (TCE_PCI_READ | TCE_PCI_WRITE)))
2419 continue;
2420
2421 pnv_pci_ioda2_table_do_free_pages(__va(hpa), size,
2422 level - 1);
2423 }
2424 }
2425
2426 free_pages(addr_ul, get_order(size << 3));
2427 }
2428
2429 static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl)
2430 {
2431 const unsigned long size = tbl->it_indirect_levels ?
2432 tbl->it_level_size : tbl->it_size;
2433
2434 if (!tbl->it_size)
2435 return;
2436
2437 pnv_pci_ioda2_table_do_free_pages((__be64 *)tbl->it_base, size,
2438 tbl->it_indirect_levels);
2439 }
2440
2441 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
2442 struct pnv_ioda_pe *pe)
2443 {
2444 int64_t rc;
2445
2446 /* We shouldn't already have a 32-bit DMA associated */
2447 if (WARN_ON(pe->tce32_seg >= 0))
2448 return;
2449
2450 /* TVE #1 is selected by PCI address bit 59 */
2451 pe->tce_bypass_base = 1ull << 59;
2452
2453 iommu_register_group(&pe->table_group, phb->hose->global_number,
2454 pe->pe_number);
2455
2456 /* The PE will reserve all possible 32-bits space */
2457 pe->tce32_seg = 0;
2458 pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n",
2459 phb->ioda.m32_pci_base);
2460
2461 /* Setup linux iommu table */
2462 pe->table_group.tce32_start = 0;
2463 pe->table_group.tce32_size = phb->ioda.m32_pci_base;
2464 pe->table_group.max_dynamic_windows_supported =
2465 IOMMU_TABLE_GROUP_MAX_TABLES;
2466 pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS;
2467 pe->table_group.pgsizes = SZ_4K | SZ_64K | SZ_16M;
2468 #ifdef CONFIG_IOMMU_API
2469 pe->table_group.ops = &pnv_pci_ioda2_ops;
2470 #endif
2471
2472 rc = pnv_pci_ioda2_setup_default_config(pe);
2473 if (rc) {
2474 if (pe->tce32_seg >= 0)
2475 pe->tce32_seg = -1;
2476 return;
2477 }
2478
2479 if (pe->flags & PNV_IODA_PE_DEV)
2480 iommu_add_device(&pe->pdev->dev);
2481 else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
2482 pnv_ioda_setup_bus_dma(pe, pe->pbus);
2483 }
2484
2485 static void pnv_ioda_setup_dma(struct pnv_phb *phb)
2486 {
2487 struct pci_controller *hose = phb->hose;
2488 unsigned int residual, remaining, segs, tw, base;
2489 struct pnv_ioda_pe *pe;
2490
2491 /* If we have more PE# than segments available, hand out one
2492 * per PE until we run out and let the rest fail. If not,
2493 * then we assign at least one segment per PE, plus more based
2494 * on the amount of devices under that PE
2495 */
2496 if (phb->ioda.dma_pe_count > phb->ioda.tce32_count)
2497 residual = 0;
2498 else
2499 residual = phb->ioda.tce32_count -
2500 phb->ioda.dma_pe_count;
2501
2502 pr_info("PCI: Domain %04x has %ld available 32-bit DMA segments\n",
2503 hose->global_number, phb->ioda.tce32_count);
2504 pr_info("PCI: %d PE# for a total weight of %d\n",
2505 phb->ioda.dma_pe_count, phb->ioda.dma_weight);
2506
2507 pnv_pci_ioda_setup_opal_tce_kill(phb);
2508
2509 /* Walk our PE list and configure their DMA segments, hand them
2510 * out one base segment plus any residual segments based on
2511 * weight
2512 */
2513 remaining = phb->ioda.tce32_count;
2514 tw = phb->ioda.dma_weight;
2515 base = 0;
2516 list_for_each_entry(pe, &phb->ioda.pe_dma_list, dma_link) {
2517 if (!pe->dma_weight)
2518 continue;
2519 if (!remaining) {
2520 pe_warn(pe, "No DMA32 resources available\n");
2521 continue;
2522 }
2523 segs = 1;
2524 if (residual) {
2525 segs += ((pe->dma_weight * residual) + (tw / 2)) / tw;
2526 if (segs > remaining)
2527 segs = remaining;
2528 }
2529
2530 /*
2531 * For IODA2 compliant PHB3, we needn't care about the weight.
2532 * The all available 32-bits DMA space will be assigned to
2533 * the specific PE.
2534 */
2535 if (phb->type == PNV_PHB_IODA1) {
2536 pe_info(pe, "DMA weight %d, assigned %d DMA32 segments\n",
2537 pe->dma_weight, segs);
2538 pnv_pci_ioda_setup_dma_pe(phb, pe, base, segs);
2539 } else if (phb->type == PNV_PHB_IODA2) {
2540 pe_info(pe, "Assign DMA32 space\n");
2541 segs = 0;
2542 pnv_pci_ioda2_setup_dma_pe(phb, pe);
2543 } else if (phb->type == PNV_PHB_NPU) {
2544 /*
2545 * We initialise the DMA space for an NPU PHB
2546 * after setup of the PHB is complete as we
2547 * point the NPU TVT to the the same location
2548 * as the PHB3 TVT.
2549 */
2550 }
2551
2552 remaining -= segs;
2553 base += segs;
2554 }
2555 }
2556
2557 #ifdef CONFIG_PCI_MSI
2558 static void pnv_ioda2_msi_eoi(struct irq_data *d)
2559 {
2560 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
2561 struct irq_chip *chip = irq_data_get_irq_chip(d);
2562 struct pnv_phb *phb = container_of(chip, struct pnv_phb,
2563 ioda.irq_chip);
2564 int64_t rc;
2565
2566 rc = opal_pci_msi_eoi(phb->opal_id, hw_irq);
2567 WARN_ON_ONCE(rc);
2568
2569 icp_native_eoi(d);
2570 }
2571
2572
2573 static void set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq)
2574 {
2575 struct irq_data *idata;
2576 struct irq_chip *ichip;
2577
2578 if (phb->type != PNV_PHB_IODA2)
2579 return;
2580
2581 if (!phb->ioda.irq_chip_init) {
2582 /*
2583 * First time we setup an MSI IRQ, we need to setup the
2584 * corresponding IRQ chip to route correctly.
2585 */
2586 idata = irq_get_irq_data(virq);
2587 ichip = irq_data_get_irq_chip(idata);
2588 phb->ioda.irq_chip_init = 1;
2589 phb->ioda.irq_chip = *ichip;
2590 phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi;
2591 }
2592 irq_set_chip(virq, &phb->ioda.irq_chip);
2593 }
2594
2595 #ifdef CONFIG_CXL_BASE
2596
2597 struct device_node *pnv_pci_get_phb_node(struct pci_dev *dev)
2598 {
2599 struct pci_controller *hose = pci_bus_to_host(dev->bus);
2600
2601 return of_node_get(hose->dn);
2602 }
2603 EXPORT_SYMBOL(pnv_pci_get_phb_node);
2604
2605 int pnv_phb_to_cxl_mode(struct pci_dev *dev, uint64_t mode)
2606 {
2607 struct pci_controller *hose = pci_bus_to_host(dev->bus);
2608 struct pnv_phb *phb = hose->private_data;
2609 struct pnv_ioda_pe *pe;
2610 int rc;
2611
2612 pe = pnv_ioda_get_pe(dev);
2613 if (!pe)
2614 return -ENODEV;
2615
2616 pe_info(pe, "Switching PHB to CXL\n");
2617
2618 rc = opal_pci_set_phb_cxl_mode(phb->opal_id, mode, pe->pe_number);
2619 if (rc)
2620 dev_err(&dev->dev, "opal_pci_set_phb_cxl_mode failed: %i\n", rc);
2621
2622 return rc;
2623 }
2624 EXPORT_SYMBOL(pnv_phb_to_cxl_mode);
2625
2626 /* Find PHB for cxl dev and allocate MSI hwirqs?
2627 * Returns the absolute hardware IRQ number
2628 */
2629 int pnv_cxl_alloc_hwirqs(struct pci_dev *dev, int num)
2630 {
2631 struct pci_controller *hose = pci_bus_to_host(dev->bus);
2632 struct pnv_phb *phb = hose->private_data;
2633 int hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, num);
2634
2635 if (hwirq < 0) {
2636 dev_warn(&dev->dev, "Failed to find a free MSI\n");
2637 return -ENOSPC;
2638 }
2639
2640 return phb->msi_base + hwirq;
2641 }
2642 EXPORT_SYMBOL(pnv_cxl_alloc_hwirqs);
2643
2644 void pnv_cxl_release_hwirqs(struct pci_dev *dev, int hwirq, int num)
2645 {
2646 struct pci_controller *hose = pci_bus_to_host(dev->bus);
2647 struct pnv_phb *phb = hose->private_data;
2648
2649 msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq - phb->msi_base, num);
2650 }
2651 EXPORT_SYMBOL(pnv_cxl_release_hwirqs);
2652
2653 void pnv_cxl_release_hwirq_ranges(struct cxl_irq_ranges *irqs,
2654 struct pci_dev *dev)
2655 {
2656 struct pci_controller *hose = pci_bus_to_host(dev->bus);
2657 struct pnv_phb *phb = hose->private_data;
2658 int i, hwirq;
2659
2660 for (i = 1; i < CXL_IRQ_RANGES; i++) {
2661 if (!irqs->range[i])
2662 continue;
2663 pr_devel("cxl release irq range 0x%x: offset: 0x%lx limit: %ld\n",
2664 i, irqs->offset[i],
2665 irqs->range[i]);
2666 hwirq = irqs->offset[i] - phb->msi_base;
2667 msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq,
2668 irqs->range[i]);
2669 }
2670 }
2671 EXPORT_SYMBOL(pnv_cxl_release_hwirq_ranges);
2672
2673 int pnv_cxl_alloc_hwirq_ranges(struct cxl_irq_ranges *irqs,
2674 struct pci_dev *dev, int num)
2675 {
2676 struct pci_controller *hose = pci_bus_to_host(dev->bus);
2677 struct pnv_phb *phb = hose->private_data;
2678 int i, hwirq, try;
2679
2680 memset(irqs, 0, sizeof(struct cxl_irq_ranges));
2681
2682 /* 0 is reserved for the multiplexed PSL DSI interrupt */
2683 for (i = 1; i < CXL_IRQ_RANGES && num; i++) {
2684 try = num;
2685 while (try) {
2686 hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, try);
2687 if (hwirq >= 0)
2688 break;
2689 try /= 2;
2690 }
2691 if (!try)
2692 goto fail;
2693
2694 irqs->offset[i] = phb->msi_base + hwirq;
2695 irqs->range[i] = try;
2696 pr_devel("cxl alloc irq range 0x%x: offset: 0x%lx limit: %li\n",
2697 i, irqs->offset[i], irqs->range[i]);
2698 num -= try;
2699 }
2700 if (num)
2701 goto fail;
2702
2703 return 0;
2704 fail:
2705 pnv_cxl_release_hwirq_ranges(irqs, dev);
2706 return -ENOSPC;
2707 }
2708 EXPORT_SYMBOL(pnv_cxl_alloc_hwirq_ranges);
2709
2710 int pnv_cxl_get_irq_count(struct pci_dev *dev)
2711 {
2712 struct pci_controller *hose = pci_bus_to_host(dev->bus);
2713 struct pnv_phb *phb = hose->private_data;
2714
2715 return phb->msi_bmp.irq_count;
2716 }
2717 EXPORT_SYMBOL(pnv_cxl_get_irq_count);
2718
2719 int pnv_cxl_ioda_msi_setup(struct pci_dev *dev, unsigned int hwirq,
2720 unsigned int virq)
2721 {
2722 struct pci_controller *hose = pci_bus_to_host(dev->bus);
2723 struct pnv_phb *phb = hose->private_data;
2724 unsigned int xive_num = hwirq - phb->msi_base;
2725 struct pnv_ioda_pe *pe;
2726 int rc;
2727
2728 if (!(pe = pnv_ioda_get_pe(dev)))
2729 return -ENODEV;
2730
2731 /* Assign XIVE to PE */
2732 rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num);
2733 if (rc) {
2734 pe_warn(pe, "%s: OPAL error %d setting msi_base 0x%x "
2735 "hwirq 0x%x XIVE 0x%x PE\n",
2736 pci_name(dev), rc, phb->msi_base, hwirq, xive_num);
2737 return -EIO;
2738 }
2739 set_msi_irq_chip(phb, virq);
2740
2741 return 0;
2742 }
2743 EXPORT_SYMBOL(pnv_cxl_ioda_msi_setup);
2744 #endif
2745
2746 static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev,
2747 unsigned int hwirq, unsigned int virq,
2748 unsigned int is_64, struct msi_msg *msg)
2749 {
2750 struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev);
2751 unsigned int xive_num = hwirq - phb->msi_base;
2752 __be32 data;
2753 int rc;
2754
2755 /* No PE assigned ? bail out ... no MSI for you ! */
2756 if (pe == NULL)
2757 return -ENXIO;
2758
2759 /* Check if we have an MVE */
2760 if (pe->mve_number < 0)
2761 return -ENXIO;
2762
2763 /* Force 32-bit MSI on some broken devices */
2764 if (dev->no_64bit_msi)
2765 is_64 = 0;
2766
2767 /* Assign XIVE to PE */
2768 rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num);
2769 if (rc) {
2770 pr_warn("%s: OPAL error %d setting XIVE %d PE\n",
2771 pci_name(dev), rc, xive_num);
2772 return -EIO;
2773 }
2774
2775 if (is_64) {
2776 __be64 addr64;
2777
2778 rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1,
2779 &addr64, &data);
2780 if (rc) {
2781 pr_warn("%s: OPAL error %d getting 64-bit MSI data\n",
2782 pci_name(dev), rc);
2783 return -EIO;
2784 }
2785 msg->address_hi = be64_to_cpu(addr64) >> 32;
2786 msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful;
2787 } else {
2788 __be32 addr32;
2789
2790 rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1,
2791 &addr32, &data);
2792 if (rc) {
2793 pr_warn("%s: OPAL error %d getting 32-bit MSI data\n",
2794 pci_name(dev), rc);
2795 return -EIO;
2796 }
2797 msg->address_hi = 0;
2798 msg->address_lo = be32_to_cpu(addr32);
2799 }
2800 msg->data = be32_to_cpu(data);
2801
2802 set_msi_irq_chip(phb, virq);
2803
2804 pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d),"
2805 " address=%x_%08x data=%x PE# %d\n",
2806 pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num,
2807 msg->address_hi, msg->address_lo, data, pe->pe_number);
2808
2809 return 0;
2810 }
2811
2812 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb)
2813 {
2814 unsigned int count;
2815 const __be32 *prop = of_get_property(phb->hose->dn,
2816 "ibm,opal-msi-ranges", NULL);
2817 if (!prop) {
2818 /* BML Fallback */
2819 prop = of_get_property(phb->hose->dn, "msi-ranges", NULL);
2820 }
2821 if (!prop)
2822 return;
2823
2824 phb->msi_base = be32_to_cpup(prop);
2825 count = be32_to_cpup(prop + 1);
2826 if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) {
2827 pr_err("PCI %d: Failed to allocate MSI bitmap !\n",
2828 phb->hose->global_number);
2829 return;
2830 }
2831
2832 phb->msi_setup = pnv_pci_ioda_msi_setup;
2833 phb->msi32_support = 1;
2834 pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n",
2835 count, phb->msi_base);
2836 }
2837 #else
2838 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { }
2839 #endif /* CONFIG_PCI_MSI */
2840
2841 #ifdef CONFIG_PCI_IOV
2842 static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev)
2843 {
2844 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
2845 struct pnv_phb *phb = hose->private_data;
2846 const resource_size_t gate = phb->ioda.m64_segsize >> 2;
2847 struct resource *res;
2848 int i;
2849 resource_size_t size, total_vf_bar_sz;
2850 struct pci_dn *pdn;
2851 int mul, total_vfs;
2852
2853 if (!pdev->is_physfn || pdev->is_added)
2854 return;
2855
2856 pdn = pci_get_pdn(pdev);
2857 pdn->vfs_expanded = 0;
2858 pdn->m64_single_mode = false;
2859
2860 total_vfs = pci_sriov_get_totalvfs(pdev);
2861 mul = phb->ioda.total_pe;
2862 total_vf_bar_sz = 0;
2863
2864 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
2865 res = &pdev->resource[i + PCI_IOV_RESOURCES];
2866 if (!res->flags || res->parent)
2867 continue;
2868 if (!pnv_pci_is_mem_pref_64(res->flags)) {
2869 dev_warn(&pdev->dev, "Don't support SR-IOV with"
2870 " non M64 VF BAR%d: %pR. \n",
2871 i, res);
2872 goto truncate_iov;
2873 }
2874
2875 total_vf_bar_sz += pci_iov_resource_size(pdev,
2876 i + PCI_IOV_RESOURCES);
2877
2878 /*
2879 * If bigger than quarter of M64 segment size, just round up
2880 * power of two.
2881 *
2882 * Generally, one M64 BAR maps one IOV BAR. To avoid conflict
2883 * with other devices, IOV BAR size is expanded to be
2884 * (total_pe * VF_BAR_size). When VF_BAR_size is half of M64
2885 * segment size , the expanded size would equal to half of the
2886 * whole M64 space size, which will exhaust the M64 Space and
2887 * limit the system flexibility. This is a design decision to
2888 * set the boundary to quarter of the M64 segment size.
2889 */
2890 if (total_vf_bar_sz > gate) {
2891 mul = roundup_pow_of_two(total_vfs);
2892 dev_info(&pdev->dev,
2893 "VF BAR Total IOV size %llx > %llx, roundup to %d VFs\n",
2894 total_vf_bar_sz, gate, mul);
2895 pdn->m64_single_mode = true;
2896 break;
2897 }
2898 }
2899
2900 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
2901 res = &pdev->resource[i + PCI_IOV_RESOURCES];
2902 if (!res->flags || res->parent)
2903 continue;
2904
2905 size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES);
2906 /*
2907 * On PHB3, the minimum size alignment of M64 BAR in single
2908 * mode is 32MB.
2909 */
2910 if (pdn->m64_single_mode && (size < SZ_32M))
2911 goto truncate_iov;
2912 dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res);
2913 res->end = res->start + size * mul - 1;
2914 dev_dbg(&pdev->dev, " %pR\n", res);
2915 dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)",
2916 i, res, mul);
2917 }
2918 pdn->vfs_expanded = mul;
2919
2920 return;
2921
2922 truncate_iov:
2923 /* To save MMIO space, IOV BAR is truncated. */
2924 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
2925 res = &pdev->resource[i + PCI_IOV_RESOURCES];
2926 res->flags = 0;
2927 res->end = res->start - 1;
2928 }
2929 }
2930 #endif /* CONFIG_PCI_IOV */
2931
2932 /*
2933 * This function is supposed to be called on basis of PE from top
2934 * to bottom style. So the the I/O or MMIO segment assigned to
2935 * parent PE could be overrided by its child PEs if necessary.
2936 */
2937 static void pnv_ioda_setup_pe_seg(struct pci_controller *hose,
2938 struct pnv_ioda_pe *pe)
2939 {
2940 struct pnv_phb *phb = hose->private_data;
2941 struct pci_bus_region region;
2942 struct resource *res;
2943 int i, index;
2944 int rc;
2945
2946 /*
2947 * NOTE: We only care PCI bus based PE for now. For PCI
2948 * device based PE, for example SRIOV sensitive VF should
2949 * be figured out later.
2950 */
2951 BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)));
2952
2953 pci_bus_for_each_resource(pe->pbus, res, i) {
2954 if (!res || !res->flags ||
2955 res->start > res->end)
2956 continue;
2957
2958 if (res->flags & IORESOURCE_IO) {
2959 region.start = res->start - phb->ioda.io_pci_base;
2960 region.end = res->end - phb->ioda.io_pci_base;
2961 index = region.start / phb->ioda.io_segsize;
2962
2963 while (index < phb->ioda.total_pe &&
2964 region.start <= region.end) {
2965 phb->ioda.io_segmap[index] = pe->pe_number;
2966 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
2967 pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index);
2968 if (rc != OPAL_SUCCESS) {
2969 pr_err("%s: OPAL error %d when mapping IO "
2970 "segment #%d to PE#%d\n",
2971 __func__, rc, index, pe->pe_number);
2972 break;
2973 }
2974
2975 region.start += phb->ioda.io_segsize;
2976 index++;
2977 }
2978 } else if ((res->flags & IORESOURCE_MEM) &&
2979 !pnv_pci_is_mem_pref_64(res->flags)) {
2980 region.start = res->start -
2981 hose->mem_offset[0] -
2982 phb->ioda.m32_pci_base;
2983 region.end = res->end -
2984 hose->mem_offset[0] -
2985 phb->ioda.m32_pci_base;
2986 index = region.start / phb->ioda.m32_segsize;
2987
2988 while (index < phb->ioda.total_pe &&
2989 region.start <= region.end) {
2990 phb->ioda.m32_segmap[index] = pe->pe_number;
2991 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
2992 pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index);
2993 if (rc != OPAL_SUCCESS) {
2994 pr_err("%s: OPAL error %d when mapping M32 "
2995 "segment#%d to PE#%d",
2996 __func__, rc, index, pe->pe_number);
2997 break;
2998 }
2999
3000 region.start += phb->ioda.m32_segsize;
3001 index++;
3002 }
3003 }
3004 }
3005 }
3006
3007 static void pnv_pci_ioda_setup_seg(void)
3008 {
3009 struct pci_controller *tmp, *hose;
3010 struct pnv_phb *phb;
3011 struct pnv_ioda_pe *pe;
3012
3013 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
3014 phb = hose->private_data;
3015
3016 /* NPU PHB does not support IO or MMIO segmentation */
3017 if (phb->type == PNV_PHB_NPU)
3018 continue;
3019
3020 list_for_each_entry(pe, &phb->ioda.pe_list, list) {
3021 pnv_ioda_setup_pe_seg(hose, pe);
3022 }
3023 }
3024 }
3025
3026 static void pnv_pci_ioda_setup_DMA(void)
3027 {
3028 struct pci_controller *hose, *tmp;
3029 struct pnv_phb *phb;
3030
3031 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
3032 pnv_ioda_setup_dma(hose->private_data);
3033
3034 /* Mark the PHB initialization done */
3035 phb = hose->private_data;
3036 phb->initialized = 1;
3037 }
3038 }
3039
3040 static void pnv_pci_ioda_create_dbgfs(void)
3041 {
3042 #ifdef CONFIG_DEBUG_FS
3043 struct pci_controller *hose, *tmp;
3044 struct pnv_phb *phb;
3045 char name[16];
3046
3047 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
3048 phb = hose->private_data;
3049
3050 sprintf(name, "PCI%04x", hose->global_number);
3051 phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root);
3052 if (!phb->dbgfs)
3053 pr_warning("%s: Error on creating debugfs on PHB#%x\n",
3054 __func__, hose->global_number);
3055 }
3056 #endif /* CONFIG_DEBUG_FS */
3057 }
3058
3059 static void pnv_npu_ioda_fixup(void)
3060 {
3061 bool enable_bypass;
3062 struct pci_controller *hose, *tmp;
3063 struct pnv_phb *phb;
3064 struct pnv_ioda_pe *pe;
3065
3066 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
3067 phb = hose->private_data;
3068 if (phb->type != PNV_PHB_NPU)
3069 continue;
3070
3071 list_for_each_entry(pe, &phb->ioda.pe_dma_list, dma_link) {
3072 enable_bypass = dma_get_mask(&pe->pdev->dev) ==
3073 DMA_BIT_MASK(64);
3074 pnv_npu_init_dma_pe(pe);
3075 pnv_npu_dma_set_bypass(pe, enable_bypass);
3076 }
3077 }
3078 }
3079
3080 static void pnv_pci_ioda_fixup(void)
3081 {
3082 pnv_pci_ioda_setup_PEs();
3083 pnv_pci_ioda_setup_seg();
3084 pnv_pci_ioda_setup_DMA();
3085
3086 pnv_pci_ioda_create_dbgfs();
3087
3088 #ifdef CONFIG_EEH
3089 eeh_init();
3090 eeh_addr_cache_build();
3091 #endif
3092
3093 /* Link NPU IODA tables to their PCI devices. */
3094 pnv_npu_ioda_fixup();
3095 }
3096
3097 /*
3098 * Returns the alignment for I/O or memory windows for P2P
3099 * bridges. That actually depends on how PEs are segmented.
3100 * For now, we return I/O or M32 segment size for PE sensitive
3101 * P2P bridges. Otherwise, the default values (4KiB for I/O,
3102 * 1MiB for memory) will be returned.
3103 *
3104 * The current PCI bus might be put into one PE, which was
3105 * create against the parent PCI bridge. For that case, we
3106 * needn't enlarge the alignment so that we can save some
3107 * resources.
3108 */
3109 static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus,
3110 unsigned long type)
3111 {
3112 struct pci_dev *bridge;
3113 struct pci_controller *hose = pci_bus_to_host(bus);
3114 struct pnv_phb *phb = hose->private_data;
3115 int num_pci_bridges = 0;
3116
3117 bridge = bus->self;
3118 while (bridge) {
3119 if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) {
3120 num_pci_bridges++;
3121 if (num_pci_bridges >= 2)
3122 return 1;
3123 }
3124
3125 bridge = bridge->bus->self;
3126 }
3127
3128 /* We fail back to M32 if M64 isn't supported */
3129 if (phb->ioda.m64_segsize &&
3130 pnv_pci_is_mem_pref_64(type))
3131 return phb->ioda.m64_segsize;
3132 if (type & IORESOURCE_MEM)
3133 return phb->ioda.m32_segsize;
3134
3135 return phb->ioda.io_segsize;
3136 }
3137
3138 #ifdef CONFIG_PCI_IOV
3139 static resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev,
3140 int resno)
3141 {
3142 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
3143 struct pnv_phb *phb = hose->private_data;
3144 struct pci_dn *pdn = pci_get_pdn(pdev);
3145 resource_size_t align;
3146
3147 /*
3148 * On PowerNV platform, IOV BAR is mapped by M64 BAR to enable the
3149 * SR-IOV. While from hardware perspective, the range mapped by M64
3150 * BAR should be size aligned.
3151 *
3152 * When IOV BAR is mapped with M64 BAR in Single PE mode, the extra
3153 * powernv-specific hardware restriction is gone. But if just use the
3154 * VF BAR size as the alignment, PF BAR / VF BAR may be allocated with
3155 * in one segment of M64 #15, which introduces the PE conflict between
3156 * PF and VF. Based on this, the minimum alignment of an IOV BAR is
3157 * m64_segsize.
3158 *
3159 * This function returns the total IOV BAR size if M64 BAR is in
3160 * Shared PE mode or just VF BAR size if not.
3161 * If the M64 BAR is in Single PE mode, return the VF BAR size or
3162 * M64 segment size if IOV BAR size is less.
3163 */
3164 align = pci_iov_resource_size(pdev, resno);
3165 if (!pdn->vfs_expanded)
3166 return align;
3167 if (pdn->m64_single_mode)
3168 return max(align, (resource_size_t)phb->ioda.m64_segsize);
3169
3170 return pdn->vfs_expanded * align;
3171 }
3172 #endif /* CONFIG_PCI_IOV */
3173
3174 /* Prevent enabling devices for which we couldn't properly
3175 * assign a PE
3176 */
3177 static bool pnv_pci_enable_device_hook(struct pci_dev *dev)
3178 {
3179 struct pci_controller *hose = pci_bus_to_host(dev->bus);
3180 struct pnv_phb *phb = hose->private_data;
3181 struct pci_dn *pdn;
3182
3183 /* The function is probably called while the PEs have
3184 * not be created yet. For example, resource reassignment
3185 * during PCI probe period. We just skip the check if
3186 * PEs isn't ready.
3187 */
3188 if (!phb->initialized)
3189 return true;
3190
3191 pdn = pci_get_pdn(dev);
3192 if (!pdn || pdn->pe_number == IODA_INVALID_PE)
3193 return false;
3194
3195 return true;
3196 }
3197
3198 static u32 pnv_ioda_bdfn_to_pe(struct pnv_phb *phb, struct pci_bus *bus,
3199 u32 devfn)
3200 {
3201 return phb->ioda.pe_rmap[(bus->number << 8) | devfn];
3202 }
3203
3204 static void pnv_pci_ioda_shutdown(struct pci_controller *hose)
3205 {
3206 struct pnv_phb *phb = hose->private_data;
3207
3208 opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE,
3209 OPAL_ASSERT_RESET);
3210 }
3211
3212 static const struct pci_controller_ops pnv_pci_ioda_controller_ops = {
3213 .dma_dev_setup = pnv_pci_dma_dev_setup,
3214 .dma_bus_setup = pnv_pci_dma_bus_setup,
3215 #ifdef CONFIG_PCI_MSI
3216 .setup_msi_irqs = pnv_setup_msi_irqs,
3217 .teardown_msi_irqs = pnv_teardown_msi_irqs,
3218 #endif
3219 .enable_device_hook = pnv_pci_enable_device_hook,
3220 .window_alignment = pnv_pci_window_alignment,
3221 .reset_secondary_bus = pnv_pci_reset_secondary_bus,
3222 .dma_set_mask = pnv_pci_ioda_dma_set_mask,
3223 .dma_get_required_mask = pnv_pci_ioda_dma_get_required_mask,
3224 .shutdown = pnv_pci_ioda_shutdown,
3225 };
3226
3227 static const struct pci_controller_ops pnv_npu_ioda_controller_ops = {
3228 .dma_dev_setup = pnv_pci_dma_dev_setup,
3229 #ifdef CONFIG_PCI_MSI
3230 .setup_msi_irqs = pnv_setup_msi_irqs,
3231 .teardown_msi_irqs = pnv_teardown_msi_irqs,
3232 #endif
3233 .enable_device_hook = pnv_pci_enable_device_hook,
3234 .window_alignment = pnv_pci_window_alignment,
3235 .reset_secondary_bus = pnv_pci_reset_secondary_bus,
3236 .dma_set_mask = pnv_npu_dma_set_mask,
3237 .shutdown = pnv_pci_ioda_shutdown,
3238 };
3239
3240 static void __init pnv_pci_init_ioda_phb(struct device_node *np,
3241 u64 hub_id, int ioda_type)
3242 {
3243 struct pci_controller *hose;
3244 struct pnv_phb *phb;
3245 unsigned long size, m32map_off, pemap_off, iomap_off = 0;
3246 const __be64 *prop64;
3247 const __be32 *prop32;
3248 int len;
3249 u64 phb_id;
3250 void *aux;
3251 long rc;
3252
3253 pr_info("Initializing IODA%d OPAL PHB %s\n", ioda_type, np->full_name);
3254
3255 prop64 = of_get_property(np, "ibm,opal-phbid", NULL);
3256 if (!prop64) {
3257 pr_err(" Missing \"ibm,opal-phbid\" property !\n");
3258 return;
3259 }
3260 phb_id = be64_to_cpup(prop64);
3261 pr_debug(" PHB-ID : 0x%016llx\n", phb_id);
3262
3263 phb = memblock_virt_alloc(sizeof(struct pnv_phb), 0);
3264
3265 /* Allocate PCI controller */
3266 phb->hose = hose = pcibios_alloc_controller(np);
3267 if (!phb->hose) {
3268 pr_err(" Can't allocate PCI controller for %s\n",
3269 np->full_name);
3270 memblock_free(__pa(phb), sizeof(struct pnv_phb));
3271 return;
3272 }
3273
3274 spin_lock_init(&phb->lock);
3275 prop32 = of_get_property(np, "bus-range", &len);
3276 if (prop32 && len == 8) {
3277 hose->first_busno = be32_to_cpu(prop32[0]);
3278 hose->last_busno = be32_to_cpu(prop32[1]);
3279 } else {
3280 pr_warn(" Broken <bus-range> on %s\n", np->full_name);
3281 hose->first_busno = 0;
3282 hose->last_busno = 0xff;
3283 }
3284 hose->private_data = phb;
3285 phb->hub_id = hub_id;
3286 phb->opal_id = phb_id;
3287 phb->type = ioda_type;
3288 mutex_init(&phb->ioda.pe_alloc_mutex);
3289
3290 /* Detect specific models for error handling */
3291 if (of_device_is_compatible(np, "ibm,p7ioc-pciex"))
3292 phb->model = PNV_PHB_MODEL_P7IOC;
3293 else if (of_device_is_compatible(np, "ibm,power8-pciex"))
3294 phb->model = PNV_PHB_MODEL_PHB3;
3295 else if (of_device_is_compatible(np, "ibm,power8-npu-pciex"))
3296 phb->model = PNV_PHB_MODEL_NPU;
3297 else
3298 phb->model = PNV_PHB_MODEL_UNKNOWN;
3299
3300 /* Parse 32-bit and IO ranges (if any) */
3301 pci_process_bridge_OF_ranges(hose, np, !hose->global_number);
3302
3303 /* Get registers */
3304 phb->regs = of_iomap(np, 0);
3305 if (phb->regs == NULL)
3306 pr_err(" Failed to map registers !\n");
3307
3308 /* Initialize more IODA stuff */
3309 phb->ioda.total_pe = 1;
3310 prop32 = of_get_property(np, "ibm,opal-num-pes", NULL);
3311 if (prop32)
3312 phb->ioda.total_pe = be32_to_cpup(prop32);
3313 prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL);
3314 if (prop32)
3315 phb->ioda.reserved_pe = be32_to_cpup(prop32);
3316
3317 /* Parse 64-bit MMIO range */
3318 pnv_ioda_parse_m64_window(phb);
3319
3320 phb->ioda.m32_size = resource_size(&hose->mem_resources[0]);
3321 /* FW Has already off top 64k of M32 space (MSI space) */
3322 phb->ioda.m32_size += 0x10000;
3323
3324 phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe;
3325 phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0];
3326 phb->ioda.io_size = hose->pci_io_size;
3327 phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe;
3328 phb->ioda.io_pci_base = 0; /* XXX calculate this ? */
3329
3330 /* Allocate aux data & arrays. We don't have IO ports on PHB3 */
3331 size = _ALIGN_UP(phb->ioda.total_pe / 8, sizeof(unsigned long));
3332 m32map_off = size;
3333 size += phb->ioda.total_pe * sizeof(phb->ioda.m32_segmap[0]);
3334 if (phb->type == PNV_PHB_IODA1) {
3335 iomap_off = size;
3336 size += phb->ioda.total_pe * sizeof(phb->ioda.io_segmap[0]);
3337 }
3338 pemap_off = size;
3339 size += phb->ioda.total_pe * sizeof(struct pnv_ioda_pe);
3340 aux = memblock_virt_alloc(size, 0);
3341 phb->ioda.pe_alloc = aux;
3342 phb->ioda.m32_segmap = aux + m32map_off;
3343 if (phb->type == PNV_PHB_IODA1)
3344 phb->ioda.io_segmap = aux + iomap_off;
3345 phb->ioda.pe_array = aux + pemap_off;
3346 set_bit(phb->ioda.reserved_pe, phb->ioda.pe_alloc);
3347
3348 INIT_LIST_HEAD(&phb->ioda.pe_dma_list);
3349 INIT_LIST_HEAD(&phb->ioda.pe_list);
3350 mutex_init(&phb->ioda.pe_list_mutex);
3351
3352 /* Calculate how many 32-bit TCE segments we have */
3353 phb->ioda.tce32_count = phb->ioda.m32_pci_base >> 28;
3354
3355 #if 0 /* We should really do that ... */
3356 rc = opal_pci_set_phb_mem_window(opal->phb_id,
3357 window_type,
3358 window_num,
3359 starting_real_address,
3360 starting_pci_address,
3361 segment_size);
3362 #endif
3363
3364 pr_info(" %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n",
3365 phb->ioda.total_pe, phb->ioda.reserved_pe,
3366 phb->ioda.m32_size, phb->ioda.m32_segsize);
3367 if (phb->ioda.m64_size)
3368 pr_info(" M64: 0x%lx [segment=0x%lx]\n",
3369 phb->ioda.m64_size, phb->ioda.m64_segsize);
3370 if (phb->ioda.io_size)
3371 pr_info(" IO: 0x%x [segment=0x%x]\n",
3372 phb->ioda.io_size, phb->ioda.io_segsize);
3373
3374
3375 phb->hose->ops = &pnv_pci_ops;
3376 phb->get_pe_state = pnv_ioda_get_pe_state;
3377 phb->freeze_pe = pnv_ioda_freeze_pe;
3378 phb->unfreeze_pe = pnv_ioda_unfreeze_pe;
3379
3380 /* Setup RID -> PE mapping function */
3381 phb->bdfn_to_pe = pnv_ioda_bdfn_to_pe;
3382
3383 /* Setup TCEs */
3384 phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup;
3385
3386 /* Setup MSI support */
3387 pnv_pci_init_ioda_msis(phb);
3388
3389 /*
3390 * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here
3391 * to let the PCI core do resource assignment. It's supposed
3392 * that the PCI core will do correct I/O and MMIO alignment
3393 * for the P2P bridge bars so that each PCI bus (excluding
3394 * the child P2P bridges) can form individual PE.
3395 */
3396 ppc_md.pcibios_fixup = pnv_pci_ioda_fixup;
3397
3398 if (phb->type == PNV_PHB_NPU)
3399 hose->controller_ops = pnv_npu_ioda_controller_ops;
3400 else
3401 hose->controller_ops = pnv_pci_ioda_controller_ops;
3402
3403 #ifdef CONFIG_PCI_IOV
3404 ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov_resources;
3405 ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment;
3406 #endif
3407
3408 pci_add_flags(PCI_REASSIGN_ALL_RSRC);
3409
3410 /* Reset IODA tables to a clean state */
3411 rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET);
3412 if (rc)
3413 pr_warning(" OPAL Error %ld performing IODA table reset !\n", rc);
3414
3415 /* If we're running in kdump kerenl, the previous kerenl never
3416 * shutdown PCI devices correctly. We already got IODA table
3417 * cleaned out. So we have to issue PHB reset to stop all PCI
3418 * transactions from previous kerenl.
3419 */
3420 if (is_kdump_kernel()) {
3421 pr_info(" Issue PHB reset ...\n");
3422 pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL);
3423 pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE);
3424 }
3425
3426 /* Remove M64 resource if we can't configure it successfully */
3427 if (!phb->init_m64 || phb->init_m64(phb))
3428 hose->mem_resources[1].flags = 0;
3429 }
3430
3431 void __init pnv_pci_init_ioda2_phb(struct device_node *np)
3432 {
3433 pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2);
3434 }
3435
3436 void __init pnv_pci_init_npu_phb(struct device_node *np)
3437 {
3438 pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU);
3439 }
3440
3441 void __init pnv_pci_init_ioda_hub(struct device_node *np)
3442 {
3443 struct device_node *phbn;
3444 const __be64 *prop64;
3445 u64 hub_id;
3446
3447 pr_info("Probing IODA IO-Hub %s\n", np->full_name);
3448
3449 prop64 = of_get_property(np, "ibm,opal-hubid", NULL);
3450 if (!prop64) {
3451 pr_err(" Missing \"ibm,opal-hubid\" property !\n");
3452 return;
3453 }
3454 hub_id = be64_to_cpup(prop64);
3455 pr_devel(" HUB-ID : 0x%016llx\n", hub_id);
3456
3457 /* Count child PHBs */
3458 for_each_child_of_node(np, phbn) {
3459 /* Look for IODA1 PHBs */
3460 if (of_device_is_compatible(phbn, "ibm,ioda-phb"))
3461 pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1);
3462 }
3463 }
Linux kernel - Deliverables
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