2 * Support PCI/PCIe on PowerNV platforms
4 * Currently supports only P5IOC2
6 * Copyright 2011 Benjamin Herrenschmidt, IBM Corp.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
14 #include <linux/kernel.h>
15 #include <linux/pci.h>
16 #include <linux/delay.h>
17 #include <linux/string.h>
18 #include <linux/init.h>
19 #include <linux/irq.h>
21 #include <linux/msi.h>
22 #include <linux/iommu.h>
24 #include <asm/sections.h>
27 #include <asm/pci-bridge.h>
28 #include <asm/machdep.h>
29 #include <asm/msi_bitmap.h>
30 #include <asm/ppc-pci.h>
32 #include <asm/iommu.h>
34 #include <asm/firmware.h>
35 #include <asm/eeh_event.h>
42 #define PCI_RESET_DELAY_US 3000000
44 #define cfg_dbg(fmt...) do { } while(0)
45 //#define cfg_dbg(fmt...) printk(fmt)
48 static int pnv_setup_msi_irqs(struct pci_dev
*pdev
, int nvec
, int type
)
50 struct pci_controller
*hose
= pci_bus_to_host(pdev
->bus
);
51 struct pnv_phb
*phb
= hose
->private_data
;
52 struct msi_desc
*entry
;
58 if (WARN_ON(!phb
) || !phb
->msi_bmp
.bitmap
)
61 if (pdev
->no_64bit_msi
&& !phb
->msi32_support
)
64 list_for_each_entry(entry
, &pdev
->msi_list
, list
) {
65 if (!entry
->msi_attrib
.is_64
&& !phb
->msi32_support
) {
66 pr_warn("%s: Supports only 64-bit MSIs\n",
70 hwirq
= msi_bitmap_alloc_hwirqs(&phb
->msi_bmp
, 1);
72 pr_warn("%s: Failed to find a free MSI\n",
76 virq
= irq_create_mapping(NULL
, phb
->msi_base
+ hwirq
);
78 pr_warn("%s: Failed to map MSI to linux irq\n",
80 msi_bitmap_free_hwirqs(&phb
->msi_bmp
, hwirq
, 1);
83 rc
= phb
->msi_setup(phb
, pdev
, phb
->msi_base
+ hwirq
,
84 virq
, entry
->msi_attrib
.is_64
, &msg
);
86 pr_warn("%s: Failed to setup MSI\n", pci_name(pdev
));
87 irq_dispose_mapping(virq
);
88 msi_bitmap_free_hwirqs(&phb
->msi_bmp
, hwirq
, 1);
91 irq_set_msi_desc(virq
, entry
);
92 pci_write_msi_msg(virq
, &msg
);
97 static void pnv_teardown_msi_irqs(struct pci_dev
*pdev
)
99 struct pci_controller
*hose
= pci_bus_to_host(pdev
->bus
);
100 struct pnv_phb
*phb
= hose
->private_data
;
101 struct msi_desc
*entry
;
106 list_for_each_entry(entry
, &pdev
->msi_list
, list
) {
107 if (entry
->irq
== NO_IRQ
)
109 irq_set_msi_desc(entry
->irq
, NULL
);
110 msi_bitmap_free_hwirqs(&phb
->msi_bmp
,
111 virq_to_hw(entry
->irq
) - phb
->msi_base
, 1);
112 irq_dispose_mapping(entry
->irq
);
115 #endif /* CONFIG_PCI_MSI */
117 static void pnv_pci_dump_p7ioc_diag_data(struct pci_controller
*hose
,
118 struct OpalIoPhbErrorCommon
*common
)
120 struct OpalIoP7IOCPhbErrorData
*data
;
123 data
= (struct OpalIoP7IOCPhbErrorData
*)common
;
124 pr_info("P7IOC PHB#%d Diag-data (Version: %d)\n",
125 hose
->global_number
, be32_to_cpu(common
->version
));
128 pr_info("brdgCtl: %08x\n",
129 be32_to_cpu(data
->brdgCtl
));
130 if (data
->portStatusReg
|| data
->rootCmplxStatus
||
131 data
->busAgentStatus
)
132 pr_info("UtlSts: %08x %08x %08x\n",
133 be32_to_cpu(data
->portStatusReg
),
134 be32_to_cpu(data
->rootCmplxStatus
),
135 be32_to_cpu(data
->busAgentStatus
));
136 if (data
->deviceStatus
|| data
->slotStatus
||
137 data
->linkStatus
|| data
->devCmdStatus
||
139 pr_info("RootSts: %08x %08x %08x %08x %08x\n",
140 be32_to_cpu(data
->deviceStatus
),
141 be32_to_cpu(data
->slotStatus
),
142 be32_to_cpu(data
->linkStatus
),
143 be32_to_cpu(data
->devCmdStatus
),
144 be32_to_cpu(data
->devSecStatus
));
145 if (data
->rootErrorStatus
|| data
->uncorrErrorStatus
||
146 data
->corrErrorStatus
)
147 pr_info("RootErrSts: %08x %08x %08x\n",
148 be32_to_cpu(data
->rootErrorStatus
),
149 be32_to_cpu(data
->uncorrErrorStatus
),
150 be32_to_cpu(data
->corrErrorStatus
));
151 if (data
->tlpHdr1
|| data
->tlpHdr2
||
152 data
->tlpHdr3
|| data
->tlpHdr4
)
153 pr_info("RootErrLog: %08x %08x %08x %08x\n",
154 be32_to_cpu(data
->tlpHdr1
),
155 be32_to_cpu(data
->tlpHdr2
),
156 be32_to_cpu(data
->tlpHdr3
),
157 be32_to_cpu(data
->tlpHdr4
));
158 if (data
->sourceId
|| data
->errorClass
||
160 pr_info("RootErrLog1: %08x %016llx %016llx\n",
161 be32_to_cpu(data
->sourceId
),
162 be64_to_cpu(data
->errorClass
),
163 be64_to_cpu(data
->correlator
));
164 if (data
->p7iocPlssr
|| data
->p7iocCsr
)
165 pr_info("PhbSts: %016llx %016llx\n",
166 be64_to_cpu(data
->p7iocPlssr
),
167 be64_to_cpu(data
->p7iocCsr
));
169 pr_info("Lem: %016llx %016llx %016llx\n",
170 be64_to_cpu(data
->lemFir
),
171 be64_to_cpu(data
->lemErrorMask
),
172 be64_to_cpu(data
->lemWOF
));
173 if (data
->phbErrorStatus
)
174 pr_info("PhbErr: %016llx %016llx %016llx %016llx\n",
175 be64_to_cpu(data
->phbErrorStatus
),
176 be64_to_cpu(data
->phbFirstErrorStatus
),
177 be64_to_cpu(data
->phbErrorLog0
),
178 be64_to_cpu(data
->phbErrorLog1
));
179 if (data
->mmioErrorStatus
)
180 pr_info("OutErr: %016llx %016llx %016llx %016llx\n",
181 be64_to_cpu(data
->mmioErrorStatus
),
182 be64_to_cpu(data
->mmioFirstErrorStatus
),
183 be64_to_cpu(data
->mmioErrorLog0
),
184 be64_to_cpu(data
->mmioErrorLog1
));
185 if (data
->dma0ErrorStatus
)
186 pr_info("InAErr: %016llx %016llx %016llx %016llx\n",
187 be64_to_cpu(data
->dma0ErrorStatus
),
188 be64_to_cpu(data
->dma0FirstErrorStatus
),
189 be64_to_cpu(data
->dma0ErrorLog0
),
190 be64_to_cpu(data
->dma0ErrorLog1
));
191 if (data
->dma1ErrorStatus
)
192 pr_info("InBErr: %016llx %016llx %016llx %016llx\n",
193 be64_to_cpu(data
->dma1ErrorStatus
),
194 be64_to_cpu(data
->dma1FirstErrorStatus
),
195 be64_to_cpu(data
->dma1ErrorLog0
),
196 be64_to_cpu(data
->dma1ErrorLog1
));
198 for (i
= 0; i
< OPAL_P7IOC_NUM_PEST_REGS
; i
++) {
199 if ((data
->pestA
[i
] >> 63) == 0 &&
200 (data
->pestB
[i
] >> 63) == 0)
203 pr_info("PE[%3d] A/B: %016llx %016llx\n",
204 i
, be64_to_cpu(data
->pestA
[i
]),
205 be64_to_cpu(data
->pestB
[i
]));
209 static void pnv_pci_dump_phb3_diag_data(struct pci_controller
*hose
,
210 struct OpalIoPhbErrorCommon
*common
)
212 struct OpalIoPhb3ErrorData
*data
;
215 data
= (struct OpalIoPhb3ErrorData
*)common
;
216 pr_info("PHB3 PHB#%d Diag-data (Version: %d)\n",
217 hose
->global_number
, be32_to_cpu(common
->version
));
219 pr_info("brdgCtl: %08x\n",
220 be32_to_cpu(data
->brdgCtl
));
221 if (data
->portStatusReg
|| data
->rootCmplxStatus
||
222 data
->busAgentStatus
)
223 pr_info("UtlSts: %08x %08x %08x\n",
224 be32_to_cpu(data
->portStatusReg
),
225 be32_to_cpu(data
->rootCmplxStatus
),
226 be32_to_cpu(data
->busAgentStatus
));
227 if (data
->deviceStatus
|| data
->slotStatus
||
228 data
->linkStatus
|| data
->devCmdStatus
||
230 pr_info("RootSts: %08x %08x %08x %08x %08x\n",
231 be32_to_cpu(data
->deviceStatus
),
232 be32_to_cpu(data
->slotStatus
),
233 be32_to_cpu(data
->linkStatus
),
234 be32_to_cpu(data
->devCmdStatus
),
235 be32_to_cpu(data
->devSecStatus
));
236 if (data
->rootErrorStatus
|| data
->uncorrErrorStatus
||
237 data
->corrErrorStatus
)
238 pr_info("RootErrSts: %08x %08x %08x\n",
239 be32_to_cpu(data
->rootErrorStatus
),
240 be32_to_cpu(data
->uncorrErrorStatus
),
241 be32_to_cpu(data
->corrErrorStatus
));
242 if (data
->tlpHdr1
|| data
->tlpHdr2
||
243 data
->tlpHdr3
|| data
->tlpHdr4
)
244 pr_info("RootErrLog: %08x %08x %08x %08x\n",
245 be32_to_cpu(data
->tlpHdr1
),
246 be32_to_cpu(data
->tlpHdr2
),
247 be32_to_cpu(data
->tlpHdr3
),
248 be32_to_cpu(data
->tlpHdr4
));
249 if (data
->sourceId
|| data
->errorClass
||
251 pr_info("RootErrLog1: %08x %016llx %016llx\n",
252 be32_to_cpu(data
->sourceId
),
253 be64_to_cpu(data
->errorClass
),
254 be64_to_cpu(data
->correlator
));
256 pr_info("nFir: %016llx %016llx %016llx\n",
257 be64_to_cpu(data
->nFir
),
258 be64_to_cpu(data
->nFirMask
),
259 be64_to_cpu(data
->nFirWOF
));
260 if (data
->phbPlssr
|| data
->phbCsr
)
261 pr_info("PhbSts: %016llx %016llx\n",
262 be64_to_cpu(data
->phbPlssr
),
263 be64_to_cpu(data
->phbCsr
));
265 pr_info("Lem: %016llx %016llx %016llx\n",
266 be64_to_cpu(data
->lemFir
),
267 be64_to_cpu(data
->lemErrorMask
),
268 be64_to_cpu(data
->lemWOF
));
269 if (data
->phbErrorStatus
)
270 pr_info("PhbErr: %016llx %016llx %016llx %016llx\n",
271 be64_to_cpu(data
->phbErrorStatus
),
272 be64_to_cpu(data
->phbFirstErrorStatus
),
273 be64_to_cpu(data
->phbErrorLog0
),
274 be64_to_cpu(data
->phbErrorLog1
));
275 if (data
->mmioErrorStatus
)
276 pr_info("OutErr: %016llx %016llx %016llx %016llx\n",
277 be64_to_cpu(data
->mmioErrorStatus
),
278 be64_to_cpu(data
->mmioFirstErrorStatus
),
279 be64_to_cpu(data
->mmioErrorLog0
),
280 be64_to_cpu(data
->mmioErrorLog1
));
281 if (data
->dma0ErrorStatus
)
282 pr_info("InAErr: %016llx %016llx %016llx %016llx\n",
283 be64_to_cpu(data
->dma0ErrorStatus
),
284 be64_to_cpu(data
->dma0FirstErrorStatus
),
285 be64_to_cpu(data
->dma0ErrorLog0
),
286 be64_to_cpu(data
->dma0ErrorLog1
));
287 if (data
->dma1ErrorStatus
)
288 pr_info("InBErr: %016llx %016llx %016llx %016llx\n",
289 be64_to_cpu(data
->dma1ErrorStatus
),
290 be64_to_cpu(data
->dma1FirstErrorStatus
),
291 be64_to_cpu(data
->dma1ErrorLog0
),
292 be64_to_cpu(data
->dma1ErrorLog1
));
294 for (i
= 0; i
< OPAL_PHB3_NUM_PEST_REGS
; i
++) {
295 if ((be64_to_cpu(data
->pestA
[i
]) >> 63) == 0 &&
296 (be64_to_cpu(data
->pestB
[i
]) >> 63) == 0)
299 pr_info("PE[%3d] A/B: %016llx %016llx\n",
300 i
, be64_to_cpu(data
->pestA
[i
]),
301 be64_to_cpu(data
->pestB
[i
]));
305 void pnv_pci_dump_phb_diag_data(struct pci_controller
*hose
,
306 unsigned char *log_buff
)
308 struct OpalIoPhbErrorCommon
*common
;
310 if (!hose
|| !log_buff
)
313 common
= (struct OpalIoPhbErrorCommon
*)log_buff
;
314 switch (be32_to_cpu(common
->ioType
)) {
315 case OPAL_PHB_ERROR_DATA_TYPE_P7IOC
:
316 pnv_pci_dump_p7ioc_diag_data(hose
, common
);
318 case OPAL_PHB_ERROR_DATA_TYPE_PHB3
:
319 pnv_pci_dump_phb3_diag_data(hose
, common
);
322 pr_warn("%s: Unrecognized ioType %d\n",
323 __func__
, be32_to_cpu(common
->ioType
));
327 static void pnv_pci_handle_eeh_config(struct pnv_phb
*phb
, u32 pe_no
)
329 unsigned long flags
, rc
;
330 int has_diag
, ret
= 0;
332 spin_lock_irqsave(&phb
->lock
, flags
);
334 /* Fetch PHB diag-data */
335 rc
= opal_pci_get_phb_diag_data2(phb
->opal_id
, phb
->diag
.blob
,
336 PNV_PCI_DIAG_BUF_SIZE
);
337 has_diag
= (rc
== OPAL_SUCCESS
);
339 /* If PHB supports compound PE, to handle it */
340 if (phb
->unfreeze_pe
) {
341 ret
= phb
->unfreeze_pe(phb
,
343 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL
);
345 rc
= opal_pci_eeh_freeze_clear(phb
->opal_id
,
347 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL
);
349 pr_warn("%s: Failure %ld clearing frozen "
351 __func__
, rc
, phb
->hose
->global_number
,
358 * For now, let's only display the diag buffer when we fail to clear
359 * the EEH status. We'll do more sensible things later when we have
360 * proper EEH support. We need to make sure we don't pollute ourselves
361 * with the normal errors generated when probing empty slots
364 pnv_pci_dump_phb_diag_data(phb
->hose
, phb
->diag
.blob
);
366 spin_unlock_irqrestore(&phb
->lock
, flags
);
369 static void pnv_pci_config_check_eeh(struct pnv_phb
*phb
,
370 struct device_node
*dn
)
378 * Get the PE#. During the PCI probe stage, we might not
379 * setup that yet. So all ER errors should be mapped to
382 pe_no
= PCI_DN(dn
)->pe_number
;
383 if (pe_no
== IODA_INVALID_PE
) {
384 if (phb
->type
== PNV_PHB_P5IOC2
)
387 pe_no
= phb
->ioda
.reserved_pe
;
391 * Fetch frozen state. If the PHB support compound PE,
392 * we need handle that case.
394 if (phb
->get_pe_state
) {
395 fstate
= phb
->get_pe_state(phb
, pe_no
);
397 rc
= opal_pci_eeh_freeze_status(phb
->opal_id
,
403 pr_warn("%s: Failure %lld getting PHB#%x-PE#%x state\n",
404 __func__
, rc
, phb
->hose
->global_number
, pe_no
);
409 cfg_dbg(" -> EEH check, bdfn=%04x PE#%d fstate=%x\n",
410 (PCI_DN(dn
)->busno
<< 8) | (PCI_DN(dn
)->devfn
),
413 /* Clear the frozen state if applicable */
414 if (fstate
== OPAL_EEH_STOPPED_MMIO_FREEZE
||
415 fstate
== OPAL_EEH_STOPPED_DMA_FREEZE
||
416 fstate
== OPAL_EEH_STOPPED_MMIO_DMA_FREEZE
) {
418 * If PHB supports compound PE, freeze it for
422 phb
->freeze_pe(phb
, pe_no
);
424 pnv_pci_handle_eeh_config(phb
, pe_no
);
428 int pnv_pci_cfg_read(struct device_node
*dn
,
429 int where
, int size
, u32
*val
)
431 struct pci_dn
*pdn
= PCI_DN(dn
);
432 struct pnv_phb
*phb
= pdn
->phb
->private_data
;
433 u32 bdfn
= (pdn
->busno
<< 8) | pdn
->devfn
;
439 rc
= opal_pci_config_read_byte(phb
->opal_id
, bdfn
, where
, &v8
);
440 *val
= (rc
== OPAL_SUCCESS
) ? v8
: 0xff;
445 rc
= opal_pci_config_read_half_word(phb
->opal_id
, bdfn
, where
,
447 *val
= (rc
== OPAL_SUCCESS
) ? be16_to_cpu(v16
) : 0xffff;
452 rc
= opal_pci_config_read_word(phb
->opal_id
, bdfn
, where
, &v32
);
453 *val
= (rc
== OPAL_SUCCESS
) ? be32_to_cpu(v32
) : 0xffffffff;
457 return PCIBIOS_FUNC_NOT_SUPPORTED
;
460 cfg_dbg("%s: bus: %x devfn: %x +%x/%x -> %08x\n",
461 __func__
, pdn
->busno
, pdn
->devfn
, where
, size
, *val
);
462 return PCIBIOS_SUCCESSFUL
;
465 int pnv_pci_cfg_write(struct device_node
*dn
,
466 int where
, int size
, u32 val
)
468 struct pci_dn
*pdn
= PCI_DN(dn
);
469 struct pnv_phb
*phb
= pdn
->phb
->private_data
;
470 u32 bdfn
= (pdn
->busno
<< 8) | pdn
->devfn
;
472 cfg_dbg("%s: bus: %x devfn: %x +%x/%x -> %08x\n",
473 pdn
->busno
, pdn
->devfn
, where
, size
, val
);
476 opal_pci_config_write_byte(phb
->opal_id
, bdfn
, where
, val
);
479 opal_pci_config_write_half_word(phb
->opal_id
, bdfn
, where
, val
);
482 opal_pci_config_write_word(phb
->opal_id
, bdfn
, where
, val
);
485 return PCIBIOS_FUNC_NOT_SUPPORTED
;
488 return PCIBIOS_SUCCESSFUL
;
492 static bool pnv_pci_cfg_check(struct pci_controller
*hose
,
493 struct device_node
*dn
)
495 struct eeh_dev
*edev
= NULL
;
496 struct pnv_phb
*phb
= hose
->private_data
;
498 /* EEH not enabled ? */
499 if (!(phb
->flags
& PNV_PHB_FLAG_EEH
))
502 /* PE reset or device removed ? */
503 edev
= of_node_to_eeh_dev(dn
);
506 (edev
->pe
->state
& EEH_PE_CFG_BLOCKED
))
509 if (edev
->mode
& EEH_DEV_REMOVED
)
516 static inline pnv_pci_cfg_check(struct pci_controller
*hose
,
517 struct device_node
*dn
)
521 #endif /* CONFIG_EEH */
523 static int pnv_pci_read_config(struct pci_bus
*bus
,
525 int where
, int size
, u32
*val
)
527 struct device_node
*dn
, *busdn
= pci_bus_to_OF_node(bus
);
534 for (dn
= busdn
->child
; dn
; dn
= dn
->sibling
) {
536 if (pdn
&& pdn
->devfn
== devfn
) {
537 phb
= pdn
->phb
->private_data
;
543 if (!found
|| !pnv_pci_cfg_check(pdn
->phb
, dn
))
544 return PCIBIOS_DEVICE_NOT_FOUND
;
546 ret
= pnv_pci_cfg_read(dn
, where
, size
, val
);
547 if (phb
->flags
& PNV_PHB_FLAG_EEH
) {
548 if (*val
== EEH_IO_ERROR_VALUE(size
) &&
549 eeh_dev_check_failure(of_node_to_eeh_dev(dn
)))
550 return PCIBIOS_DEVICE_NOT_FOUND
;
552 pnv_pci_config_check_eeh(phb
, dn
);
558 static int pnv_pci_write_config(struct pci_bus
*bus
,
560 int where
, int size
, u32 val
)
562 struct device_node
*dn
, *busdn
= pci_bus_to_OF_node(bus
);
568 for (dn
= busdn
->child
; dn
; dn
= dn
->sibling
) {
570 if (pdn
&& pdn
->devfn
== devfn
) {
571 phb
= pdn
->phb
->private_data
;
577 if (!found
|| !pnv_pci_cfg_check(pdn
->phb
, dn
))
578 return PCIBIOS_DEVICE_NOT_FOUND
;
580 ret
= pnv_pci_cfg_write(dn
, where
, size
, val
);
581 if (!(phb
->flags
& PNV_PHB_FLAG_EEH
))
582 pnv_pci_config_check_eeh(phb
, dn
);
587 struct pci_ops pnv_pci_ops
= {
588 .read
= pnv_pci_read_config
,
589 .write
= pnv_pci_write_config
,
592 static int pnv_tce_build(struct iommu_table
*tbl
, long index
, long npages
,
593 unsigned long uaddr
, enum dma_data_direction direction
,
594 struct dma_attrs
*attrs
, bool rm
)
600 proto_tce
= TCE_PCI_READ
; // Read allowed
602 if (direction
!= DMA_TO_DEVICE
)
603 proto_tce
|= TCE_PCI_WRITE
;
605 tces
= tcep
= ((__be64
*)tbl
->it_base
) + index
- tbl
->it_offset
;
606 rpn
= __pa(uaddr
) >> tbl
->it_page_shift
;
609 *(tcep
++) = cpu_to_be64(proto_tce
|
610 (rpn
++ << tbl
->it_page_shift
));
612 /* Some implementations won't cache invalid TCEs and thus may not
613 * need that flush. We'll probably turn it_type into a bit mask
614 * of flags if that becomes the case
616 if (tbl
->it_type
& TCE_PCI_SWINV_CREATE
)
617 pnv_pci_ioda_tce_invalidate(tbl
, tces
, tcep
- 1, rm
);
622 static int pnv_tce_build_vm(struct iommu_table
*tbl
, long index
, long npages
,
624 enum dma_data_direction direction
,
625 struct dma_attrs
*attrs
)
627 return pnv_tce_build(tbl
, index
, npages
, uaddr
, direction
, attrs
,
631 static void pnv_tce_free(struct iommu_table
*tbl
, long index
, long npages
,
636 tces
= tcep
= ((__be64
*)tbl
->it_base
) + index
- tbl
->it_offset
;
639 *(tcep
++) = cpu_to_be64(0);
641 if (tbl
->it_type
& TCE_PCI_SWINV_FREE
)
642 pnv_pci_ioda_tce_invalidate(tbl
, tces
, tcep
- 1, rm
);
645 static void pnv_tce_free_vm(struct iommu_table
*tbl
, long index
, long npages
)
647 pnv_tce_free(tbl
, index
, npages
, false);
650 static unsigned long pnv_tce_get(struct iommu_table
*tbl
, long index
)
652 return ((u64
*)tbl
->it_base
)[index
- tbl
->it_offset
];
655 static int pnv_tce_build_rm(struct iommu_table
*tbl
, long index
, long npages
,
657 enum dma_data_direction direction
,
658 struct dma_attrs
*attrs
)
660 return pnv_tce_build(tbl
, index
, npages
, uaddr
, direction
, attrs
, true);
663 static void pnv_tce_free_rm(struct iommu_table
*tbl
, long index
, long npages
)
665 pnv_tce_free(tbl
, index
, npages
, true);
668 void pnv_pci_setup_iommu_table(struct iommu_table
*tbl
,
669 void *tce_mem
, u64 tce_size
,
670 u64 dma_offset
, unsigned page_shift
)
672 tbl
->it_blocksize
= 16;
673 tbl
->it_base
= (unsigned long)tce_mem
;
674 tbl
->it_page_shift
= page_shift
;
675 tbl
->it_offset
= dma_offset
>> tbl
->it_page_shift
;
677 tbl
->it_size
= tce_size
>> 3;
679 tbl
->it_type
= TCE_PCI
;
682 static struct iommu_table
*pnv_pci_setup_bml_iommu(struct pci_controller
*hose
)
684 struct iommu_table
*tbl
;
685 const __be64
*basep
, *swinvp
;
688 basep
= of_get_property(hose
->dn
, "linux,tce-base", NULL
);
689 sizep
= of_get_property(hose
->dn
, "linux,tce-size", NULL
);
690 if (basep
== NULL
|| sizep
== NULL
) {
691 pr_err("PCI: %s has missing tce entries !\n",
692 hose
->dn
->full_name
);
695 tbl
= kzalloc_node(sizeof(struct iommu_table
), GFP_KERNEL
, hose
->node
);
698 pnv_pci_setup_iommu_table(tbl
, __va(be64_to_cpup(basep
)),
699 be32_to_cpup(sizep
), 0, IOMMU_PAGE_SHIFT_4K
);
700 iommu_init_table(tbl
, hose
->node
);
701 iommu_register_group(tbl
, pci_domain_nr(hose
->bus
), 0);
703 /* Deal with SW invalidated TCEs when needed (BML way) */
704 swinvp
= of_get_property(hose
->dn
, "linux,tce-sw-invalidate-info",
707 tbl
->it_busno
= be64_to_cpu(swinvp
[1]);
708 tbl
->it_index
= (unsigned long)ioremap(be64_to_cpup(swinvp
), 8);
709 tbl
->it_type
= TCE_PCI_SWINV_CREATE
| TCE_PCI_SWINV_FREE
;
714 static void pnv_pci_dma_fallback_setup(struct pci_controller
*hose
,
715 struct pci_dev
*pdev
)
717 struct device_node
*np
= pci_bus_to_OF_node(hose
->bus
);
723 if (!pdn
->iommu_table
)
724 pdn
->iommu_table
= pnv_pci_setup_bml_iommu(hose
);
725 if (!pdn
->iommu_table
)
727 set_iommu_table_base_and_group(&pdev
->dev
, pdn
->iommu_table
);
730 static void pnv_pci_dma_dev_setup(struct pci_dev
*pdev
)
732 struct pci_controller
*hose
= pci_bus_to_host(pdev
->bus
);
733 struct pnv_phb
*phb
= hose
->private_data
;
735 /* If we have no phb structure, try to setup a fallback based on
736 * the device-tree (RTAS PCI for example)
738 if (phb
&& phb
->dma_dev_setup
)
739 phb
->dma_dev_setup(phb
, pdev
);
741 pnv_pci_dma_fallback_setup(hose
, pdev
);
744 int pnv_pci_dma_set_mask(struct pci_dev
*pdev
, u64 dma_mask
)
746 struct pci_controller
*hose
= pci_bus_to_host(pdev
->bus
);
747 struct pnv_phb
*phb
= hose
->private_data
;
749 if (phb
&& phb
->dma_set_mask
)
750 return phb
->dma_set_mask(phb
, pdev
, dma_mask
);
751 return __dma_set_mask(&pdev
->dev
, dma_mask
);
754 u64
pnv_pci_dma_get_required_mask(struct pci_dev
*pdev
)
756 struct pci_controller
*hose
= pci_bus_to_host(pdev
->bus
);
757 struct pnv_phb
*phb
= hose
->private_data
;
759 if (phb
&& phb
->dma_get_required_mask
)
760 return phb
->dma_get_required_mask(phb
, pdev
);
762 return __dma_get_required_mask(&pdev
->dev
);
765 void pnv_pci_shutdown(void)
767 struct pci_controller
*hose
;
769 list_for_each_entry(hose
, &hose_list
, list_node
) {
770 struct pnv_phb
*phb
= hose
->private_data
;
772 if (phb
&& phb
->shutdown
)
777 /* Fixup wrong class code in p7ioc and p8 root complex */
778 static void pnv_p7ioc_rc_quirk(struct pci_dev
*dev
)
780 dev
->class = PCI_CLASS_BRIDGE_PCI
<< 8;
782 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_IBM
, 0x3b9, pnv_p7ioc_rc_quirk
);
784 void __init
pnv_pci_init(void)
786 struct device_node
*np
;
788 pci_add_flags(PCI_CAN_SKIP_ISA_ALIGN
);
790 /* OPAL absent, try POPAL first then RTAS detection of PHBs */
791 if (!firmware_has_feature(FW_FEATURE_OPAL
)) {
792 #ifdef CONFIG_PPC_POWERNV_RTAS
793 init_pci_config_tokens();
794 find_and_init_phbs();
795 #endif /* CONFIG_PPC_POWERNV_RTAS */
797 /* OPAL is here, do our normal stuff */
801 /* Look for IODA IO-Hubs. We don't support mixing IODA
802 * and p5ioc2 due to the need to change some global
805 for_each_compatible_node(np
, NULL
, "ibm,ioda-hub") {
806 pnv_pci_init_ioda_hub(np
);
810 /* Look for p5ioc2 IO-Hubs */
812 for_each_compatible_node(np
, NULL
, "ibm,p5ioc2")
813 pnv_pci_init_p5ioc2_hub(np
);
815 /* Look for ioda2 built-in PHB3's */
816 for_each_compatible_node(np
, NULL
, "ibm,ioda2-phb")
817 pnv_pci_init_ioda2_phb(np
);
820 /* Setup the linkage between OF nodes and PHBs */
823 /* Configure IOMMU DMA hooks */
824 ppc_md
.pci_dma_dev_setup
= pnv_pci_dma_dev_setup
;
825 ppc_md
.tce_build
= pnv_tce_build_vm
;
826 ppc_md
.tce_free
= pnv_tce_free_vm
;
827 ppc_md
.tce_build_rm
= pnv_tce_build_rm
;
828 ppc_md
.tce_free_rm
= pnv_tce_free_rm
;
829 ppc_md
.tce_get
= pnv_tce_get
;
830 set_pci_dma_ops(&dma_iommu_ops
);
833 #ifdef CONFIG_PCI_MSI
834 ppc_md
.setup_msi_irqs
= pnv_setup_msi_irqs
;
835 ppc_md
.teardown_msi_irqs
= pnv_teardown_msi_irqs
;
839 machine_subsys_initcall_sync(powernv
, tce_iommu_bus_notifier_init
);