projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
powerpc/eeh: Enable EEH check for config access
[deliverable/linux.git] / arch / powerpc / platforms / powernv / pci.c
1 /*
2 * Support PCI/PCIe on PowerNV platforms
3 *
4 * Currently supports only P5IOC2
5 *
6 * Copyright 2011 Benjamin Herrenschmidt, IBM Corp.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
12 */
13
14 #include <linux/kernel.h>
15 #include <linux/pci.h>
16 #include <linux/delay.h>
17 #include <linux/string.h>
18 #include <linux/init.h>
19 #include <linux/bootmem.h>
20 #include <linux/irq.h>
21 #include <linux/io.h>
22 #include <linux/msi.h>
23 #include <linux/iommu.h>
24
25 #include <asm/sections.h>
26 #include <asm/io.h>
27 #include <asm/prom.h>
28 #include <asm/pci-bridge.h>
29 #include <asm/machdep.h>
30 #include <asm/msi_bitmap.h>
31 #include <asm/ppc-pci.h>
32 #include <asm/opal.h>
33 #include <asm/iommu.h>
34 #include <asm/tce.h>
35 #include <asm/firmware.h>
36 #include <asm/eeh_event.h>
37 #include <asm/eeh.h>
38
39 #include "powernv.h"
40 #include "pci.h"
41
42 /* Delay in usec */
43 #define PCI_RESET_DELAY_US 3000000
44
45 #define cfg_dbg(fmt...) do { } while(0)
46 //#define cfg_dbg(fmt...) printk(fmt)
47
48 #ifdef CONFIG_PCI_MSI
49 static int pnv_msi_check_device(struct pci_dev* pdev, int nvec, int type)
50 {
51 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
52 struct pnv_phb *phb = hose->private_data;
53 struct pci_dn *pdn = pci_get_pdn(pdev);
54
55 if (pdn && pdn->force_32bit_msi && !phb->msi32_support)
56 return -ENODEV;
57
58 return (phb && phb->msi_bmp.bitmap) ? 0 : -ENODEV;
59 }
60
61 static int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
62 {
63 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
64 struct pnv_phb *phb = hose->private_data;
65 struct msi_desc *entry;
66 struct msi_msg msg;
67 int hwirq;
68 unsigned int virq;
69 int rc;
70
71 if (WARN_ON(!phb))
72 return -ENODEV;
73
74 list_for_each_entry(entry, &pdev->msi_list, list) {
75 if (!entry->msi_attrib.is_64 && !phb->msi32_support) {
76 pr_warn("%s: Supports only 64-bit MSIs\n",
77 pci_name(pdev));
78 return -ENXIO;
79 }
80 hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, 1);
81 if (hwirq < 0) {
82 pr_warn("%s: Failed to find a free MSI\n",
83 pci_name(pdev));
84 return -ENOSPC;
85 }
86 virq = irq_create_mapping(NULL, phb->msi_base + hwirq);
87 if (virq == NO_IRQ) {
88 pr_warn("%s: Failed to map MSI to linux irq\n",
89 pci_name(pdev));
90 msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, 1);
91 return -ENOMEM;
92 }
93 rc = phb->msi_setup(phb, pdev, phb->msi_base + hwirq,
94 virq, entry->msi_attrib.is_64, &msg);
95 if (rc) {
96 pr_warn("%s: Failed to setup MSI\n", pci_name(pdev));
97 irq_dispose_mapping(virq);
98 msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, 1);
99 return rc;
100 }
101 irq_set_msi_desc(virq, entry);
102 write_msi_msg(virq, &msg);
103 }
104 return 0;
105 }
106
107 static void pnv_teardown_msi_irqs(struct pci_dev *pdev)
108 {
109 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
110 struct pnv_phb *phb = hose->private_data;
111 struct msi_desc *entry;
112
113 if (WARN_ON(!phb))
114 return;
115
116 list_for_each_entry(entry, &pdev->msi_list, list) {
117 if (entry->irq == NO_IRQ)
118 continue;
119 irq_set_msi_desc(entry->irq, NULL);
120 msi_bitmap_free_hwirqs(&phb->msi_bmp,
121 virq_to_hw(entry->irq) - phb->msi_base, 1);
122 irq_dispose_mapping(entry->irq);
123 }
124 }
125 #endif /* CONFIG_PCI_MSI */
126
127 static void pnv_pci_dump_p7ioc_diag_data(struct pnv_phb *phb)
128 {
129 struct OpalIoP7IOCPhbErrorData *data = &phb->diag.p7ioc;
130 int i;
131
132 pr_info("PHB %d diagnostic data:\n", phb->hose->global_number);
133
134 pr_info(" brdgCtl = 0x%08x\n", data->brdgCtl);
135
136 pr_info(" portStatusReg = 0x%08x\n", data->portStatusReg);
137 pr_info(" rootCmplxStatus = 0x%08x\n", data->rootCmplxStatus);
138 pr_info(" busAgentStatus = 0x%08x\n", data->busAgentStatus);
139
140 pr_info(" deviceStatus = 0x%08x\n", data->deviceStatus);
141 pr_info(" slotStatus = 0x%08x\n", data->slotStatus);
142 pr_info(" linkStatus = 0x%08x\n", data->linkStatus);
143 pr_info(" devCmdStatus = 0x%08x\n", data->devCmdStatus);
144 pr_info(" devSecStatus = 0x%08x\n", data->devSecStatus);
145
146 pr_info(" rootErrorStatus = 0x%08x\n", data->rootErrorStatus);
147 pr_info(" uncorrErrorStatus = 0x%08x\n", data->uncorrErrorStatus);
148 pr_info(" corrErrorStatus = 0x%08x\n", data->corrErrorStatus);
149 pr_info(" tlpHdr1 = 0x%08x\n", data->tlpHdr1);
150 pr_info(" tlpHdr2 = 0x%08x\n", data->tlpHdr2);
151 pr_info(" tlpHdr3 = 0x%08x\n", data->tlpHdr3);
152 pr_info(" tlpHdr4 = 0x%08x\n", data->tlpHdr4);
153 pr_info(" sourceId = 0x%08x\n", data->sourceId);
154
155 pr_info(" errorClass = 0x%016llx\n", data->errorClass);
156 pr_info(" correlator = 0x%016llx\n", data->correlator);
157
158 pr_info(" p7iocPlssr = 0x%016llx\n", data->p7iocPlssr);
159 pr_info(" p7iocCsr = 0x%016llx\n", data->p7iocCsr);
160 pr_info(" lemFir = 0x%016llx\n", data->lemFir);
161 pr_info(" lemErrorMask = 0x%016llx\n", data->lemErrorMask);
162 pr_info(" lemWOF = 0x%016llx\n", data->lemWOF);
163 pr_info(" phbErrorStatus = 0x%016llx\n", data->phbErrorStatus);
164 pr_info(" phbFirstErrorStatus = 0x%016llx\n", data->phbFirstErrorStatus);
165 pr_info(" phbErrorLog0 = 0x%016llx\n", data->phbErrorLog0);
166 pr_info(" phbErrorLog1 = 0x%016llx\n", data->phbErrorLog1);
167 pr_info(" mmioErrorStatus = 0x%016llx\n", data->mmioErrorStatus);
168 pr_info(" mmioFirstErrorStatus = 0x%016llx\n", data->mmioFirstErrorStatus);
169 pr_info(" mmioErrorLog0 = 0x%016llx\n", data->mmioErrorLog0);
170 pr_info(" mmioErrorLog1 = 0x%016llx\n", data->mmioErrorLog1);
171 pr_info(" dma0ErrorStatus = 0x%016llx\n", data->dma0ErrorStatus);
172 pr_info(" dma0FirstErrorStatus = 0x%016llx\n", data->dma0FirstErrorStatus);
173 pr_info(" dma0ErrorLog0 = 0x%016llx\n", data->dma0ErrorLog0);
174 pr_info(" dma0ErrorLog1 = 0x%016llx\n", data->dma0ErrorLog1);
175 pr_info(" dma1ErrorStatus = 0x%016llx\n", data->dma1ErrorStatus);
176 pr_info(" dma1FirstErrorStatus = 0x%016llx\n", data->dma1FirstErrorStatus);
177 pr_info(" dma1ErrorLog0 = 0x%016llx\n", data->dma1ErrorLog0);
178 pr_info(" dma1ErrorLog1 = 0x%016llx\n", data->dma1ErrorLog1);
179
180 for (i = 0; i < OPAL_P7IOC_NUM_PEST_REGS; i++) {
181 if ((data->pestA[i] >> 63) == 0 &&
182 (data->pestB[i] >> 63) == 0)
183 continue;
184 pr_info(" PE[%3d] PESTA = 0x%016llx\n", i, data->pestA[i]);
185 pr_info(" PESTB = 0x%016llx\n", data->pestB[i]);
186 }
187 }
188
189 static void pnv_pci_dump_phb_diag_data(struct pnv_phb *phb)
190 {
191 switch(phb->model) {
192 case PNV_PHB_MODEL_P7IOC:
193 pnv_pci_dump_p7ioc_diag_data(phb);
194 break;
195 default:
196 pr_warning("PCI %d: Can't decode this PHB diag data\n",
197 phb->hose->global_number);
198 }
199 }
200
201 static void pnv_pci_handle_eeh_config(struct pnv_phb *phb, u32 pe_no)
202 {
203 unsigned long flags, rc;
204 int has_diag;
205
206 spin_lock_irqsave(&phb->lock, flags);
207
208 rc = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag.blob,
209 PNV_PCI_DIAG_BUF_SIZE);
210 has_diag = (rc == OPAL_SUCCESS);
211
212 rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no,
213 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
214 if (rc) {
215 pr_warning("PCI %d: Failed to clear EEH freeze state"
216 " for PE#%d, err %ld\n",
217 phb->hose->global_number, pe_no, rc);
218
219 /* For now, let's only display the diag buffer when we fail to clear
220 * the EEH status. We'll do more sensible things later when we have
221 * proper EEH support. We need to make sure we don't pollute ourselves
222 * with the normal errors generated when probing empty slots
223 */
224 if (has_diag)
225 pnv_pci_dump_phb_diag_data(phb);
226 else
227 pr_warning("PCI %d: No diag data available\n",
228 phb->hose->global_number);
229 }
230
231 spin_unlock_irqrestore(&phb->lock, flags);
232 }
233
234 static void pnv_pci_config_check_eeh(struct pnv_phb *phb, struct pci_bus *bus,
235 u32 bdfn)
236 {
237 s64 rc;
238 u8 fstate;
239 u16 pcierr;
240 u32 pe_no;
241
242 /* Get PE# if we support IODA */
243 pe_no = phb->bdfn_to_pe ? phb->bdfn_to_pe(phb, bus, bdfn & 0xff) : 0;
244
245 /* Read freeze status */
246 rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no, &fstate, &pcierr,
247 NULL);
248 if (rc) {
249 pr_warning("PCI %d: Failed to read EEH status for PE#%d,"
250 " err %lld\n", phb->hose->global_number, pe_no, rc);
251 return;
252 }
253 cfg_dbg(" -> EEH check, bdfn=%04x PE%d fstate=%x\n",
254 bdfn, pe_no, fstate);
255 if (fstate != 0)
256 pnv_pci_handle_eeh_config(phb, pe_no);
257 }
258
259 static int pnv_pci_read_config(struct pci_bus *bus,
260 unsigned int devfn,
261 int where, int size, u32 *val)
262 {
263 struct pci_controller *hose = pci_bus_to_host(bus);
264 struct pnv_phb *phb = hose->private_data;
265 #ifdef CONFIG_EEH
266 struct device_node *busdn, *dn;
267 struct eeh_pe *phb_pe = NULL;
268 #endif
269 u32 bdfn = (((uint64_t)bus->number) << 8) | devfn;
270 s64 rc;
271
272 if (hose == NULL)
273 return PCIBIOS_DEVICE_NOT_FOUND;
274
275 switch (size) {
276 case 1: {
277 u8 v8;
278 rc = opal_pci_config_read_byte(phb->opal_id, bdfn, where, &v8);
279 *val = (rc == OPAL_SUCCESS) ? v8 : 0xff;
280 break;
281 }
282 case 2: {
283 u16 v16;
284 rc = opal_pci_config_read_half_word(phb->opal_id, bdfn, where,
285 &v16);
286 *val = (rc == OPAL_SUCCESS) ? v16 : 0xffff;
287 break;
288 }
289 case 4: {
290 u32 v32;
291 rc = opal_pci_config_read_word(phb->opal_id, bdfn, where, &v32);
292 *val = (rc == OPAL_SUCCESS) ? v32 : 0xffffffff;
293 break;
294 }
295 default:
296 return PCIBIOS_FUNC_NOT_SUPPORTED;
297 }
298 cfg_dbg("pnv_pci_read_config bus: %x devfn: %x +%x/%x -> %08x\n",
299 bus->number, devfn, where, size, *val);
300
301 /*
302 * Check if the specified PE has been put into frozen
303 * state. On the other hand, we needn't do that while
304 * the PHB has been put into frozen state because of
305 * PHB-fatal errors.
306 */
307 #ifdef CONFIG_EEH
308 phb_pe = eeh_phb_pe_get(hose);
309 if (phb_pe && (phb_pe->state & EEH_PE_ISOLATED))
310 return PCIBIOS_SUCCESSFUL;
311
312 if (phb->eeh_enabled) {
313 if (*val == EEH_IO_ERROR_VALUE(size)) {
314 busdn = pci_bus_to_OF_node(bus);
315 for (dn = busdn->child; dn; dn = dn->sibling) {
316 struct pci_dn *pdn = PCI_DN(dn);
317
318 if (pdn && pdn->devfn == devfn &&
319 eeh_dev_check_failure(of_node_to_eeh_dev(dn)))
320 return PCIBIOS_DEVICE_NOT_FOUND;
321 }
322 }
323 } else {
324 pnv_pci_config_check_eeh(phb, bus, bdfn);
325 }
326 #else
327 pnv_pci_config_check_eeh(phb, bus, bdfn);
328 #endif
329
330 return PCIBIOS_SUCCESSFUL;
331 }
332
333 static int pnv_pci_write_config(struct pci_bus *bus,
334 unsigned int devfn,
335 int where, int size, u32 val)
336 {
337 struct pci_controller *hose = pci_bus_to_host(bus);
338 struct pnv_phb *phb = hose->private_data;
339 u32 bdfn = (((uint64_t)bus->number) << 8) | devfn;
340
341 if (hose == NULL)
342 return PCIBIOS_DEVICE_NOT_FOUND;
343
344 cfg_dbg("pnv_pci_write_config bus: %x devfn: %x +%x/%x -> %08x\n",
345 bus->number, devfn, where, size, val);
346 switch (size) {
347 case 1:
348 opal_pci_config_write_byte(phb->opal_id, bdfn, where, val);
349 break;
350 case 2:
351 opal_pci_config_write_half_word(phb->opal_id, bdfn, where, val);
352 break;
353 case 4:
354 opal_pci_config_write_word(phb->opal_id, bdfn, where, val);
355 break;
356 default:
357 return PCIBIOS_FUNC_NOT_SUPPORTED;
358 }
359
360 /* Check if the PHB got frozen due to an error (no response) */
361 #ifdef CONFIG_EEH
362 if (!phb->eeh_enabled)
363 pnv_pci_config_check_eeh(phb, bus, bdfn);
364 #else
365 pnv_pci_config_check_eeh(phb, bus, bdfn);
366 #endif
367
368 return PCIBIOS_SUCCESSFUL;
369 }
370
371 struct pci_ops pnv_pci_ops = {
372 .read = pnv_pci_read_config,
373 .write = pnv_pci_write_config,
374 };
375
376 static int pnv_tce_build(struct iommu_table *tbl, long index, long npages,
377 unsigned long uaddr, enum dma_data_direction direction,
378 struct dma_attrs *attrs)
379 {
380 u64 proto_tce;
381 u64 *tcep, *tces;
382 u64 rpn;
383
384 proto_tce = TCE_PCI_READ; // Read allowed
385
386 if (direction != DMA_TO_DEVICE)
387 proto_tce |= TCE_PCI_WRITE;
388
389 tces = tcep = ((u64 *)tbl->it_base) + index - tbl->it_offset;
390 rpn = __pa(uaddr) >> TCE_SHIFT;
391
392 while (npages--)
393 *(tcep++) = proto_tce | (rpn++ << TCE_RPN_SHIFT);
394
395 /* Some implementations won't cache invalid TCEs and thus may not
396 * need that flush. We'll probably turn it_type into a bit mask
397 * of flags if that becomes the case
398 */
399 if (tbl->it_type & TCE_PCI_SWINV_CREATE)
400 pnv_pci_ioda_tce_invalidate(tbl, tces, tcep - 1);
401
402 return 0;
403 }
404
405 static void pnv_tce_free(struct iommu_table *tbl, long index, long npages)
406 {
407 u64 *tcep, *tces;
408
409 tces = tcep = ((u64 *)tbl->it_base) + index - tbl->it_offset;
410
411 while (npages--)
412 *(tcep++) = 0;
413
414 if (tbl->it_type & TCE_PCI_SWINV_FREE)
415 pnv_pci_ioda_tce_invalidate(tbl, tces, tcep - 1);
416 }
417
418 static unsigned long pnv_tce_get(struct iommu_table *tbl, long index)
419 {
420 return ((u64 *)tbl->it_base)[index - tbl->it_offset];
421 }
422
423 void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
424 void *tce_mem, u64 tce_size,
425 u64 dma_offset)
426 {
427 tbl->it_blocksize = 16;
428 tbl->it_base = (unsigned long)tce_mem;
429 tbl->it_offset = dma_offset >> IOMMU_PAGE_SHIFT;
430 tbl->it_index = 0;
431 tbl->it_size = tce_size >> 3;
432 tbl->it_busno = 0;
433 tbl->it_type = TCE_PCI;
434 }
435
436 static struct iommu_table *pnv_pci_setup_bml_iommu(struct pci_controller *hose)
437 {
438 struct iommu_table *tbl;
439 const __be64 *basep, *swinvp;
440 const __be32 *sizep;
441
442 basep = of_get_property(hose->dn, "linux,tce-base", NULL);
443 sizep = of_get_property(hose->dn, "linux,tce-size", NULL);
444 if (basep == NULL || sizep == NULL) {
445 pr_err("PCI: %s has missing tce entries !\n",
446 hose->dn->full_name);
447 return NULL;
448 }
449 tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL, hose->node);
450 if (WARN_ON(!tbl))
451 return NULL;
452 pnv_pci_setup_iommu_table(tbl, __va(be64_to_cpup(basep)),
453 be32_to_cpup(sizep), 0);
454 iommu_init_table(tbl, hose->node);
455 iommu_register_group(tbl, pci_domain_nr(hose->bus), 0);
456
457 /* Deal with SW invalidated TCEs when needed (BML way) */
458 swinvp = of_get_property(hose->dn, "linux,tce-sw-invalidate-info",
459 NULL);
460 if (swinvp) {
461 tbl->it_busno = swinvp[1];
462 tbl->it_index = (unsigned long)ioremap(swinvp[0], 8);
463 tbl->it_type = TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE;
464 }
465 return tbl;
466 }
467
468 static void pnv_pci_dma_fallback_setup(struct pci_controller *hose,
469 struct pci_dev *pdev)
470 {
471 struct device_node *np = pci_bus_to_OF_node(hose->bus);
472 struct pci_dn *pdn;
473
474 if (np == NULL)
475 return;
476 pdn = PCI_DN(np);
477 if (!pdn->iommu_table)
478 pdn->iommu_table = pnv_pci_setup_bml_iommu(hose);
479 if (!pdn->iommu_table)
480 return;
481 set_iommu_table_base(&pdev->dev, pdn->iommu_table);
482 }
483
484 static void pnv_pci_dma_dev_setup(struct pci_dev *pdev)
485 {
486 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
487 struct pnv_phb *phb = hose->private_data;
488
489 /* If we have no phb structure, try to setup a fallback based on
490 * the device-tree (RTAS PCI for example)
491 */
492 if (phb && phb->dma_dev_setup)
493 phb->dma_dev_setup(phb, pdev);
494 else
495 pnv_pci_dma_fallback_setup(hose, pdev);
496 }
497
498 void pnv_pci_shutdown(void)
499 {
500 struct pci_controller *hose;
501
502 list_for_each_entry(hose, &hose_list, list_node) {
503 struct pnv_phb *phb = hose->private_data;
504
505 if (phb && phb->shutdown)
506 phb->shutdown(phb);
507 }
508 }
509
510 /* Fixup wrong class code in p7ioc and p8 root complex */
511 static void pnv_p7ioc_rc_quirk(struct pci_dev *dev)
512 {
513 dev->class = PCI_CLASS_BRIDGE_PCI << 8;
514 }
515 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_IBM, 0x3b9, pnv_p7ioc_rc_quirk);
516
517 static int pnv_pci_probe_mode(struct pci_bus *bus)
518 {
519 struct pci_controller *hose = pci_bus_to_host(bus);
520 const __be64 *tstamp;
521 u64 now, target;
522
523
524 /* We hijack this as a way to ensure we have waited long
525 * enough since the reset was lifted on the PCI bus
526 */
527 if (bus != hose->bus)
528 return PCI_PROBE_NORMAL;
529 tstamp = of_get_property(hose->dn, "reset-clear-timestamp", NULL);
530 if (!tstamp || !*tstamp)
531 return PCI_PROBE_NORMAL;
532
533 now = mftb() / tb_ticks_per_usec;
534 target = (be64_to_cpup(tstamp) / tb_ticks_per_usec)
535 + PCI_RESET_DELAY_US;
536
537 pr_devel("pci %04d: Reset target: 0x%llx now: 0x%llx\n",
538 hose->global_number, target, now);
539
540 if (now < target)
541 msleep((target - now + 999) / 1000);
542
543 return PCI_PROBE_NORMAL;
544 }
545
546 void __init pnv_pci_init(void)
547 {
548 struct device_node *np;
549
550 pci_add_flags(PCI_CAN_SKIP_ISA_ALIGN);
551
552 /* OPAL absent, try POPAL first then RTAS detection of PHBs */
553 if (!firmware_has_feature(FW_FEATURE_OPAL)) {
554 #ifdef CONFIG_PPC_POWERNV_RTAS
555 init_pci_config_tokens();
556 find_and_init_phbs();
557 #endif /* CONFIG_PPC_POWERNV_RTAS */
558 }
559 /* OPAL is here, do our normal stuff */
560 else {
561 int found_ioda = 0;
562
563 /* Look for IODA IO-Hubs. We don't support mixing IODA
564 * and p5ioc2 due to the need to change some global
565 * probing flags
566 */
567 for_each_compatible_node(np, NULL, "ibm,ioda-hub") {
568 pnv_pci_init_ioda_hub(np);
569 found_ioda = 1;
570 }
571
572 /* Look for p5ioc2 IO-Hubs */
573 if (!found_ioda)
574 for_each_compatible_node(np, NULL, "ibm,p5ioc2")
575 pnv_pci_init_p5ioc2_hub(np);
576
577 /* Look for ioda2 built-in PHB3's */
578 for_each_compatible_node(np, NULL, "ibm,ioda2-phb")
579 pnv_pci_init_ioda2_phb(np);
580 }
581
582 /* Setup the linkage between OF nodes and PHBs */
583 pci_devs_phb_init();
584
585 /* Configure IOMMU DMA hooks */
586 ppc_md.pci_dma_dev_setup = pnv_pci_dma_dev_setup;
587 ppc_md.tce_build = pnv_tce_build;
588 ppc_md.tce_free = pnv_tce_free;
589 ppc_md.tce_get = pnv_tce_get;
590 ppc_md.pci_probe_mode = pnv_pci_probe_mode;
591 set_pci_dma_ops(&dma_iommu_ops);
592
593 /* Configure MSIs */
594 #ifdef CONFIG_PCI_MSI
595 ppc_md.msi_check_device = pnv_msi_check_device;
596 ppc_md.setup_msi_irqs = pnv_setup_msi_irqs;
597 ppc_md.teardown_msi_irqs = pnv_teardown_msi_irqs;
598 #endif
599 }
Linux kernel - Deliverables
This page took 0.053721 seconds and 5 git commands to generate.