arch/powerpc/sysdev/fsl_pci.c

   1 /*
   2  * MPC83xx/85xx/86xx PCI/PCIE support routing.
   3  *
   4  * Copyright 2007,2008 Freescale Semiconductor, Inc
   5  *
   6  * Initial author: Xianghua Xiao <x.xiao@freescale.com>
   7  * Recode: ZHANG WEI <wei.zhang@freescale.com>
   8  * Rewrite the routing for Frescale PCI and PCI Express
   9  *      Roy Zang <tie-fei.zang@freescale.com>
  10  *
  11  * This program is free software; you can redistribute  it and/or modify it
  12  * under  the terms of  the GNU General  Public License as published by the
  13  * Free Software Foundation;  either version 2 of the  License, or (at your
  14  * option) any later version.
  15  */
  16 #include <linux/kernel.h>
  17 #include <linux/pci.h>
  18 #include <linux/delay.h>
  19 #include <linux/string.h>
  20 #include <linux/init.h>
  21 #include <linux/bootmem.h>
  22
  23 #include <asm/io.h>
  24 #include <asm/prom.h>
  25 #include <asm/pci-bridge.h>
  26 #include <asm/machdep.h>
  27 #include <sysdev/fsl_soc.h>
  28 #include <sysdev/fsl_pci.h>
  29
  30 #if defined(CONFIG_PPC_85xx) || defined(CONFIG_PPC_86xx)
  31 static int __init setup_one_atmu(struct ccsr_pci __iomem *pci,
  32         unsigned int index, const struct resource *res,
  33         resource_size_t offset)
  34 {
  35         resource_size_t pci_addr = res->start - offset;
  36         resource_size_t phys_addr = res->start;
  37         resource_size_t size = res->end - res->start + 1;
  38         u32 flags = 0x80044000; /* enable & mem R/W */
  39         unsigned int i;
  40
  41         pr_debug("PCI MEM resource start 0x%016llx, size 0x%016llx.\n",
  42                 (u64)res->start, (u64)size);
  43
  44         if (res->flags & IORESOURCE_PREFETCH)
  45                 flags |= 0x10000000; /* enable relaxed ordering */
  46
  47         for (i = 0; size > 0; i++) {
  48                 unsigned int bits = min(__ilog2(size),
  49                                         __ffs(pci_addr | phys_addr));
  50
  51                 if (index + i >= 5)
  52                         return -1;
  53
  54                 out_be32(&pci->pow[index + i].potar, pci_addr >> 12);
  55                 out_be32(&pci->pow[index + i].potear, (u64)pci_addr >> 44);
  56                 out_be32(&pci->pow[index + i].powbar, phys_addr >> 12);
  57                 out_be32(&pci->pow[index + i].powar, flags | (bits - 1));
  58
  59                 pci_addr += (resource_size_t)1U << bits;
  60                 phys_addr += (resource_size_t)1U << bits;
  61                 size -= (resource_size_t)1U << bits;
  62         }
  63
  64         return i;
  65 }
  66
  67 /* atmu setup for fsl pci/pcie controller */
  68 static void __init setup_pci_atmu(struct pci_controller *hose,
  69                                   struct resource *rsrc)
  70 {
  71         struct ccsr_pci __iomem *pci;
  72         int i, j, n;
  73
  74         pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n",
  75                     (u64)rsrc->start, (u64)rsrc->end - (u64)rsrc->start + 1);
  76         pci = ioremap(rsrc->start, rsrc->end - rsrc->start + 1);
  77         if (!pci) {
  78             dev_err(hose->parent, "Unable to map ATMU registers\n");
  79             return;
  80         }
  81
  82         /* Disable all windows (except powar0 since it's ignored) */
  83         for(i = 1; i < 5; i++)
  84                 out_be32(&pci->pow[i].powar, 0);
  85         for(i = 0; i < 3; i++)
  86                 out_be32(&pci->piw[i].piwar, 0);
  87
  88         /* Setup outbound MEM window */
  89         for(i = 0, j = 1; i < 3; i++) {
  90                 if (!(hose->mem_resources[i].flags & IORESOURCE_MEM))
  91                         continue;
  92
  93                 n = setup_one_atmu(pci, j, &hose->mem_resources[i],
  94                                    hose->pci_mem_offset);
  95
  96                 if (n < 0 || j >= 5) {
  97                         pr_err("Ran out of outbound PCI ATMUs for resource %d!\n", i);
  98                         hose->mem_resources[i].flags |= IORESOURCE_DISABLED;
  99                 } else
 100                         j += n;
 101         }
 102
 103         /* Setup outbound IO window */
 104         if (hose->io_resource.flags & IORESOURCE_IO) {
 105                 if (j >= 5) {
 106                         pr_err("Ran out of outbound PCI ATMUs for IO resource\n");
 107                 } else {
 108                         pr_debug("PCI IO resource start 0x%016llx, size 0x%016llx, "
 109                                  "phy base 0x%016llx.\n",
 110                                 (u64)hose->io_resource.start,
 111                                 (u64)hose->io_resource.end - (u64)hose->io_resource.start + 1,
 112                                 (u64)hose->io_base_phys);
 113                         out_be32(&pci->pow[j].potar, (hose->io_resource.start >> 12));
 114                         out_be32(&pci->pow[j].potear, 0);
 115                         out_be32(&pci->pow[j].powbar, (hose->io_base_phys >> 12));
 116                         /* Enable, IO R/W */
 117                         out_be32(&pci->pow[j].powar, 0x80088000
 118                                 | (__ilog2(hose->io_resource.end
 119                                 - hose->io_resource.start + 1) - 1));
 120                 }
 121         }
 122
 123         /* Setup 2G inbound Memory Window @ 1 */
 124         out_be32(&pci->piw[2].pitar, 0x00000000);
 125         out_be32(&pci->piw[2].piwbar,0x00000000);
 126         out_be32(&pci->piw[2].piwar, PIWAR_2G);
 127
 128         iounmap(pci);
 129 }
 130
 131 static void __init setup_pci_cmd(struct pci_controller *hose)
 132 {
 133         u16 cmd;
 134         int cap_x;
 135
 136         early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd);
 137         cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
 138                 | PCI_COMMAND_IO;
 139         early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd);
 140
 141         cap_x = early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX);
 142         if (cap_x) {
 143                 int pci_x_cmd = cap_x + PCI_X_CMD;
 144                 cmd = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
 145                         | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
 146                 early_write_config_word(hose, 0, 0, pci_x_cmd, cmd);
 147         } else {
 148                 early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
 149         }
 150 }
 151
 152 static void __init setup_pci_pcsrbar(struct pci_controller *hose)
 153 {
 154 #ifdef CONFIG_PCI_MSI
 155         phys_addr_t immr_base;
 156
 157         immr_base = get_immrbase();
 158         early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, immr_base);
 159 #endif
 160 }
 161
 162 static int fsl_pcie_bus_fixup;
 163
 164 static void __init quirk_fsl_pcie_header(struct pci_dev *dev)
 165 {
 166         /* if we aren't a PCIe don't bother */
 167         if (!pci_find_capability(dev, PCI_CAP_ID_EXP))
 168                 return ;
 169
 170         dev->class = PCI_CLASS_BRIDGE_PCI << 8;
 171         fsl_pcie_bus_fixup = 1;
 172         return ;
 173 }
 174
 175 static int __init fsl_pcie_check_link(struct pci_controller *hose)
 176 {
 177         u32 val;
 178         early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val);
 179         if (val < PCIE_LTSSM_L0)
 180                 return 1;
 181         return 0;
 182 }
 183
 184 void fsl_pcibios_fixup_bus(struct pci_bus *bus)
 185 {
 186         struct pci_controller *hose = (struct pci_controller *) bus->sysdata;
 187         int i;
 188
 189         if ((bus->parent == hose->bus) &&
 190             ((fsl_pcie_bus_fixup &&
 191               early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) ||
 192              (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK)))
 193         {
 194                 for (i = 0; i < 4; ++i) {
 195                         struct resource *res = bus->resource[i];
 196                         struct resource *par = bus->parent->resource[i];
 197                         if (res) {
 198                                 res->start = 0;
 199                                 res->end   = 0;
 200                                 res->flags = 0;
 201                         }
 202                         if (res && par) {
 203                                 res->start = par->start;
 204                                 res->end   = par->end;
 205                                 res->flags = par->flags;
 206                         }
 207                 }
 208         }
 209 }
 210
 211 int __init fsl_add_bridge(struct device_node *dev, int is_primary)
 212 {
 213         int len;
 214         struct pci_controller *hose;
 215         struct resource rsrc;
 216         const int *bus_range;
 217
 218         pr_debug("Adding PCI host bridge %s\n", dev->full_name);
 219
 220         /* Fetch host bridge registers address */
 221         if (of_address_to_resource(dev, 0, &rsrc)) {
 222                 printk(KERN_WARNING "Can't get pci register base!");
 223                 return -ENOMEM;
 224         }
 225
 226         /* Get bus range if any */
 227         bus_range = of_get_property(dev, "bus-range", &len);
 228         if (bus_range == NULL || len < 2 * sizeof(int))
 229                 printk(KERN_WARNING "Can't get bus-range for %s, assume"
 230                         " bus 0\n", dev->full_name);
 231
 232         ppc_pci_add_flags(PPC_PCI_REASSIGN_ALL_BUS);
 233         hose = pcibios_alloc_controller(dev);
 234         if (!hose)
 235                 return -ENOMEM;
 236
 237         hose->first_busno = bus_range ? bus_range[0] : 0x0;
 238         hose->last_busno = bus_range ? bus_range[1] : 0xff;
 239
 240         setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
 241                 PPC_INDIRECT_TYPE_BIG_ENDIAN);
 242         setup_pci_cmd(hose);
 243
 244         /* check PCI express link status */
 245         if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
 246                 hose->indirect_type |= PPC_INDIRECT_TYPE_EXT_REG |
 247                         PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS;
 248                 if (fsl_pcie_check_link(hose))
 249                         hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
 250         }
 251
 252         printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
 253                 "Firmware bus number: %d->%d\n",
 254                 (unsigned long long)rsrc.start, hose->first_busno,
 255                 hose->last_busno);
 256
 257         pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
 258                 hose, hose->cfg_addr, hose->cfg_data);
 259
 260         /* Interpret the "ranges" property */
 261         /* This also maps the I/O region and sets isa_io/mem_base */
 262         pci_process_bridge_OF_ranges(hose, dev, is_primary);
 263
 264         /* Setup PEX window registers */
 265         setup_pci_atmu(hose, &rsrc);
 266
 267         /* Setup PEXCSRBAR */
 268         setup_pci_pcsrbar(hose);
 269         return 0;
 270 }
 271
 272 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8548E, quirk_fsl_pcie_header);
 273 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8548, quirk_fsl_pcie_header);
 274 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8543E, quirk_fsl_pcie_header);
 275 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8543, quirk_fsl_pcie_header);
 276 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8547E, quirk_fsl_pcie_header);
 277 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8545E, quirk_fsl_pcie_header);
 278 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8545, quirk_fsl_pcie_header);
 279 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8568E, quirk_fsl_pcie_header);
 280 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8568, quirk_fsl_pcie_header);
 281 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8567E, quirk_fsl_pcie_header);
 282 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8567, quirk_fsl_pcie_header);
 283 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8533E, quirk_fsl_pcie_header);
 284 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8533, quirk_fsl_pcie_header);
 285 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8544E, quirk_fsl_pcie_header);
 286 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8544, quirk_fsl_pcie_header);
 287 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8572E, quirk_fsl_pcie_header);
 288 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8572, quirk_fsl_pcie_header);
 289 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8536E, quirk_fsl_pcie_header);
 290 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8536, quirk_fsl_pcie_header);
 291 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8641, quirk_fsl_pcie_header);
 292 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8641D, quirk_fsl_pcie_header);
 293 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8610, quirk_fsl_pcie_header);
 294 #endif /* CONFIG_PPC_85xx || CONFIG_PPC_86xx */
 295
 296 #if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_MPC512x)
 297 int __init mpc83xx_add_bridge(struct device_node *dev)
 298 {
 299         int len;
 300         struct pci_controller *hose;
 301         struct resource rsrc_reg;
 302         struct resource rsrc_cfg;
 303         const int *bus_range;
 304         int primary;
 305
 306         pr_debug("Adding PCI host bridge %s\n", dev->full_name);
 307
 308         /* Fetch host bridge registers address */
 309         if (of_address_to_resource(dev, 0, &rsrc_reg)) {
 310                 printk(KERN_WARNING "Can't get pci register base!\n");
 311                 return -ENOMEM;
 312         }
 313
 314         memset(&rsrc_cfg, 0, sizeof(rsrc_cfg));
 315
 316         if (of_address_to_resource(dev, 1, &rsrc_cfg)) {
 317                 printk(KERN_WARNING
 318                         "No pci config register base in dev tree, "
 319                         "using default\n");
 320                 /*
 321                  * MPC83xx supports up to two host controllers
 322                  *      one at 0x8500 has config space registers at 0x8300
 323                  *      one at 0x8600 has config space registers at 0x8380
 324                  */
 325                 if ((rsrc_reg.start & 0xfffff) == 0x8500)
 326                         rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8300;
 327                 else if ((rsrc_reg.start & 0xfffff) == 0x8600)
 328                         rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8380;
 329         }
 330         /*
 331          * Controller at offset 0x8500 is primary
 332          */
 333         if ((rsrc_reg.start & 0xfffff) == 0x8500)
 334                 primary = 1;
 335         else
 336                 primary = 0;
 337
 338         /* Get bus range if any */
 339         bus_range = of_get_property(dev, "bus-range", &len);
 340         if (bus_range == NULL || len < 2 * sizeof(int)) {
 341                 printk(KERN_WARNING "Can't get bus-range for %s, assume"
 342                        " bus 0\n", dev->full_name);
 343         }
 344
 345         ppc_pci_add_flags(PPC_PCI_REASSIGN_ALL_BUS);
 346         hose = pcibios_alloc_controller(dev);
 347         if (!hose)
 348                 return -ENOMEM;
 349
 350         hose->first_busno = bus_range ? bus_range[0] : 0;
 351         hose->last_busno = bus_range ? bus_range[1] : 0xff;
 352
 353         setup_indirect_pci(hose, rsrc_cfg.start, rsrc_cfg.start + 4, 0);
 354
 355         printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
 356                "Firmware bus number: %d->%d\n",
 357                (unsigned long long)rsrc_reg.start, hose->first_busno,
 358                hose->last_busno);
 359
 360         pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
 361             hose, hose->cfg_addr, hose->cfg_data);
 362
 363         /* Interpret the "ranges" property */
 364         /* This also maps the I/O region and sets isa_io/mem_base */
 365         pci_process_bridge_OF_ranges(hose, dev, primary);
 366
 367         return 0;
 368 }
 369 #endif /* CONFIG_PPC_83xx */