arch/powerpc/sysdev/fsl_pci.c

   1 /*
   2  * MPC83xx/85xx/86xx PCI/PCIE support routing.
   3  *
   4  * Copyright 2007,2008 Freescale Semiconductor, Inc
   5  *
   6  * Initial author: Xianghua Xiao <x.xiao@freescale.com>
   7  * Recode: ZHANG WEI <wei.zhang@freescale.com>
   8  * Rewrite the routing for Frescale PCI and PCI Express
   9  *      Roy Zang <tie-fei.zang@freescale.com>
  10  *
  11  * This program is free software; you can redistribute  it and/or modify it
  12  * under  the terms of  the GNU General  Public License as published by the
  13  * Free Software Foundation;  either version 2 of the  License, or (at your
  14  * option) any later version.
  15  */
  16 #include <linux/kernel.h>
  17 #include <linux/pci.h>
  18 #include <linux/delay.h>
  19 #include <linux/string.h>
  20 #include <linux/init.h>
  21 #include <linux/bootmem.h>
  22
  23 #include <asm/io.h>
  24 #include <asm/prom.h>
  25 #include <asm/pci-bridge.h>
  26 #include <asm/machdep.h>
  27 #include <sysdev/fsl_soc.h>
  28 #include <sysdev/fsl_pci.h>
  29
  30 #if defined(CONFIG_PPC_85xx) || defined(CONFIG_PPC_86xx)
  31 /* atmu setup for fsl pci/pcie controller */
  32 void __init setup_pci_atmu(struct pci_controller *hose, struct resource *rsrc)
  33 {
  34         struct ccsr_pci __iomem *pci;
  35         int i;
  36
  37         pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n",
  38                     (u64)rsrc->start, (u64)rsrc->end - (u64)rsrc->start + 1);
  39         pci = ioremap(rsrc->start, rsrc->end - rsrc->start + 1);
  40
  41         /* Disable all windows (except powar0 since its ignored) */
  42         for(i = 1; i < 5; i++)
  43                 out_be32(&pci->pow[i].powar, 0);
  44         for(i = 0; i < 3; i++)
  45                 out_be32(&pci->piw[i].piwar, 0);
  46
  47         /* Setup outbound MEM window */
  48         for(i = 0; i < 3; i++)
  49                 if (hose->mem_resources[i].flags & IORESOURCE_MEM){
  50                         resource_size_t pci_addr_start =
  51                                  hose->mem_resources[i].start -
  52                                  hose->pci_mem_offset;
  53                         pr_debug("PCI MEM resource start 0x%016llx, size 0x%016llx.\n",
  54                                 (u64)hose->mem_resources[i].start,
  55                                 (u64)hose->mem_resources[i].end
  56                                   - (u64)hose->mem_resources[i].start + 1);
  57                         out_be32(&pci->pow[i+1].potar, (pci_addr_start >> 12));
  58                         out_be32(&pci->pow[i+1].potear, 0);
  59                         out_be32(&pci->pow[i+1].powbar,
  60                                 (hose->mem_resources[i].start >> 12));
  61                         /* Enable, Mem R/W */
  62                         out_be32(&pci->pow[i+1].powar, 0x80044000
  63                                 | (__ilog2(hose->mem_resources[i].end
  64                                 - hose->mem_resources[i].start + 1) - 1));
  65                 }
  66
  67         /* Setup outbound IO window */
  68         if (hose->io_resource.flags & IORESOURCE_IO){
  69                 pr_debug("PCI IO resource start 0x%016llx, size 0x%016llx, "
  70                          "phy base 0x%016llx.\n",
  71                         (u64)hose->io_resource.start,
  72                         (u64)hose->io_resource.end - (u64)hose->io_resource.start + 1,
  73                         (u64)hose->io_base_phys);
  74                 out_be32(&pci->pow[i+1].potar, (hose->io_resource.start >> 12));
  75                 out_be32(&pci->pow[i+1].potear, 0);
  76                 out_be32(&pci->pow[i+1].powbar, (hose->io_base_phys >> 12));
  77                 /* Enable, IO R/W */
  78                 out_be32(&pci->pow[i+1].powar, 0x80088000
  79                         | (__ilog2(hose->io_resource.end
  80                         - hose->io_resource.start + 1) - 1));
  81         }
  82
  83         /* Setup 2G inbound Memory Window @ 1 */
  84         out_be32(&pci->piw[2].pitar, 0x00000000);
  85         out_be32(&pci->piw[2].piwbar,0x00000000);
  86         out_be32(&pci->piw[2].piwar, PIWAR_2G);
  87 }
  88
  89 void __init setup_pci_cmd(struct pci_controller *hose)
  90 {
  91         u16 cmd;
  92         int cap_x;
  93
  94         early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd);
  95         cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
  96                 | PCI_COMMAND_IO;
  97         early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd);
  98
  99         cap_x = early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX);
 100         if (cap_x) {
 101                 int pci_x_cmd = cap_x + PCI_X_CMD;
 102                 cmd = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
 103                         | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
 104                 early_write_config_word(hose, 0, 0, pci_x_cmd, cmd);
 105         } else {
 106                 early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
 107         }
 108 }
 109
 110 static void __init setup_pci_pcsrbar(struct pci_controller *hose)
 111 {
 112 #ifdef CONFIG_PCI_MSI
 113         phys_addr_t immr_base;
 114
 115         immr_base = get_immrbase();
 116         early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, immr_base);
 117 #endif
 118 }
 119
 120 static int fsl_pcie_bus_fixup;
 121
 122 static void __init quirk_fsl_pcie_header(struct pci_dev *dev)
 123 {
 124         /* if we aren't a PCIe don't bother */
 125         if (!pci_find_capability(dev, PCI_CAP_ID_EXP))
 126                 return ;
 127
 128         dev->class = PCI_CLASS_BRIDGE_PCI << 8;
 129         fsl_pcie_bus_fixup = 1;
 130         return ;
 131 }
 132
 133 int __init fsl_pcie_check_link(struct pci_controller *hose)
 134 {
 135         u32 val;
 136         early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val);
 137         if (val < PCIE_LTSSM_L0)
 138                 return 1;
 139         return 0;
 140 }
 141
 142 void fsl_pcibios_fixup_bus(struct pci_bus *bus)
 143 {
 144         struct pci_controller *hose = (struct pci_controller *) bus->sysdata;
 145         int i;
 146
 147         if ((bus->parent == hose->bus) &&
 148             ((fsl_pcie_bus_fixup &&
 149               early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) ||
 150              (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK)))
 151         {
 152                 for (i = 0; i < 4; ++i) {
 153                         struct resource *res = bus->resource[i];
 154                         struct resource *par = bus->parent->resource[i];
 155                         if (res) {
 156                                 res->start = 0;
 157                                 res->end   = 0;
 158                                 res->flags = 0;
 159                         }
 160                         if (res && par) {
 161                                 res->start = par->start;
 162                                 res->end   = par->end;
 163                                 res->flags = par->flags;
 164                         }
 165                 }
 166         }
 167 }
 168
 169 int __init fsl_add_bridge(struct device_node *dev, int is_primary)
 170 {
 171         int len;
 172         struct pci_controller *hose;
 173         struct resource rsrc;
 174         const int *bus_range;
 175
 176         pr_debug("Adding PCI host bridge %s\n", dev->full_name);
 177
 178         /* Fetch host bridge registers address */
 179         if (of_address_to_resource(dev, 0, &rsrc)) {
 180                 printk(KERN_WARNING "Can't get pci register base!");
 181                 return -ENOMEM;
 182         }
 183
 184         /* Get bus range if any */
 185         bus_range = of_get_property(dev, "bus-range", &len);
 186         if (bus_range == NULL || len < 2 * sizeof(int))
 187                 printk(KERN_WARNING "Can't get bus-range for %s, assume"
 188                         " bus 0\n", dev->full_name);
 189
 190         ppc_pci_add_flags(PPC_PCI_REASSIGN_ALL_BUS);
 191         hose = pcibios_alloc_controller(dev);
 192         if (!hose)
 193                 return -ENOMEM;
 194
 195         hose->first_busno = bus_range ? bus_range[0] : 0x0;
 196         hose->last_busno = bus_range ? bus_range[1] : 0xff;
 197
 198         setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
 199                 PPC_INDIRECT_TYPE_BIG_ENDIAN);
 200         setup_pci_cmd(hose);
 201
 202         /* check PCI express link status */
 203         if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
 204                 hose->indirect_type |= PPC_INDIRECT_TYPE_EXT_REG |
 205                         PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS;
 206                 if (fsl_pcie_check_link(hose))
 207                         hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
 208         }
 209
 210         printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
 211                 "Firmware bus number: %d->%d\n",
 212                 (unsigned long long)rsrc.start, hose->first_busno,
 213                 hose->last_busno);
 214
 215         pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
 216                 hose, hose->cfg_addr, hose->cfg_data);
 217
 218         /* Interpret the "ranges" property */
 219         /* This also maps the I/O region and sets isa_io/mem_base */
 220         pci_process_bridge_OF_ranges(hose, dev, is_primary);
 221
 222         /* Setup PEX window registers */
 223         setup_pci_atmu(hose, &rsrc);
 224
 225         /* Setup PEXCSRBAR */
 226         setup_pci_pcsrbar(hose);
 227         return 0;
 228 }
 229
 230 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8548E, quirk_fsl_pcie_header);
 231 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8548, quirk_fsl_pcie_header);
 232 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8543E, quirk_fsl_pcie_header);
 233 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8543, quirk_fsl_pcie_header);
 234 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8547E, quirk_fsl_pcie_header);
 235 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8545E, quirk_fsl_pcie_header);
 236 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8545, quirk_fsl_pcie_header);
 237 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8568E, quirk_fsl_pcie_header);
 238 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8568, quirk_fsl_pcie_header);
 239 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8567E, quirk_fsl_pcie_header);
 240 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8567, quirk_fsl_pcie_header);
 241 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8533E, quirk_fsl_pcie_header);
 242 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8533, quirk_fsl_pcie_header);
 243 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8544E, quirk_fsl_pcie_header);
 244 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8544, quirk_fsl_pcie_header);
 245 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8572E, quirk_fsl_pcie_header);
 246 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8572, quirk_fsl_pcie_header);
 247 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8536E, quirk_fsl_pcie_header);
 248 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8536, quirk_fsl_pcie_header);
 249 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8641, quirk_fsl_pcie_header);
 250 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8641D, quirk_fsl_pcie_header);
 251 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8610, quirk_fsl_pcie_header);
 252 #endif /* CONFIG_PPC_85xx || CONFIG_PPC_86xx */
 253
 254 #if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_MPC512x)
 255 int __init mpc83xx_add_bridge(struct device_node *dev)
 256 {
 257         int len;
 258         struct pci_controller *hose;
 259         struct resource rsrc_reg;
 260         struct resource rsrc_cfg;
 261         const int *bus_range;
 262         int primary;
 263
 264         pr_debug("Adding PCI host bridge %s\n", dev->full_name);
 265
 266         /* Fetch host bridge registers address */
 267         if (of_address_to_resource(dev, 0, &rsrc_reg)) {
 268                 printk(KERN_WARNING "Can't get pci register base!\n");
 269                 return -ENOMEM;
 270         }
 271
 272         memset(&rsrc_cfg, 0, sizeof(rsrc_cfg));
 273
 274         if (of_address_to_resource(dev, 1, &rsrc_cfg)) {
 275                 printk(KERN_WARNING
 276                         "No pci config register base in dev tree, "
 277                         "using default\n");
 278                 /*
 279                  * MPC83xx supports up to two host controllers
 280                  *      one at 0x8500 has config space registers at 0x8300
 281                  *      one at 0x8600 has config space registers at 0x8380
 282                  */
 283                 if ((rsrc_reg.start & 0xfffff) == 0x8500)
 284                         rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8300;
 285                 else if ((rsrc_reg.start & 0xfffff) == 0x8600)
 286                         rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8380;
 287         }
 288         /*
 289          * Controller at offset 0x8500 is primary
 290          */
 291         if ((rsrc_reg.start & 0xfffff) == 0x8500)
 292                 primary = 1;
 293         else
 294                 primary = 0;
 295
 296         /* Get bus range if any */
 297         bus_range = of_get_property(dev, "bus-range", &len);
 298         if (bus_range == NULL || len < 2 * sizeof(int)) {
 299                 printk(KERN_WARNING "Can't get bus-range for %s, assume"
 300                        " bus 0\n", dev->full_name);
 301         }
 302
 303         ppc_pci_add_flags(PPC_PCI_REASSIGN_ALL_BUS);
 304         hose = pcibios_alloc_controller(dev);
 305         if (!hose)
 306                 return -ENOMEM;
 307
 308         hose->first_busno = bus_range ? bus_range[0] : 0;
 309         hose->last_busno = bus_range ? bus_range[1] : 0xff;
 310
 311         setup_indirect_pci(hose, rsrc_cfg.start, rsrc_cfg.start + 4, 0);
 312
 313         printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
 314                "Firmware bus number: %d->%d\n",
 315                (unsigned long long)rsrc_reg.start, hose->first_busno,
 316                hose->last_busno);
 317
 318         pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
 319             hose, hose->cfg_addr, hose->cfg_data);
 320
 321         /* Interpret the "ranges" property */
 322         /* This also maps the I/O region and sets isa_io/mem_base */
 323         pci_process_bridge_OF_ranges(hose, dev, primary);
 324
 325         return 0;
 326 }
 327 #endif /* CONFIG_PPC_83xx */