2 * MPC83xx/85xx/86xx PCI/PCIE support routing.
4 * Copyright 2007,2008 Freescale Semiconductor, Inc
6 * Initial author: Xianghua Xiao <x.xiao@freescale.com>
7 * Recode: ZHANG WEI <wei.zhang@freescale.com>
8 * Rewrite the routing for Frescale PCI and PCI Express
9 * Roy Zang <tie-fei.zang@freescale.com>
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
16 #include <linux/kernel.h>
17 #include <linux/pci.h>
18 #include <linux/delay.h>
19 #include <linux/string.h>
20 #include <linux/init.h>
21 #include <linux/bootmem.h>
25 #include <asm/pci-bridge.h>
26 #include <asm/machdep.h>
27 #include <sysdev/fsl_soc.h>
28 #include <sysdev/fsl_pci.h>
30 #if defined(CONFIG_PPC_85xx) || defined(CONFIG_PPC_86xx)
31 /* atmu setup for fsl pci/pcie controller */
32 static void __init
setup_pci_atmu(struct pci_controller
*hose
,
33 struct resource
*rsrc
)
35 struct ccsr_pci __iomem
*pci
;
38 pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n",
39 (u64
)rsrc
->start
, (u64
)rsrc
->end
- (u64
)rsrc
->start
+ 1);
40 pci
= ioremap(rsrc
->start
, rsrc
->end
- rsrc
->start
+ 1);
42 /* Disable all windows (except powar0 since its ignored) */
43 for(i
= 1; i
< 5; i
++)
44 out_be32(&pci
->pow
[i
].powar
, 0);
45 for(i
= 0; i
< 3; i
++)
46 out_be32(&pci
->piw
[i
].piwar
, 0);
48 /* Setup outbound MEM window */
49 for(i
= 0; i
< 3; i
++)
50 if (hose
->mem_resources
[i
].flags
& IORESOURCE_MEM
){
51 resource_size_t pci_addr_start
=
52 hose
->mem_resources
[i
].start
-
54 pr_debug("PCI MEM resource start 0x%016llx, size 0x%016llx.\n",
55 (u64
)hose
->mem_resources
[i
].start
,
56 (u64
)hose
->mem_resources
[i
].end
57 - (u64
)hose
->mem_resources
[i
].start
+ 1);
58 out_be32(&pci
->pow
[i
+1].potar
, (pci_addr_start
>> 12));
59 out_be32(&pci
->pow
[i
+1].potear
, 0);
60 out_be32(&pci
->pow
[i
+1].powbar
,
61 (hose
->mem_resources
[i
].start
>> 12));
63 out_be32(&pci
->pow
[i
+1].powar
, 0x80044000
64 | (__ilog2(hose
->mem_resources
[i
].end
65 - hose
->mem_resources
[i
].start
+ 1) - 1));
68 /* Setup outbound IO window */
69 if (hose
->io_resource
.flags
& IORESOURCE_IO
){
70 pr_debug("PCI IO resource start 0x%016llx, size 0x%016llx, "
71 "phy base 0x%016llx.\n",
72 (u64
)hose
->io_resource
.start
,
73 (u64
)hose
->io_resource
.end
- (u64
)hose
->io_resource
.start
+ 1,
74 (u64
)hose
->io_base_phys
);
75 out_be32(&pci
->pow
[i
+1].potar
, (hose
->io_resource
.start
>> 12));
76 out_be32(&pci
->pow
[i
+1].potear
, 0);
77 out_be32(&pci
->pow
[i
+1].powbar
, (hose
->io_base_phys
>> 12));
79 out_be32(&pci
->pow
[i
+1].powar
, 0x80088000
80 | (__ilog2(hose
->io_resource
.end
81 - hose
->io_resource
.start
+ 1) - 1));
84 /* Setup 2G inbound Memory Window @ 1 */
85 out_be32(&pci
->piw
[2].pitar
, 0x00000000);
86 out_be32(&pci
->piw
[2].piwbar
,0x00000000);
87 out_be32(&pci
->piw
[2].piwar
, PIWAR_2G
);
90 static void __init
setup_pci_cmd(struct pci_controller
*hose
)
95 early_read_config_word(hose
, 0, 0, PCI_COMMAND
, &cmd
);
96 cmd
|= PCI_COMMAND_SERR
| PCI_COMMAND_MASTER
| PCI_COMMAND_MEMORY
98 early_write_config_word(hose
, 0, 0, PCI_COMMAND
, cmd
);
100 cap_x
= early_find_capability(hose
, 0, 0, PCI_CAP_ID_PCIX
);
102 int pci_x_cmd
= cap_x
+ PCI_X_CMD
;
103 cmd
= PCI_X_CMD_MAX_SPLIT
| PCI_X_CMD_MAX_READ
104 | PCI_X_CMD_ERO
| PCI_X_CMD_DPERR_E
;
105 early_write_config_word(hose
, 0, 0, pci_x_cmd
, cmd
);
107 early_write_config_byte(hose
, 0, 0, PCI_LATENCY_TIMER
, 0x80);
111 static void __init
setup_pci_pcsrbar(struct pci_controller
*hose
)
113 #ifdef CONFIG_PCI_MSI
114 phys_addr_t immr_base
;
116 immr_base
= get_immrbase();
117 early_write_config_dword(hose
, 0, 0, PCI_BASE_ADDRESS_0
, immr_base
);
121 static int fsl_pcie_bus_fixup
;
123 static void __init
quirk_fsl_pcie_header(struct pci_dev
*dev
)
125 /* if we aren't a PCIe don't bother */
126 if (!pci_find_capability(dev
, PCI_CAP_ID_EXP
))
129 dev
->class = PCI_CLASS_BRIDGE_PCI
<< 8;
130 fsl_pcie_bus_fixup
= 1;
134 static int __init
fsl_pcie_check_link(struct pci_controller
*hose
)
137 early_read_config_dword(hose
, 0, 0, PCIE_LTSSM
, &val
);
138 if (val
< PCIE_LTSSM_L0
)
143 void fsl_pcibios_fixup_bus(struct pci_bus
*bus
)
145 struct pci_controller
*hose
= (struct pci_controller
*) bus
->sysdata
;
148 if ((bus
->parent
== hose
->bus
) &&
149 ((fsl_pcie_bus_fixup
&&
150 early_find_capability(hose
, 0, 0, PCI_CAP_ID_EXP
)) ||
151 (hose
->indirect_type
& PPC_INDIRECT_TYPE_NO_PCIE_LINK
)))
153 for (i
= 0; i
< 4; ++i
) {
154 struct resource
*res
= bus
->resource
[i
];
155 struct resource
*par
= bus
->parent
->resource
[i
];
162 res
->start
= par
->start
;
164 res
->flags
= par
->flags
;
170 int __init
fsl_add_bridge(struct device_node
*dev
, int is_primary
)
173 struct pci_controller
*hose
;
174 struct resource rsrc
;
175 const int *bus_range
;
177 pr_debug("Adding PCI host bridge %s\n", dev
->full_name
);
179 /* Fetch host bridge registers address */
180 if (of_address_to_resource(dev
, 0, &rsrc
)) {
181 printk(KERN_WARNING
"Can't get pci register base!");
185 /* Get bus range if any */
186 bus_range
= of_get_property(dev
, "bus-range", &len
);
187 if (bus_range
== NULL
|| len
< 2 * sizeof(int))
188 printk(KERN_WARNING
"Can't get bus-range for %s, assume"
189 " bus 0\n", dev
->full_name
);
191 ppc_pci_add_flags(PPC_PCI_REASSIGN_ALL_BUS
);
192 hose
= pcibios_alloc_controller(dev
);
196 hose
->first_busno
= bus_range
? bus_range
[0] : 0x0;
197 hose
->last_busno
= bus_range
? bus_range
[1] : 0xff;
199 setup_indirect_pci(hose
, rsrc
.start
, rsrc
.start
+ 0x4,
200 PPC_INDIRECT_TYPE_BIG_ENDIAN
);
203 /* check PCI express link status */
204 if (early_find_capability(hose
, 0, 0, PCI_CAP_ID_EXP
)) {
205 hose
->indirect_type
|= PPC_INDIRECT_TYPE_EXT_REG
|
206 PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS
;
207 if (fsl_pcie_check_link(hose
))
208 hose
->indirect_type
|= PPC_INDIRECT_TYPE_NO_PCIE_LINK
;
211 printk(KERN_INFO
"Found FSL PCI host bridge at 0x%016llx. "
212 "Firmware bus number: %d->%d\n",
213 (unsigned long long)rsrc
.start
, hose
->first_busno
,
216 pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
217 hose
, hose
->cfg_addr
, hose
->cfg_data
);
219 /* Interpret the "ranges" property */
220 /* This also maps the I/O region and sets isa_io/mem_base */
221 pci_process_bridge_OF_ranges(hose
, dev
, is_primary
);
223 /* Setup PEX window registers */
224 setup_pci_atmu(hose
, &rsrc
);
226 /* Setup PEXCSRBAR */
227 setup_pci_pcsrbar(hose
);
231 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8548E
, quirk_fsl_pcie_header
);
232 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8548
, quirk_fsl_pcie_header
);
233 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8543E
, quirk_fsl_pcie_header
);
234 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8543
, quirk_fsl_pcie_header
);
235 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8547E
, quirk_fsl_pcie_header
);
236 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8545E
, quirk_fsl_pcie_header
);
237 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8545
, quirk_fsl_pcie_header
);
238 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8568E
, quirk_fsl_pcie_header
);
239 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8568
, quirk_fsl_pcie_header
);
240 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8567E
, quirk_fsl_pcie_header
);
241 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8567
, quirk_fsl_pcie_header
);
242 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8533E
, quirk_fsl_pcie_header
);
243 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8533
, quirk_fsl_pcie_header
);
244 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8544E
, quirk_fsl_pcie_header
);
245 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8544
, quirk_fsl_pcie_header
);
246 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8572E
, quirk_fsl_pcie_header
);
247 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8572
, quirk_fsl_pcie_header
);
248 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8536E
, quirk_fsl_pcie_header
);
249 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8536
, quirk_fsl_pcie_header
);
250 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8641
, quirk_fsl_pcie_header
);
251 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8641D
, quirk_fsl_pcie_header
);
252 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8610
, quirk_fsl_pcie_header
);
253 #endif /* CONFIG_PPC_85xx || CONFIG_PPC_86xx */
255 #if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_MPC512x)
256 int __init
mpc83xx_add_bridge(struct device_node
*dev
)
259 struct pci_controller
*hose
;
260 struct resource rsrc_reg
;
261 struct resource rsrc_cfg
;
262 const int *bus_range
;
265 pr_debug("Adding PCI host bridge %s\n", dev
->full_name
);
267 /* Fetch host bridge registers address */
268 if (of_address_to_resource(dev
, 0, &rsrc_reg
)) {
269 printk(KERN_WARNING
"Can't get pci register base!\n");
273 memset(&rsrc_cfg
, 0, sizeof(rsrc_cfg
));
275 if (of_address_to_resource(dev
, 1, &rsrc_cfg
)) {
277 "No pci config register base in dev tree, "
280 * MPC83xx supports up to two host controllers
281 * one at 0x8500 has config space registers at 0x8300
282 * one at 0x8600 has config space registers at 0x8380
284 if ((rsrc_reg
.start
& 0xfffff) == 0x8500)
285 rsrc_cfg
.start
= (rsrc_reg
.start
& 0xfff00000) + 0x8300;
286 else if ((rsrc_reg
.start
& 0xfffff) == 0x8600)
287 rsrc_cfg
.start
= (rsrc_reg
.start
& 0xfff00000) + 0x8380;
290 * Controller at offset 0x8500 is primary
292 if ((rsrc_reg
.start
& 0xfffff) == 0x8500)
297 /* Get bus range if any */
298 bus_range
= of_get_property(dev
, "bus-range", &len
);
299 if (bus_range
== NULL
|| len
< 2 * sizeof(int)) {
300 printk(KERN_WARNING
"Can't get bus-range for %s, assume"
301 " bus 0\n", dev
->full_name
);
304 ppc_pci_add_flags(PPC_PCI_REASSIGN_ALL_BUS
);
305 hose
= pcibios_alloc_controller(dev
);
309 hose
->first_busno
= bus_range
? bus_range
[0] : 0;
310 hose
->last_busno
= bus_range
? bus_range
[1] : 0xff;
312 setup_indirect_pci(hose
, rsrc_cfg
.start
, rsrc_cfg
.start
+ 4, 0);
314 printk(KERN_INFO
"Found FSL PCI host bridge at 0x%016llx. "
315 "Firmware bus number: %d->%d\n",
316 (unsigned long long)rsrc_reg
.start
, hose
->first_busno
,
319 pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
320 hose
, hose
->cfg_addr
, hose
->cfg_data
);
322 /* Interpret the "ranges" property */
323 /* This also maps the I/O region and sets isa_io/mem_base */
324 pci_process_bridge_OF_ranges(hose
, dev
, primary
);
328 #endif /* CONFIG_PPC_83xx */