arch/powerpc/sysdev/fsl_pci.h

   1 /*
   2  * MPC85xx/86xx PCI Express structure define
   3  *
   4  * Copyright 2007,2011 Freescale Semiconductor, Inc
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  *
  11  */
  12
  13 #ifdef __KERNEL__
  14 #ifndef __POWERPC_FSL_PCI_H
  15 #define __POWERPC_FSL_PCI_H
  16
  17 #define PCIE_LTSSM      0x0404          /* PCIE Link Training and Status */
  18 #define PCIE_LTSSM_L0   0x16            /* L0 state */
  19 #define PCIE_IP_REV_2_2         0x02080202 /* PCIE IP block version Rev2.2 */
  20 #define PIWAR_EN                0x80000000      /* Enable */
  21 #define PIWAR_PF                0x20000000      /* prefetch */
  22 #define PIWAR_TGI_LOCAL         0x00f00000      /* target - local memory */
  23 #define PIWAR_READ_SNOOP        0x00050000
  24 #define PIWAR_WRITE_SNOOP       0x00005000
  25 #define PIWAR_SZ_MASK          0x0000003f
  26
  27 /* PCI/PCI Express outbound window reg */
  28 struct pci_outbound_window_regs {
  29         __be32  potar;  /* 0x.0 - Outbound translation address register */
  30         __be32  potear; /* 0x.4 - Outbound translation extended address register */
  31         __be32  powbar; /* 0x.8 - Outbound window base address register */
  32         u8      res1[4];
  33         __be32  powar;  /* 0x.10 - Outbound window attributes register */
  34         u8      res2[12];
  35 };
  36
  37 /* PCI/PCI Express inbound window reg */
  38 struct pci_inbound_window_regs {
  39         __be32  pitar;  /* 0x.0 - Inbound translation address register */
  40         u8      res1[4];
  41         __be32  piwbar; /* 0x.8 - Inbound window base address register */
  42         __be32  piwbear;        /* 0x.c - Inbound window base extended address register */
  43         __be32  piwar;  /* 0x.10 - Inbound window attributes register */
  44         u8      res2[12];
  45 };
  46
  47 /* PCI/PCI Express IO block registers for 85xx/86xx */
  48 struct ccsr_pci {
  49         __be32  config_addr;            /* 0x.000 - PCI/PCIE Configuration Address Register */
  50         __be32  config_data;            /* 0x.004 - PCI/PCIE Configuration Data Register */
  51         __be32  int_ack;                /* 0x.008 - PCI Interrupt Acknowledge Register */
  52         __be32  pex_otb_cpl_tor;        /* 0x.00c - PCIE Outbound completion timeout register */
  53         __be32  pex_conf_tor;           /* 0x.010 - PCIE configuration timeout register */
  54         __be32  pex_config;             /* 0x.014 - PCIE CONFIG Register */
  55         __be32  pex_int_status;         /* 0x.018 - PCIE interrupt status */
  56         u8      res2[4];
  57         __be32  pex_pme_mes_dr;         /* 0x.020 - PCIE PME and message detect register */
  58         __be32  pex_pme_mes_disr;       /* 0x.024 - PCIE PME and message disable register */
  59         __be32  pex_pme_mes_ier;        /* 0x.028 - PCIE PME and message interrupt enable register */
  60         __be32  pex_pmcr;               /* 0x.02c - PCIE power management command register */
  61         u8      res3[3016];
  62         __be32  block_rev1;     /* 0x.bf8 - PCIE Block Revision register 1 */
  63         __be32  block_rev2;     /* 0x.bfc - PCIE Block Revision register 2 */
  64
  65 /* PCI/PCI Express outbound window 0-4
  66  * Window 0 is the default window and is the only window enabled upon reset.
  67  * The default outbound register set is used when a transaction misses
  68  * in all of the other outbound windows.
  69  */
  70         struct pci_outbound_window_regs pow[5];
  71         u8      res14[96];
  72         struct pci_inbound_window_regs  pmit;   /* 0xd00 - 0xd9c Inbound MSI */
  73         u8      res6[96];
  74 /* PCI/PCI Express inbound window 3-0
  75  * inbound window 1 supports only a 32-bit base address and does not
  76  * define an inbound window base extended address register.
  77  */
  78         struct pci_inbound_window_regs piw[4];
  79
  80         __be32  pex_err_dr;             /* 0x.e00 - PCI/PCIE error detect register */
  81         u8      res21[4];
  82         __be32  pex_err_en;             /* 0x.e08 - PCI/PCIE error interrupt enable register */
  83         u8      res22[4];
  84         __be32  pex_err_disr;           /* 0x.e10 - PCI/PCIE error disable register */
  85         u8      res23[12];
  86         __be32  pex_err_cap_stat;       /* 0x.e20 - PCI/PCIE error capture status register */
  87         u8      res24[4];
  88         __be32  pex_err_cap_r0;         /* 0x.e28 - PCIE error capture register 0 */
  89         __be32  pex_err_cap_r1;         /* 0x.e2c - PCIE error capture register 0 */
  90         __be32  pex_err_cap_r2;         /* 0x.e30 - PCIE error capture register 0 */
  91         __be32  pex_err_cap_r3;         /* 0x.e34 - PCIE error capture register 0 */
  92 };
  93
  94 extern int fsl_add_bridge(struct device_node *dev, int is_primary);
  95 extern void fsl_pcibios_fixup_bus(struct pci_bus *bus);
  96 extern int mpc83xx_add_bridge(struct device_node *dev);
  97 u64 fsl_pci_immrbar_base(struct pci_controller *hose);
  98
  99 extern struct device_node *fsl_pci_primary;
 100
 101 #ifdef CONFIG_PCI
 102 void fsl_pci_assign_primary(void);
 103 #else
 104 static inline void fsl_pci_assign_primary(void) {}
 105 #endif
 106
 107 #ifdef CONFIG_EDAC_MPC85XX
 108 int mpc85xx_pci_err_probe(struct platform_device *op);
 109 #else
 110 static inline int mpc85xx_pci_err_probe(struct platform_device *op)
 111 {
 112         return -ENOTSUPP;
 113 }
 114 #endif
 115
 116 #endif /* __POWERPC_FSL_PCI_H */
 117 #endif /* __KERNEL__ */