2 * arch/powerpc/kernel/mpic.c
4 * Driver for interrupt controllers following the OpenPIC standard, the
5 * common implementation beeing IBM's MPIC. This driver also can deal
6 * with various broken implementations of this HW.
8 * Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp.
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file COPYING in the main directory of this archive
20 #include <linux/config.h>
21 #include <linux/types.h>
22 #include <linux/kernel.h>
23 #include <linux/init.h>
24 #include <linux/irq.h>
25 #include <linux/smp.h>
26 #include <linux/interrupt.h>
27 #include <linux/bootmem.h>
28 #include <linux/spinlock.h>
29 #include <linux/pci.h>
31 #include <asm/ptrace.h>
32 #include <asm/signal.h>
34 #include <asm/pgtable.h>
36 #include <asm/machdep.h>
41 #define DBG(fmt...) printk(fmt)
46 static struct mpic
*mpics
;
47 static struct mpic
*mpic_primary
;
48 static DEFINE_SPINLOCK(mpic_lock
);
50 #ifdef CONFIG_PPC32 /* XXX for now */
51 #ifdef CONFIG_IRQ_ALL_CPUS
52 #define distribute_irqs (1)
54 #define distribute_irqs (0)
59 * Register accessor functions
63 static inline u32
_mpic_read(unsigned int be
, volatile u32 __iomem
*base
,
67 return in_be32(base
+ (reg
>> 2));
69 return in_le32(base
+ (reg
>> 2));
72 static inline void _mpic_write(unsigned int be
, volatile u32 __iomem
*base
,
73 unsigned int reg
, u32 value
)
76 out_be32(base
+ (reg
>> 2), value
);
78 out_le32(base
+ (reg
>> 2), value
);
81 static inline u32
_mpic_ipi_read(struct mpic
*mpic
, unsigned int ipi
)
83 unsigned int be
= (mpic
->flags
& MPIC_BIG_ENDIAN
) != 0;
84 unsigned int offset
= MPIC_GREG_IPI_VECTOR_PRI_0
+ (ipi
* 0x10);
86 if (mpic
->flags
& MPIC_BROKEN_IPI
)
88 return _mpic_read(be
, mpic
->gregs
, offset
);
91 static inline void _mpic_ipi_write(struct mpic
*mpic
, unsigned int ipi
, u32 value
)
93 unsigned int offset
= MPIC_GREG_IPI_VECTOR_PRI_0
+ (ipi
* 0x10);
95 _mpic_write(mpic
->flags
& MPIC_BIG_ENDIAN
, mpic
->gregs
, offset
, value
);
98 static inline u32
_mpic_cpu_read(struct mpic
*mpic
, unsigned int reg
)
100 unsigned int cpu
= 0;
102 if (mpic
->flags
& MPIC_PRIMARY
)
103 cpu
= hard_smp_processor_id();
105 return _mpic_read(mpic
->flags
& MPIC_BIG_ENDIAN
, mpic
->cpuregs
[cpu
], reg
);
108 static inline void _mpic_cpu_write(struct mpic
*mpic
, unsigned int reg
, u32 value
)
110 unsigned int cpu
= 0;
112 if (mpic
->flags
& MPIC_PRIMARY
)
113 cpu
= hard_smp_processor_id();
115 _mpic_write(mpic
->flags
& MPIC_BIG_ENDIAN
, mpic
->cpuregs
[cpu
], reg
, value
);
118 static inline u32
_mpic_irq_read(struct mpic
*mpic
, unsigned int src_no
, unsigned int reg
)
120 unsigned int isu
= src_no
>> mpic
->isu_shift
;
121 unsigned int idx
= src_no
& mpic
->isu_mask
;
123 return _mpic_read(mpic
->flags
& MPIC_BIG_ENDIAN
, mpic
->isus
[isu
],
124 reg
+ (idx
* MPIC_IRQ_STRIDE
));
127 static inline void _mpic_irq_write(struct mpic
*mpic
, unsigned int src_no
,
128 unsigned int reg
, u32 value
)
130 unsigned int isu
= src_no
>> mpic
->isu_shift
;
131 unsigned int idx
= src_no
& mpic
->isu_mask
;
133 _mpic_write(mpic
->flags
& MPIC_BIG_ENDIAN
, mpic
->isus
[isu
],
134 reg
+ (idx
* MPIC_IRQ_STRIDE
), value
);
137 #define mpic_read(b,r) _mpic_read(mpic->flags & MPIC_BIG_ENDIAN,(b),(r))
138 #define mpic_write(b,r,v) _mpic_write(mpic->flags & MPIC_BIG_ENDIAN,(b),(r),(v))
139 #define mpic_ipi_read(i) _mpic_ipi_read(mpic,(i))
140 #define mpic_ipi_write(i,v) _mpic_ipi_write(mpic,(i),(v))
141 #define mpic_cpu_read(i) _mpic_cpu_read(mpic,(i))
142 #define mpic_cpu_write(i,v) _mpic_cpu_write(mpic,(i),(v))
143 #define mpic_irq_read(s,r) _mpic_irq_read(mpic,(s),(r))
144 #define mpic_irq_write(s,r,v) _mpic_irq_write(mpic,(s),(r),(v))
148 * Low level utility functions
153 /* Check if we have one of those nice broken MPICs with a flipped endian on
154 * reads from IPI registers
156 static void __init
mpic_test_broken_ipi(struct mpic
*mpic
)
160 mpic_write(mpic
->gregs
, MPIC_GREG_IPI_VECTOR_PRI_0
, MPIC_VECPRI_MASK
);
161 r
= mpic_read(mpic
->gregs
, MPIC_GREG_IPI_VECTOR_PRI_0
);
163 if (r
== le32_to_cpu(MPIC_VECPRI_MASK
)) {
164 printk(KERN_INFO
"mpic: Detected reversed IPI registers\n");
165 mpic
->flags
|= MPIC_BROKEN_IPI
;
169 #ifdef CONFIG_MPIC_BROKEN_U3
171 /* Test if an interrupt is sourced from HyperTransport (used on broken U3s)
172 * to force the edge setting on the MPIC and do the ack workaround.
174 static inline int mpic_is_ht_interrupt(struct mpic
*mpic
, unsigned int source
)
176 if (source
>= 128 || !mpic
->fixups
)
178 return mpic
->fixups
[source
].base
!= NULL
;
182 static inline void mpic_ht_end_irq(struct mpic
*mpic
, unsigned int source
)
184 struct mpic_irq_fixup
*fixup
= &mpic
->fixups
[source
];
186 if (fixup
->applebase
) {
187 unsigned int soff
= (fixup
->index
>> 3) & ~3;
188 unsigned int mask
= 1U << (fixup
->index
& 0x1f);
189 writel(mask
, fixup
->applebase
+ soff
);
191 spin_lock(&mpic
->fixup_lock
);
192 writeb(0x11 + 2 * fixup
->index
, fixup
->base
+ 2);
193 writel(fixup
->data
, fixup
->base
+ 4);
194 spin_unlock(&mpic
->fixup_lock
);
198 static void mpic_startup_ht_interrupt(struct mpic
*mpic
, unsigned int source
,
199 unsigned int irqflags
)
201 struct mpic_irq_fixup
*fixup
= &mpic
->fixups
[source
];
205 if (fixup
->base
== NULL
)
208 DBG("startup_ht_interrupt(%u, %u) index: %d\n",
209 source
, irqflags
, fixup
->index
);
210 spin_lock_irqsave(&mpic
->fixup_lock
, flags
);
211 /* Enable and configure */
212 writeb(0x10 + 2 * fixup
->index
, fixup
->base
+ 2);
213 tmp
= readl(fixup
->base
+ 4);
215 if (irqflags
& IRQ_LEVEL
)
217 writel(tmp
, fixup
->base
+ 4);
218 spin_unlock_irqrestore(&mpic
->fixup_lock
, flags
);
221 static void mpic_shutdown_ht_interrupt(struct mpic
*mpic
, unsigned int source
,
222 unsigned int irqflags
)
224 struct mpic_irq_fixup
*fixup
= &mpic
->fixups
[source
];
228 if (fixup
->base
== NULL
)
231 DBG("shutdown_ht_interrupt(%u, %u)\n", source
, irqflags
);
234 spin_lock_irqsave(&mpic
->fixup_lock
, flags
);
235 writeb(0x10 + 2 * fixup
->index
, fixup
->base
+ 2);
236 tmp
= readl(fixup
->base
+ 4);
238 writel(tmp
, fixup
->base
+ 4);
239 spin_unlock_irqrestore(&mpic
->fixup_lock
, flags
);
242 static void __init
mpic_scan_ht_pic(struct mpic
*mpic
, u8 __iomem
*devbase
,
243 unsigned int devfn
, u32 vdid
)
250 for (pos
= readb(devbase
+ PCI_CAPABILITY_LIST
); pos
!= 0;
251 pos
= readb(devbase
+ pos
+ PCI_CAP_LIST_NEXT
)) {
252 u8 id
= readb(devbase
+ pos
+ PCI_CAP_LIST_ID
);
253 if (id
== PCI_CAP_ID_HT_IRQCONF
) {
254 id
= readb(devbase
+ pos
+ 3);
262 base
= devbase
+ pos
;
263 writeb(0x01, base
+ 2);
264 n
= (readl(base
+ 4) >> 16) & 0xff;
266 printk(KERN_INFO
"mpic: - HT:%02x.%x [0x%02x] vendor %04x device %04x"
268 devfn
>> 3, devfn
& 0x7, pos
, vdid
& 0xffff, vdid
>> 16, n
+ 1);
270 for (i
= 0; i
<= n
; i
++) {
271 writeb(0x10 + 2 * i
, base
+ 2);
272 tmp
= readl(base
+ 4);
273 irq
= (tmp
>> 16) & 0xff;
274 DBG("HT PIC index 0x%x, irq 0x%x, tmp: %08x\n", i
, irq
, tmp
);
275 /* mask it , will be unmasked later */
277 writel(tmp
, base
+ 4);
278 mpic
->fixups
[irq
].index
= i
;
279 mpic
->fixups
[irq
].base
= base
;
280 /* Apple HT PIC has a non-standard way of doing EOIs */
281 if ((vdid
& 0xffff) == 0x106b)
282 mpic
->fixups
[irq
].applebase
= devbase
+ 0x60;
284 mpic
->fixups
[irq
].applebase
= NULL
;
285 writeb(0x11 + 2 * i
, base
+ 2);
286 mpic
->fixups
[irq
].data
= readl(base
+ 4) | 0x80000000;
291 static void __init
mpic_scan_ht_pics(struct mpic
*mpic
)
294 u8 __iomem
*cfgspace
;
296 printk(KERN_INFO
"mpic: Setting up HT PICs workarounds for U3/U4\n");
298 /* Allocate fixups array */
299 mpic
->fixups
= alloc_bootmem(128 * sizeof(struct mpic_irq_fixup
));
300 BUG_ON(mpic
->fixups
== NULL
);
301 memset(mpic
->fixups
, 0, 128 * sizeof(struct mpic_irq_fixup
));
304 spin_lock_init(&mpic
->fixup_lock
);
306 /* Map U3 config space. We assume all IO-APICs are on the primary bus
307 * so we only need to map 64kB.
309 cfgspace
= ioremap(0xf2000000, 0x10000);
310 BUG_ON(cfgspace
== NULL
);
312 /* Now we scan all slots. We do a very quick scan, we read the header
313 * type, vendor ID and device ID only, that's plenty enough
315 for (devfn
= 0; devfn
< 0x100; devfn
++) {
316 u8 __iomem
*devbase
= cfgspace
+ (devfn
<< 8);
317 u8 hdr_type
= readb(devbase
+ PCI_HEADER_TYPE
);
318 u32 l
= readl(devbase
+ PCI_VENDOR_ID
);
321 DBG("devfn %x, l: %x\n", devfn
, l
);
323 /* If no device, skip */
324 if (l
== 0xffffffff || l
== 0x00000000 ||
325 l
== 0x0000ffff || l
== 0xffff0000)
327 /* Check if is supports capability lists */
328 s
= readw(devbase
+ PCI_STATUS
);
329 if (!(s
& PCI_STATUS_CAP_LIST
))
332 mpic_scan_ht_pic(mpic
, devbase
, devfn
, l
);
335 /* next device, if function 0 */
336 if (PCI_FUNC(devfn
) == 0 && (hdr_type
& 0x80) == 0)
341 #endif /* CONFIG_MPIC_BROKEN_U3 */
344 /* Find an mpic associated with a given linux interrupt */
345 static struct mpic
*mpic_find(unsigned int irq
, unsigned int *is_ipi
)
347 struct mpic
*mpic
= mpics
;
350 /* search IPIs first since they may override the main interrupts */
351 if (irq
>= mpic
->ipi_offset
&& irq
< (mpic
->ipi_offset
+ 4)) {
356 if (irq
>= mpic
->irq_offset
&&
357 irq
< (mpic
->irq_offset
+ mpic
->irq_count
)) {
367 /* Convert a cpu mask from logical to physical cpu numbers. */
368 static inline u32
mpic_physmask(u32 cpumask
)
373 for (i
= 0; i
< NR_CPUS
; ++i
, cpumask
>>= 1)
374 mask
|= (cpumask
& 1) << get_hard_smp_processor_id(i
);
379 /* Get the mpic structure from the IPI number */
380 static inline struct mpic
* mpic_from_ipi(unsigned int ipi
)
382 return container_of(irq_desc
[ipi
].handler
, struct mpic
, hc_ipi
);
386 /* Get the mpic structure from the irq number */
387 static inline struct mpic
* mpic_from_irq(unsigned int irq
)
389 return container_of(irq_desc
[irq
].handler
, struct mpic
, hc_irq
);
393 static inline void mpic_eoi(struct mpic
*mpic
)
395 mpic_cpu_write(MPIC_CPU_EOI
, 0);
396 (void)mpic_cpu_read(MPIC_CPU_WHOAMI
);
400 static irqreturn_t
mpic_ipi_action(int irq
, void *dev_id
, struct pt_regs
*regs
)
402 struct mpic
*mpic
= dev_id
;
404 smp_message_recv(irq
- mpic
->ipi_offset
, regs
);
407 #endif /* CONFIG_SMP */
410 * Linux descriptor level callbacks
414 static void mpic_enable_irq(unsigned int irq
)
416 unsigned int loops
= 100000;
417 struct mpic
*mpic
= mpic_from_irq(irq
);
418 unsigned int src
= irq
- mpic
->irq_offset
;
420 DBG("%p: %s: enable_irq: %d (src %d)\n", mpic
, mpic
->name
, irq
, src
);
422 mpic_irq_write(src
, MPIC_IRQ_VECTOR_PRI
,
423 mpic_irq_read(src
, MPIC_IRQ_VECTOR_PRI
) &
426 /* make sure mask gets to controller before we return to user */
429 printk(KERN_ERR
"mpic_enable_irq timeout\n");
432 } while(mpic_irq_read(src
, MPIC_IRQ_VECTOR_PRI
) & MPIC_VECPRI_MASK
);
434 #ifdef CONFIG_MPIC_BROKEN_U3
435 if (mpic
->flags
& MPIC_BROKEN_U3
) {
436 unsigned int src
= irq
- mpic
->irq_offset
;
437 if (mpic_is_ht_interrupt(mpic
, src
) &&
438 (irq_desc
[irq
].status
& IRQ_LEVEL
))
439 mpic_ht_end_irq(mpic
, src
);
441 #endif /* CONFIG_MPIC_BROKEN_U3 */
444 static unsigned int mpic_startup_irq(unsigned int irq
)
446 #ifdef CONFIG_MPIC_BROKEN_U3
447 struct mpic
*mpic
= mpic_from_irq(irq
);
448 unsigned int src
= irq
- mpic
->irq_offset
;
450 if (mpic_is_ht_interrupt(mpic
, src
))
451 mpic_startup_ht_interrupt(mpic
, src
, irq_desc
[irq
].status
);
453 #endif /* CONFIG_MPIC_BROKEN_U3 */
455 mpic_enable_irq(irq
);
460 static void mpic_disable_irq(unsigned int irq
)
462 unsigned int loops
= 100000;
463 struct mpic
*mpic
= mpic_from_irq(irq
);
464 unsigned int src
= irq
- mpic
->irq_offset
;
466 DBG("%s: disable_irq: %d (src %d)\n", mpic
->name
, irq
, src
);
468 mpic_irq_write(src
, MPIC_IRQ_VECTOR_PRI
,
469 mpic_irq_read(src
, MPIC_IRQ_VECTOR_PRI
) |
472 /* make sure mask gets to controller before we return to user */
475 printk(KERN_ERR
"mpic_enable_irq timeout\n");
478 } while(!(mpic_irq_read(src
, MPIC_IRQ_VECTOR_PRI
) & MPIC_VECPRI_MASK
));
481 static void mpic_shutdown_irq(unsigned int irq
)
483 #ifdef CONFIG_MPIC_BROKEN_U3
484 struct mpic
*mpic
= mpic_from_irq(irq
);
485 unsigned int src
= irq
- mpic
->irq_offset
;
487 if (mpic_is_ht_interrupt(mpic
, src
))
488 mpic_shutdown_ht_interrupt(mpic
, src
, irq_desc
[irq
].status
);
490 #endif /* CONFIG_MPIC_BROKEN_U3 */
492 mpic_disable_irq(irq
);
495 static void mpic_end_irq(unsigned int irq
)
497 struct mpic
*mpic
= mpic_from_irq(irq
);
500 DBG("%s: end_irq: %d\n", mpic
->name
, irq
);
502 /* We always EOI on end_irq() even for edge interrupts since that
503 * should only lower the priority, the MPIC should have properly
504 * latched another edge interrupt coming in anyway
507 #ifdef CONFIG_MPIC_BROKEN_U3
508 if (mpic
->flags
& MPIC_BROKEN_U3
) {
509 unsigned int src
= irq
- mpic
->irq_offset
;
510 if (mpic_is_ht_interrupt(mpic
, src
) &&
511 (irq_desc
[irq
].status
& IRQ_LEVEL
))
512 mpic_ht_end_irq(mpic
, src
);
514 #endif /* CONFIG_MPIC_BROKEN_U3 */
521 static void mpic_enable_ipi(unsigned int irq
)
523 struct mpic
*mpic
= mpic_from_ipi(irq
);
524 unsigned int src
= irq
- mpic
->ipi_offset
;
526 DBG("%s: enable_ipi: %d (ipi %d)\n", mpic
->name
, irq
, src
);
527 mpic_ipi_write(src
, mpic_ipi_read(src
) & ~MPIC_VECPRI_MASK
);
530 static void mpic_disable_ipi(unsigned int irq
)
532 /* NEVER disable an IPI... that's just plain wrong! */
535 static void mpic_end_ipi(unsigned int irq
)
537 struct mpic
*mpic
= mpic_from_ipi(irq
);
540 * IPIs are marked IRQ_PER_CPU. This has the side effect of
541 * preventing the IRQ_PENDING/IRQ_INPROGRESS logic from
542 * applying to them. We EOI them late to avoid re-entering.
543 * We mark IPI's with SA_INTERRUPT as they must run with
549 #endif /* CONFIG_SMP */
551 static void mpic_set_affinity(unsigned int irq
, cpumask_t cpumask
)
553 struct mpic
*mpic
= mpic_from_irq(irq
);
557 cpus_and(tmp
, cpumask
, cpu_online_map
);
559 mpic_irq_write(irq
- mpic
->irq_offset
, MPIC_IRQ_DESTINATION
,
560 mpic_physmask(cpus_addr(tmp
)[0]));
569 struct mpic
* __init
mpic_alloc(unsigned long phys_addr
,
571 unsigned int isu_size
,
572 unsigned int irq_offset
,
573 unsigned int irq_count
,
574 unsigned int ipi_offset
,
575 unsigned char *senses
,
576 unsigned int senses_count
,
584 mpic
= alloc_bootmem(sizeof(struct mpic
));
589 memset(mpic
, 0, sizeof(struct mpic
));
592 mpic
->hc_irq
.typename
= name
;
593 mpic
->hc_irq
.startup
= mpic_startup_irq
;
594 mpic
->hc_irq
.shutdown
= mpic_shutdown_irq
;
595 mpic
->hc_irq
.enable
= mpic_enable_irq
;
596 mpic
->hc_irq
.disable
= mpic_disable_irq
;
597 mpic
->hc_irq
.end
= mpic_end_irq
;
598 if (flags
& MPIC_PRIMARY
)
599 mpic
->hc_irq
.set_affinity
= mpic_set_affinity
;
601 mpic
->hc_ipi
.typename
= name
;
602 mpic
->hc_ipi
.enable
= mpic_enable_ipi
;
603 mpic
->hc_ipi
.disable
= mpic_disable_ipi
;
604 mpic
->hc_ipi
.end
= mpic_end_ipi
;
605 #endif /* CONFIG_SMP */
608 mpic
->isu_size
= isu_size
;
609 mpic
->irq_offset
= irq_offset
;
610 mpic
->irq_count
= irq_count
;
611 mpic
->ipi_offset
= ipi_offset
;
612 mpic
->num_sources
= 0; /* so far */
613 mpic
->senses
= senses
;
614 mpic
->senses_count
= senses_count
;
616 /* Map the global registers */
617 mpic
->gregs
= ioremap(phys_addr
+ MPIC_GREG_BASE
, 0x1000);
618 mpic
->tmregs
= mpic
->gregs
+ ((MPIC_TIMER_BASE
- MPIC_GREG_BASE
) >> 2);
619 BUG_ON(mpic
->gregs
== NULL
);
622 if (flags
& MPIC_WANTS_RESET
) {
623 mpic_write(mpic
->gregs
, MPIC_GREG_GLOBAL_CONF_0
,
624 mpic_read(mpic
->gregs
, MPIC_GREG_GLOBAL_CONF_0
)
625 | MPIC_GREG_GCONF_RESET
);
626 while( mpic_read(mpic
->gregs
, MPIC_GREG_GLOBAL_CONF_0
)
627 & MPIC_GREG_GCONF_RESET
)
631 /* Read feature register, calculate num CPUs and, for non-ISU
632 * MPICs, num sources as well. On ISU MPICs, sources are counted
635 reg
= mpic_read(mpic
->gregs
, MPIC_GREG_FEATURE_0
);
636 mpic
->num_cpus
= ((reg
& MPIC_GREG_FEATURE_LAST_CPU_MASK
)
637 >> MPIC_GREG_FEATURE_LAST_CPU_SHIFT
) + 1;
639 mpic
->num_sources
= ((reg
& MPIC_GREG_FEATURE_LAST_SRC_MASK
)
640 >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT
) + 1;
642 /* Map the per-CPU registers */
643 for (i
= 0; i
< mpic
->num_cpus
; i
++) {
644 mpic
->cpuregs
[i
] = ioremap(phys_addr
+ MPIC_CPU_BASE
+
645 i
* MPIC_CPU_STRIDE
, 0x1000);
646 BUG_ON(mpic
->cpuregs
[i
] == NULL
);
649 /* Initialize main ISU if none provided */
650 if (mpic
->isu_size
== 0) {
651 mpic
->isu_size
= mpic
->num_sources
;
652 mpic
->isus
[0] = ioremap(phys_addr
+ MPIC_IRQ_BASE
,
653 MPIC_IRQ_STRIDE
* mpic
->isu_size
);
654 BUG_ON(mpic
->isus
[0] == NULL
);
656 mpic
->isu_shift
= 1 + __ilog2(mpic
->isu_size
- 1);
657 mpic
->isu_mask
= (1 << mpic
->isu_shift
) - 1;
659 /* Display version */
660 switch (reg
& MPIC_GREG_FEATURE_VERSION_MASK
) {
674 printk(KERN_INFO
"mpic: Setting up MPIC \"%s\" version %s at %lx, max %d CPUs\n",
675 name
, vers
, phys_addr
, mpic
->num_cpus
);
676 printk(KERN_INFO
"mpic: ISU size: %d, shift: %d, mask: %x\n", mpic
->isu_size
,
677 mpic
->isu_shift
, mpic
->isu_mask
);
682 if (flags
& MPIC_PRIMARY
)
688 void __init
mpic_assign_isu(struct mpic
*mpic
, unsigned int isu_num
,
689 unsigned long phys_addr
)
691 unsigned int isu_first
= isu_num
* mpic
->isu_size
;
693 BUG_ON(isu_num
>= MPIC_MAX_ISU
);
695 mpic
->isus
[isu_num
] = ioremap(phys_addr
, MPIC_IRQ_STRIDE
* mpic
->isu_size
);
696 if ((isu_first
+ mpic
->isu_size
) > mpic
->num_sources
)
697 mpic
->num_sources
= isu_first
+ mpic
->isu_size
;
700 void __init
mpic_setup_cascade(unsigned int irq
, mpic_cascade_t handler
,
703 struct mpic
*mpic
= mpic_find(irq
, NULL
);
706 /* Synchronization here is a bit dodgy, so don't try to replace cascade
707 * interrupts on the fly too often ... but normally it's set up at boot.
709 spin_lock_irqsave(&mpic_lock
, flags
);
711 mpic_disable_irq(mpic
->cascade_vec
+ mpic
->irq_offset
);
712 mpic
->cascade
= NULL
;
714 mpic
->cascade_vec
= irq
- mpic
->irq_offset
;
715 mpic
->cascade_data
= data
;
717 mpic
->cascade
= handler
;
718 mpic_enable_irq(irq
);
719 spin_unlock_irqrestore(&mpic_lock
, flags
);
722 void __init
mpic_init(struct mpic
*mpic
)
726 BUG_ON(mpic
->num_sources
== 0);
728 printk(KERN_INFO
"mpic: Initializing for %d sources\n", mpic
->num_sources
);
730 /* Set current processor priority to max */
731 mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI
, 0xf);
733 /* Initialize timers: just disable them all */
734 for (i
= 0; i
< 4; i
++) {
735 mpic_write(mpic
->tmregs
,
736 i
* MPIC_TIMER_STRIDE
+ MPIC_TIMER_DESTINATION
, 0);
737 mpic_write(mpic
->tmregs
,
738 i
* MPIC_TIMER_STRIDE
+ MPIC_TIMER_VECTOR_PRI
,
740 (MPIC_VEC_TIMER_0
+ i
));
743 /* Initialize IPIs to our reserved vectors and mark them disabled for now */
744 mpic_test_broken_ipi(mpic
);
745 for (i
= 0; i
< 4; i
++) {
748 (10 << MPIC_VECPRI_PRIORITY_SHIFT
) |
749 (MPIC_VEC_IPI_0
+ i
));
751 if (!(mpic
->flags
& MPIC_PRIMARY
))
753 irq_desc
[mpic
->ipi_offset
+i
].status
|= IRQ_PER_CPU
;
754 irq_desc
[mpic
->ipi_offset
+i
].handler
= &mpic
->hc_ipi
;
755 #endif /* CONFIG_SMP */
758 /* Initialize interrupt sources */
759 if (mpic
->irq_count
== 0)
760 mpic
->irq_count
= mpic
->num_sources
;
762 #ifdef CONFIG_MPIC_BROKEN_U3
763 /* Do the HT PIC fixups on U3 broken mpic */
764 DBG("MPIC flags: %x\n", mpic
->flags
);
765 if ((mpic
->flags
& MPIC_BROKEN_U3
) && (mpic
->flags
& MPIC_PRIMARY
))
766 mpic_scan_ht_pics(mpic
);
767 #endif /* CONFIG_MPIC_BROKEN_U3 */
769 for (i
= 0; i
< mpic
->num_sources
; i
++) {
770 /* start with vector = source number, and masked */
771 u32 vecpri
= MPIC_VECPRI_MASK
| i
| (8 << MPIC_VECPRI_PRIORITY_SHIFT
);
774 /* if it's an IPI, we skip it */
775 if ((mpic
->irq_offset
+ i
) >= (mpic
->ipi_offset
+ i
) &&
776 (mpic
->irq_offset
+ i
) < (mpic
->ipi_offset
+ i
+ 4))
779 /* do senses munging */
780 if (mpic
->senses
&& i
< mpic
->senses_count
) {
781 if (mpic
->senses
[i
] & IRQ_SENSE_LEVEL
)
782 vecpri
|= MPIC_VECPRI_SENSE_LEVEL
;
783 if (mpic
->senses
[i
] & IRQ_POLARITY_POSITIVE
)
784 vecpri
|= MPIC_VECPRI_POLARITY_POSITIVE
;
786 vecpri
|= MPIC_VECPRI_SENSE_LEVEL
;
788 /* remember if it was a level interrupts */
789 level
= (vecpri
& MPIC_VECPRI_SENSE_LEVEL
);
791 /* deal with broken U3 */
792 if (mpic
->flags
& MPIC_BROKEN_U3
) {
793 #ifdef CONFIG_MPIC_BROKEN_U3
794 if (mpic_is_ht_interrupt(mpic
, i
)) {
795 vecpri
&= ~(MPIC_VECPRI_SENSE_MASK
|
796 MPIC_VECPRI_POLARITY_MASK
);
797 vecpri
|= MPIC_VECPRI_POLARITY_POSITIVE
;
800 printk(KERN_ERR
"mpic: BROKEN_U3 set, but CONFIG doesn't match\n");
804 DBG("setup source %d, vecpri: %08x, level: %d\n", i
, vecpri
,
808 mpic_irq_write(i
, MPIC_IRQ_VECTOR_PRI
, vecpri
);
809 mpic_irq_write(i
, MPIC_IRQ_DESTINATION
,
810 1 << hard_smp_processor_id());
812 /* init linux descriptors */
813 if (i
< mpic
->irq_count
) {
814 irq_desc
[mpic
->irq_offset
+i
].status
= level
? IRQ_LEVEL
: 0;
815 irq_desc
[mpic
->irq_offset
+i
].handler
= &mpic
->hc_irq
;
819 /* Init spurrious vector */
820 mpic_write(mpic
->gregs
, MPIC_GREG_SPURIOUS
, MPIC_VEC_SPURRIOUS
);
822 /* Disable 8259 passthrough */
823 mpic_write(mpic
->gregs
, MPIC_GREG_GLOBAL_CONF_0
,
824 mpic_read(mpic
->gregs
, MPIC_GREG_GLOBAL_CONF_0
)
825 | MPIC_GREG_GCONF_8259_PTHROU_DIS
);
827 /* Set current processor priority to 0 */
828 mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI
, 0);
833 void mpic_irq_set_priority(unsigned int irq
, unsigned int pri
)
836 struct mpic
*mpic
= mpic_find(irq
, &is_ipi
);
840 spin_lock_irqsave(&mpic_lock
, flags
);
842 reg
= mpic_ipi_read(irq
- mpic
->ipi_offset
) &
843 ~MPIC_VECPRI_PRIORITY_MASK
;
844 mpic_ipi_write(irq
- mpic
->ipi_offset
,
845 reg
| (pri
<< MPIC_VECPRI_PRIORITY_SHIFT
));
847 reg
= mpic_irq_read(irq
- mpic
->irq_offset
,MPIC_IRQ_VECTOR_PRI
)
848 & ~MPIC_VECPRI_PRIORITY_MASK
;
849 mpic_irq_write(irq
- mpic
->irq_offset
, MPIC_IRQ_VECTOR_PRI
,
850 reg
| (pri
<< MPIC_VECPRI_PRIORITY_SHIFT
));
852 spin_unlock_irqrestore(&mpic_lock
, flags
);
855 unsigned int mpic_irq_get_priority(unsigned int irq
)
858 struct mpic
*mpic
= mpic_find(irq
, &is_ipi
);
862 spin_lock_irqsave(&mpic_lock
, flags
);
864 reg
= mpic_ipi_read(irq
- mpic
->ipi_offset
);
866 reg
= mpic_irq_read(irq
- mpic
->irq_offset
, MPIC_IRQ_VECTOR_PRI
);
867 spin_unlock_irqrestore(&mpic_lock
, flags
);
868 return (reg
& MPIC_VECPRI_PRIORITY_MASK
) >> MPIC_VECPRI_PRIORITY_SHIFT
;
871 void mpic_setup_this_cpu(void)
874 struct mpic
*mpic
= mpic_primary
;
876 u32 msk
= 1 << hard_smp_processor_id();
879 BUG_ON(mpic
== NULL
);
881 DBG("%s: setup_this_cpu(%d)\n", mpic
->name
, hard_smp_processor_id());
883 spin_lock_irqsave(&mpic_lock
, flags
);
885 /* let the mpic know we want intrs. default affinity is 0xffffffff
886 * until changed via /proc. That's how it's done on x86. If we want
887 * it differently, then we should make sure we also change the default
888 * values of irq_affinity in irq.c.
890 if (distribute_irqs
) {
891 for (i
= 0; i
< mpic
->num_sources
; i
++)
892 mpic_irq_write(i
, MPIC_IRQ_DESTINATION
,
893 mpic_irq_read(i
, MPIC_IRQ_DESTINATION
) | msk
);
896 /* Set current processor priority to 0 */
897 mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI
, 0);
899 spin_unlock_irqrestore(&mpic_lock
, flags
);
900 #endif /* CONFIG_SMP */
903 int mpic_cpu_get_priority(void)
905 struct mpic
*mpic
= mpic_primary
;
907 return mpic_cpu_read(MPIC_CPU_CURRENT_TASK_PRI
);
910 void mpic_cpu_set_priority(int prio
)
912 struct mpic
*mpic
= mpic_primary
;
914 prio
&= MPIC_CPU_TASKPRI_MASK
;
915 mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI
, prio
);
919 * XXX: someone who knows mpic should check this.
920 * do we need to eoi the ipi including for kexec cpu here (see xics comments)?
921 * or can we reset the mpic in the new kernel?
923 void mpic_teardown_this_cpu(int secondary
)
925 struct mpic
*mpic
= mpic_primary
;
927 u32 msk
= 1 << hard_smp_processor_id();
930 BUG_ON(mpic
== NULL
);
932 DBG("%s: teardown_this_cpu(%d)\n", mpic
->name
, hard_smp_processor_id());
933 spin_lock_irqsave(&mpic_lock
, flags
);
935 /* let the mpic know we don't want intrs. */
936 for (i
= 0; i
< mpic
->num_sources
; i
++)
937 mpic_irq_write(i
, MPIC_IRQ_DESTINATION
,
938 mpic_irq_read(i
, MPIC_IRQ_DESTINATION
) & ~msk
);
940 /* Set current processor priority to max */
941 mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI
, 0xf);
943 spin_unlock_irqrestore(&mpic_lock
, flags
);
947 void mpic_send_ipi(unsigned int ipi_no
, unsigned int cpu_mask
)
949 struct mpic
*mpic
= mpic_primary
;
951 BUG_ON(mpic
== NULL
);
954 DBG("%s: send_ipi(ipi_no: %d)\n", mpic
->name
, ipi_no
);
957 mpic_cpu_write(MPIC_CPU_IPI_DISPATCH_0
+ ipi_no
* 0x10,
958 mpic_physmask(cpu_mask
& cpus_addr(cpu_online_map
)[0]));
961 int mpic_get_one_irq(struct mpic
*mpic
, struct pt_regs
*regs
)
965 irq
= mpic_cpu_read(MPIC_CPU_INTACK
) & MPIC_VECPRI_VECTOR_MASK
;
967 DBG("%s: get_one_irq(): %d\n", mpic
->name
, irq
);
969 if (mpic
->cascade
&& irq
== mpic
->cascade_vec
) {
971 DBG("%s: cascading ...\n", mpic
->name
);
973 irq
= mpic
->cascade(regs
, mpic
->cascade_data
);
977 if (unlikely(irq
== MPIC_VEC_SPURRIOUS
))
979 if (irq
< MPIC_VEC_IPI_0
) {
981 DBG("%s: irq %d\n", mpic
->name
, irq
+ mpic
->irq_offset
);
983 return irq
+ mpic
->irq_offset
;
986 DBG("%s: ipi %d !\n", mpic
->name
, irq
- MPIC_VEC_IPI_0
);
988 return irq
- MPIC_VEC_IPI_0
+ mpic
->ipi_offset
;
991 int mpic_get_irq(struct pt_regs
*regs
)
993 struct mpic
*mpic
= mpic_primary
;
995 BUG_ON(mpic
== NULL
);
997 return mpic_get_one_irq(mpic
, regs
);
1002 void mpic_request_ipis(void)
1004 struct mpic
*mpic
= mpic_primary
;
1006 BUG_ON(mpic
== NULL
);
1008 printk("requesting IPIs ... \n");
1010 /* IPIs are marked SA_INTERRUPT as they must run with irqs disabled */
1011 request_irq(mpic
->ipi_offset
+0, mpic_ipi_action
, SA_INTERRUPT
,
1012 "IPI0 (call function)", mpic
);
1013 request_irq(mpic
->ipi_offset
+1, mpic_ipi_action
, SA_INTERRUPT
,
1014 "IPI1 (reschedule)", mpic
);
1015 request_irq(mpic
->ipi_offset
+2, mpic_ipi_action
, SA_INTERRUPT
,
1016 "IPI2 (unused)", mpic
);
1017 request_irq(mpic
->ipi_offset
+3, mpic_ipi_action
, SA_INTERRUPT
,
1018 "IPI3 (debugger break)", mpic
);
1020 printk("IPIs requested... \n");
1023 void smp_mpic_message_pass(int target
, int msg
)
1025 /* make sure we're sending something that translates to an IPI */
1026 if ((unsigned int)msg
> 3) {
1027 printk("SMP %d: smp_message_pass: unknown msg %d\n",
1028 smp_processor_id(), msg
);
1033 mpic_send_ipi(msg
, 0xffffffff);
1035 case MSG_ALL_BUT_SELF
:
1036 mpic_send_ipi(msg
, 0xffffffff & ~(1 << smp_processor_id()));
1039 mpic_send_ipi(msg
, 1 << target
);
1043 #endif /* CONFIG_SMP */