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Merge tag 'md-3.9-fixes' of git://neil.brown.name/md
[deliverable/linux.git] / arch / powerpc / sysdev / mpic.c
1 /*
2 * arch/powerpc/kernel/mpic.c
3 *
4 * Driver for interrupt controllers following the OpenPIC standard, the
5 * common implementation beeing IBM's MPIC. This driver also can deal
6 * with various broken implementations of this HW.
7 *
8 * Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp.
9 * Copyright 2010-2012 Freescale Semiconductor, Inc.
10 *
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file COPYING in the main directory of this archive
13 * for more details.
14 */
15
16 #undef DEBUG
17 #undef DEBUG_IPI
18 #undef DEBUG_IRQ
19 #undef DEBUG_LOW
20
21 #include <linux/types.h>
22 #include <linux/kernel.h>
23 #include <linux/init.h>
24 #include <linux/irq.h>
25 #include <linux/smp.h>
26 #include <linux/interrupt.h>
27 #include <linux/bootmem.h>
28 #include <linux/spinlock.h>
29 #include <linux/pci.h>
30 #include <linux/slab.h>
31 #include <linux/syscore_ops.h>
32 #include <linux/ratelimit.h>
33
34 #include <asm/ptrace.h>
35 #include <asm/signal.h>
36 #include <asm/io.h>
37 #include <asm/pgtable.h>
38 #include <asm/irq.h>
39 #include <asm/machdep.h>
40 #include <asm/mpic.h>
41 #include <asm/smp.h>
42
43 #include "mpic.h"
44
45 #ifdef DEBUG
46 #define DBG(fmt...) printk(fmt)
47 #else
48 #define DBG(fmt...)
49 #endif
50
51 static struct mpic *mpics;
52 static struct mpic *mpic_primary;
53 static DEFINE_RAW_SPINLOCK(mpic_lock);
54
55 #ifdef CONFIG_PPC32 /* XXX for now */
56 #ifdef CONFIG_IRQ_ALL_CPUS
57 #define distribute_irqs (!(mpic->flags & MPIC_SINGLE_DEST_CPU))
58 #else
59 #define distribute_irqs (0)
60 #endif
61 #endif
62
63 #ifdef CONFIG_MPIC_WEIRD
64 static u32 mpic_infos[][MPIC_IDX_END] = {
65 [0] = { /* Original OpenPIC compatible MPIC */
66 MPIC_GREG_BASE,
67 MPIC_GREG_FEATURE_0,
68 MPIC_GREG_GLOBAL_CONF_0,
69 MPIC_GREG_VENDOR_ID,
70 MPIC_GREG_IPI_VECTOR_PRI_0,
71 MPIC_GREG_IPI_STRIDE,
72 MPIC_GREG_SPURIOUS,
73 MPIC_GREG_TIMER_FREQ,
74
75 MPIC_TIMER_BASE,
76 MPIC_TIMER_STRIDE,
77 MPIC_TIMER_CURRENT_CNT,
78 MPIC_TIMER_BASE_CNT,
79 MPIC_TIMER_VECTOR_PRI,
80 MPIC_TIMER_DESTINATION,
81
82 MPIC_CPU_BASE,
83 MPIC_CPU_STRIDE,
84 MPIC_CPU_IPI_DISPATCH_0,
85 MPIC_CPU_IPI_DISPATCH_STRIDE,
86 MPIC_CPU_CURRENT_TASK_PRI,
87 MPIC_CPU_WHOAMI,
88 MPIC_CPU_INTACK,
89 MPIC_CPU_EOI,
90 MPIC_CPU_MCACK,
91
92 MPIC_IRQ_BASE,
93 MPIC_IRQ_STRIDE,
94 MPIC_IRQ_VECTOR_PRI,
95 MPIC_VECPRI_VECTOR_MASK,
96 MPIC_VECPRI_POLARITY_POSITIVE,
97 MPIC_VECPRI_POLARITY_NEGATIVE,
98 MPIC_VECPRI_SENSE_LEVEL,
99 MPIC_VECPRI_SENSE_EDGE,
100 MPIC_VECPRI_POLARITY_MASK,
101 MPIC_VECPRI_SENSE_MASK,
102 MPIC_IRQ_DESTINATION
103 },
104 [1] = { /* Tsi108/109 PIC */
105 TSI108_GREG_BASE,
106 TSI108_GREG_FEATURE_0,
107 TSI108_GREG_GLOBAL_CONF_0,
108 TSI108_GREG_VENDOR_ID,
109 TSI108_GREG_IPI_VECTOR_PRI_0,
110 TSI108_GREG_IPI_STRIDE,
111 TSI108_GREG_SPURIOUS,
112 TSI108_GREG_TIMER_FREQ,
113
114 TSI108_TIMER_BASE,
115 TSI108_TIMER_STRIDE,
116 TSI108_TIMER_CURRENT_CNT,
117 TSI108_TIMER_BASE_CNT,
118 TSI108_TIMER_VECTOR_PRI,
119 TSI108_TIMER_DESTINATION,
120
121 TSI108_CPU_BASE,
122 TSI108_CPU_STRIDE,
123 TSI108_CPU_IPI_DISPATCH_0,
124 TSI108_CPU_IPI_DISPATCH_STRIDE,
125 TSI108_CPU_CURRENT_TASK_PRI,
126 TSI108_CPU_WHOAMI,
127 TSI108_CPU_INTACK,
128 TSI108_CPU_EOI,
129 TSI108_CPU_MCACK,
130
131 TSI108_IRQ_BASE,
132 TSI108_IRQ_STRIDE,
133 TSI108_IRQ_VECTOR_PRI,
134 TSI108_VECPRI_VECTOR_MASK,
135 TSI108_VECPRI_POLARITY_POSITIVE,
136 TSI108_VECPRI_POLARITY_NEGATIVE,
137 TSI108_VECPRI_SENSE_LEVEL,
138 TSI108_VECPRI_SENSE_EDGE,
139 TSI108_VECPRI_POLARITY_MASK,
140 TSI108_VECPRI_SENSE_MASK,
141 TSI108_IRQ_DESTINATION
142 },
143 };
144
145 #define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name]
146
147 #else /* CONFIG_MPIC_WEIRD */
148
149 #define MPIC_INFO(name) MPIC_##name
150
151 #endif /* CONFIG_MPIC_WEIRD */
152
153 static inline unsigned int mpic_processor_id(struct mpic *mpic)
154 {
155 unsigned int cpu = 0;
156
157 if (!(mpic->flags & MPIC_SECONDARY))
158 cpu = hard_smp_processor_id();
159
160 return cpu;
161 }
162
163 /*
164 * Register accessor functions
165 */
166
167
168 static inline u32 _mpic_read(enum mpic_reg_type type,
169 struct mpic_reg_bank *rb,
170 unsigned int reg)
171 {
172 switch(type) {
173 #ifdef CONFIG_PPC_DCR
174 case mpic_access_dcr:
175 return dcr_read(rb->dhost, reg);
176 #endif
177 case mpic_access_mmio_be:
178 return in_be32(rb->base + (reg >> 2));
179 case mpic_access_mmio_le:
180 default:
181 return in_le32(rb->base + (reg >> 2));
182 }
183 }
184
185 static inline void _mpic_write(enum mpic_reg_type type,
186 struct mpic_reg_bank *rb,
187 unsigned int reg, u32 value)
188 {
189 switch(type) {
190 #ifdef CONFIG_PPC_DCR
191 case mpic_access_dcr:
192 dcr_write(rb->dhost, reg, value);
193 break;
194 #endif
195 case mpic_access_mmio_be:
196 out_be32(rb->base + (reg >> 2), value);
197 break;
198 case mpic_access_mmio_le:
199 default:
200 out_le32(rb->base + (reg >> 2), value);
201 break;
202 }
203 }
204
205 static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi)
206 {
207 enum mpic_reg_type type = mpic->reg_type;
208 unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
209 (ipi * MPIC_INFO(GREG_IPI_STRIDE));
210
211 if ((mpic->flags & MPIC_BROKEN_IPI) && type == mpic_access_mmio_le)
212 type = mpic_access_mmio_be;
213 return _mpic_read(type, &mpic->gregs, offset);
214 }
215
216 static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value)
217 {
218 unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
219 (ipi * MPIC_INFO(GREG_IPI_STRIDE));
220
221 _mpic_write(mpic->reg_type, &mpic->gregs, offset, value);
222 }
223
224 static inline unsigned int mpic_tm_offset(struct mpic *mpic, unsigned int tm)
225 {
226 return (tm >> 2) * MPIC_TIMER_GROUP_STRIDE +
227 (tm & 3) * MPIC_INFO(TIMER_STRIDE);
228 }
229
230 static inline u32 _mpic_tm_read(struct mpic *mpic, unsigned int tm)
231 {
232 unsigned int offset = mpic_tm_offset(mpic, tm) +
233 MPIC_INFO(TIMER_VECTOR_PRI);
234
235 return _mpic_read(mpic->reg_type, &mpic->tmregs, offset);
236 }
237
238 static inline void _mpic_tm_write(struct mpic *mpic, unsigned int tm, u32 value)
239 {
240 unsigned int offset = mpic_tm_offset(mpic, tm) +
241 MPIC_INFO(TIMER_VECTOR_PRI);
242
243 _mpic_write(mpic->reg_type, &mpic->tmregs, offset, value);
244 }
245
246 static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg)
247 {
248 unsigned int cpu = mpic_processor_id(mpic);
249
250 return _mpic_read(mpic->reg_type, &mpic->cpuregs[cpu], reg);
251 }
252
253 static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value)
254 {
255 unsigned int cpu = mpic_processor_id(mpic);
256
257 _mpic_write(mpic->reg_type, &mpic->cpuregs[cpu], reg, value);
258 }
259
260 static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigned int reg)
261 {
262 unsigned int isu = src_no >> mpic->isu_shift;
263 unsigned int idx = src_no & mpic->isu_mask;
264 unsigned int val;
265
266 val = _mpic_read(mpic->reg_type, &mpic->isus[isu],
267 reg + (idx * MPIC_INFO(IRQ_STRIDE)));
268 #ifdef CONFIG_MPIC_BROKEN_REGREAD
269 if (reg == 0)
270 val = (val & (MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY)) |
271 mpic->isu_reg0_shadow[src_no];
272 #endif
273 return val;
274 }
275
276 static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no,
277 unsigned int reg, u32 value)
278 {
279 unsigned int isu = src_no >> mpic->isu_shift;
280 unsigned int idx = src_no & mpic->isu_mask;
281
282 _mpic_write(mpic->reg_type, &mpic->isus[isu],
283 reg + (idx * MPIC_INFO(IRQ_STRIDE)), value);
284
285 #ifdef CONFIG_MPIC_BROKEN_REGREAD
286 if (reg == 0)
287 mpic->isu_reg0_shadow[src_no] =
288 value & ~(MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY);
289 #endif
290 }
291
292 #define mpic_read(b,r) _mpic_read(mpic->reg_type,&(b),(r))
293 #define mpic_write(b,r,v) _mpic_write(mpic->reg_type,&(b),(r),(v))
294 #define mpic_ipi_read(i) _mpic_ipi_read(mpic,(i))
295 #define mpic_ipi_write(i,v) _mpic_ipi_write(mpic,(i),(v))
296 #define mpic_tm_read(i) _mpic_tm_read(mpic,(i))
297 #define mpic_tm_write(i,v) _mpic_tm_write(mpic,(i),(v))
298 #define mpic_cpu_read(i) _mpic_cpu_read(mpic,(i))
299 #define mpic_cpu_write(i,v) _mpic_cpu_write(mpic,(i),(v))
300 #define mpic_irq_read(s,r) _mpic_irq_read(mpic,(s),(r))
301 #define mpic_irq_write(s,r,v) _mpic_irq_write(mpic,(s),(r),(v))
302
303
304 /*
305 * Low level utility functions
306 */
307
308
309 static void _mpic_map_mmio(struct mpic *mpic, phys_addr_t phys_addr,
310 struct mpic_reg_bank *rb, unsigned int offset,
311 unsigned int size)
312 {
313 rb->base = ioremap(phys_addr + offset, size);
314 BUG_ON(rb->base == NULL);
315 }
316
317 #ifdef CONFIG_PPC_DCR
318 static void _mpic_map_dcr(struct mpic *mpic, struct mpic_reg_bank *rb,
319 unsigned int offset, unsigned int size)
320 {
321 phys_addr_t phys_addr = dcr_resource_start(mpic->node, 0);
322 rb->dhost = dcr_map(mpic->node, phys_addr + offset, size);
323 BUG_ON(!DCR_MAP_OK(rb->dhost));
324 }
325
326 static inline void mpic_map(struct mpic *mpic,
327 phys_addr_t phys_addr, struct mpic_reg_bank *rb,
328 unsigned int offset, unsigned int size)
329 {
330 if (mpic->flags & MPIC_USES_DCR)
331 _mpic_map_dcr(mpic, rb, offset, size);
332 else
333 _mpic_map_mmio(mpic, phys_addr, rb, offset, size);
334 }
335 #else /* CONFIG_PPC_DCR */
336 #define mpic_map(m,p,b,o,s) _mpic_map_mmio(m,p,b,o,s)
337 #endif /* !CONFIG_PPC_DCR */
338
339
340
341 /* Check if we have one of those nice broken MPICs with a flipped endian on
342 * reads from IPI registers
343 */
344 static void __init mpic_test_broken_ipi(struct mpic *mpic)
345 {
346 u32 r;
347
348 mpic_write(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0), MPIC_VECPRI_MASK);
349 r = mpic_read(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0));
350
351 if (r == le32_to_cpu(MPIC_VECPRI_MASK)) {
352 printk(KERN_INFO "mpic: Detected reversed IPI registers\n");
353 mpic->flags |= MPIC_BROKEN_IPI;
354 }
355 }
356
357 #ifdef CONFIG_MPIC_U3_HT_IRQS
358
359 /* Test if an interrupt is sourced from HyperTransport (used on broken U3s)
360 * to force the edge setting on the MPIC and do the ack workaround.
361 */
362 static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
363 {
364 if (source >= 128 || !mpic->fixups)
365 return 0;
366 return mpic->fixups[source].base != NULL;
367 }
368
369
370 static inline void mpic_ht_end_irq(struct mpic *mpic, unsigned int source)
371 {
372 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
373
374 if (fixup->applebase) {
375 unsigned int soff = (fixup->index >> 3) & ~3;
376 unsigned int mask = 1U << (fixup->index & 0x1f);
377 writel(mask, fixup->applebase + soff);
378 } else {
379 raw_spin_lock(&mpic->fixup_lock);
380 writeb(0x11 + 2 * fixup->index, fixup->base + 2);
381 writel(fixup->data, fixup->base + 4);
382 raw_spin_unlock(&mpic->fixup_lock);
383 }
384 }
385
386 static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source,
387 bool level)
388 {
389 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
390 unsigned long flags;
391 u32 tmp;
392
393 if (fixup->base == NULL)
394 return;
395
396 DBG("startup_ht_interrupt(0x%x) index: %d\n",
397 source, fixup->index);
398 raw_spin_lock_irqsave(&mpic->fixup_lock, flags);
399 /* Enable and configure */
400 writeb(0x10 + 2 * fixup->index, fixup->base + 2);
401 tmp = readl(fixup->base + 4);
402 tmp &= ~(0x23U);
403 if (level)
404 tmp |= 0x22;
405 writel(tmp, fixup->base + 4);
406 raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags);
407
408 #ifdef CONFIG_PM
409 /* use the lowest bit inverted to the actual HW,
410 * set if this fixup was enabled, clear otherwise */
411 mpic->save_data[source].fixup_data = tmp | 1;
412 #endif
413 }
414
415 static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source)
416 {
417 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
418 unsigned long flags;
419 u32 tmp;
420
421 if (fixup->base == NULL)
422 return;
423
424 DBG("shutdown_ht_interrupt(0x%x)\n", source);
425
426 /* Disable */
427 raw_spin_lock_irqsave(&mpic->fixup_lock, flags);
428 writeb(0x10 + 2 * fixup->index, fixup->base + 2);
429 tmp = readl(fixup->base + 4);
430 tmp |= 1;
431 writel(tmp, fixup->base + 4);
432 raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags);
433
434 #ifdef CONFIG_PM
435 /* use the lowest bit inverted to the actual HW,
436 * set if this fixup was enabled, clear otherwise */
437 mpic->save_data[source].fixup_data = tmp & ~1;
438 #endif
439 }
440
441 #ifdef CONFIG_PCI_MSI
442 static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
443 unsigned int devfn)
444 {
445 u8 __iomem *base;
446 u8 pos, flags;
447 u64 addr = 0;
448
449 for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
450 pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
451 u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
452 if (id == PCI_CAP_ID_HT) {
453 id = readb(devbase + pos + 3);
454 if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_MSI_MAPPING)
455 break;
456 }
457 }
458
459 if (pos == 0)
460 return;
461
462 base = devbase + pos;
463
464 flags = readb(base + HT_MSI_FLAGS);
465 if (!(flags & HT_MSI_FLAGS_FIXED)) {
466 addr = readl(base + HT_MSI_ADDR_LO) & HT_MSI_ADDR_LO_MASK;
467 addr = addr | ((u64)readl(base + HT_MSI_ADDR_HI) << 32);
468 }
469
470 printk(KERN_DEBUG "mpic: - HT:%02x.%x %s MSI mapping found @ 0x%llx\n",
471 PCI_SLOT(devfn), PCI_FUNC(devfn),
472 flags & HT_MSI_FLAGS_ENABLE ? "enabled" : "disabled", addr);
473
474 if (!(flags & HT_MSI_FLAGS_ENABLE))
475 writeb(flags | HT_MSI_FLAGS_ENABLE, base + HT_MSI_FLAGS);
476 }
477 #else
478 static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
479 unsigned int devfn)
480 {
481 return;
482 }
483 #endif
484
485 static void __init mpic_scan_ht_pic(struct mpic *mpic, u8 __iomem *devbase,
486 unsigned int devfn, u32 vdid)
487 {
488 int i, irq, n;
489 u8 __iomem *base;
490 u32 tmp;
491 u8 pos;
492
493 for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
494 pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
495 u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
496 if (id == PCI_CAP_ID_HT) {
497 id = readb(devbase + pos + 3);
498 if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_IRQ)
499 break;
500 }
501 }
502 if (pos == 0)
503 return;
504
505 base = devbase + pos;
506 writeb(0x01, base + 2);
507 n = (readl(base + 4) >> 16) & 0xff;
508
509 printk(KERN_INFO "mpic: - HT:%02x.%x [0x%02x] vendor %04x device %04x"
510 " has %d irqs\n",
511 devfn >> 3, devfn & 0x7, pos, vdid & 0xffff, vdid >> 16, n + 1);
512
513 for (i = 0; i <= n; i++) {
514 writeb(0x10 + 2 * i, base + 2);
515 tmp = readl(base + 4);
516 irq = (tmp >> 16) & 0xff;
517 DBG("HT PIC index 0x%x, irq 0x%x, tmp: %08x\n", i, irq, tmp);
518 /* mask it , will be unmasked later */
519 tmp |= 0x1;
520 writel(tmp, base + 4);
521 mpic->fixups[irq].index = i;
522 mpic->fixups[irq].base = base;
523 /* Apple HT PIC has a non-standard way of doing EOIs */
524 if ((vdid & 0xffff) == 0x106b)
525 mpic->fixups[irq].applebase = devbase + 0x60;
526 else
527 mpic->fixups[irq].applebase = NULL;
528 writeb(0x11 + 2 * i, base + 2);
529 mpic->fixups[irq].data = readl(base + 4) | 0x80000000;
530 }
531 }
532
533
534 static void __init mpic_scan_ht_pics(struct mpic *mpic)
535 {
536 unsigned int devfn;
537 u8 __iomem *cfgspace;
538
539 printk(KERN_INFO "mpic: Setting up HT PICs workarounds for U3/U4\n");
540
541 /* Allocate fixups array */
542 mpic->fixups = kzalloc(128 * sizeof(*mpic->fixups), GFP_KERNEL);
543 BUG_ON(mpic->fixups == NULL);
544
545 /* Init spinlock */
546 raw_spin_lock_init(&mpic->fixup_lock);
547
548 /* Map U3 config space. We assume all IO-APICs are on the primary bus
549 * so we only need to map 64kB.
550 */
551 cfgspace = ioremap(0xf2000000, 0x10000);
552 BUG_ON(cfgspace == NULL);
553
554 /* Now we scan all slots. We do a very quick scan, we read the header
555 * type, vendor ID and device ID only, that's plenty enough
556 */
557 for (devfn = 0; devfn < 0x100; devfn++) {
558 u8 __iomem *devbase = cfgspace + (devfn << 8);
559 u8 hdr_type = readb(devbase + PCI_HEADER_TYPE);
560 u32 l = readl(devbase + PCI_VENDOR_ID);
561 u16 s;
562
563 DBG("devfn %x, l: %x\n", devfn, l);
564
565 /* If no device, skip */
566 if (l == 0xffffffff || l == 0x00000000 ||
567 l == 0x0000ffff || l == 0xffff0000)
568 goto next;
569 /* Check if is supports capability lists */
570 s = readw(devbase + PCI_STATUS);
571 if (!(s & PCI_STATUS_CAP_LIST))
572 goto next;
573
574 mpic_scan_ht_pic(mpic, devbase, devfn, l);
575 mpic_scan_ht_msi(mpic, devbase, devfn);
576
577 next:
578 /* next device, if function 0 */
579 if (PCI_FUNC(devfn) == 0 && (hdr_type & 0x80) == 0)
580 devfn += 7;
581 }
582 }
583
584 #else /* CONFIG_MPIC_U3_HT_IRQS */
585
586 static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
587 {
588 return 0;
589 }
590
591 static void __init mpic_scan_ht_pics(struct mpic *mpic)
592 {
593 }
594
595 #endif /* CONFIG_MPIC_U3_HT_IRQS */
596
597 /* Find an mpic associated with a given linux interrupt */
598 static struct mpic *mpic_find(unsigned int irq)
599 {
600 if (irq < NUM_ISA_INTERRUPTS)
601 return NULL;
602
603 return irq_get_chip_data(irq);
604 }
605
606 /* Determine if the linux irq is an IPI */
607 static unsigned int mpic_is_ipi(struct mpic *mpic, unsigned int src)
608 {
609 return (src >= mpic->ipi_vecs[0] && src <= mpic->ipi_vecs[3]);
610 }
611
612 /* Determine if the linux irq is a timer */
613 static unsigned int mpic_is_tm(struct mpic *mpic, unsigned int src)
614 {
615 return (src >= mpic->timer_vecs[0] && src <= mpic->timer_vecs[7]);
616 }
617
618 /* Convert a cpu mask from logical to physical cpu numbers. */
619 static inline u32 mpic_physmask(u32 cpumask)
620 {
621 int i;
622 u32 mask = 0;
623
624 for (i = 0; i < min(32, NR_CPUS); ++i, cpumask >>= 1)
625 mask |= (cpumask & 1) << get_hard_smp_processor_id(i);
626 return mask;
627 }
628
629 #ifdef CONFIG_SMP
630 /* Get the mpic structure from the IPI number */
631 static inline struct mpic * mpic_from_ipi(struct irq_data *d)
632 {
633 return irq_data_get_irq_chip_data(d);
634 }
635 #endif
636
637 /* Get the mpic structure from the irq number */
638 static inline struct mpic * mpic_from_irq(unsigned int irq)
639 {
640 return irq_get_chip_data(irq);
641 }
642
643 /* Get the mpic structure from the irq data */
644 static inline struct mpic * mpic_from_irq_data(struct irq_data *d)
645 {
646 return irq_data_get_irq_chip_data(d);
647 }
648
649 /* Send an EOI */
650 static inline void mpic_eoi(struct mpic *mpic)
651 {
652 mpic_cpu_write(MPIC_INFO(CPU_EOI), 0);
653 (void)mpic_cpu_read(MPIC_INFO(CPU_WHOAMI));
654 }
655
656 /*
657 * Linux descriptor level callbacks
658 */
659
660
661 void mpic_unmask_irq(struct irq_data *d)
662 {
663 unsigned int loops = 100000;
664 struct mpic *mpic = mpic_from_irq_data(d);
665 unsigned int src = irqd_to_hwirq(d);
666
667 DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, d->irq, src);
668
669 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
670 mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) &
671 ~MPIC_VECPRI_MASK);
672 /* make sure mask gets to controller before we return to user */
673 do {
674 if (!loops--) {
675 printk(KERN_ERR "%s: timeout on hwirq %u\n",
676 __func__, src);
677 break;
678 }
679 } while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK);
680 }
681
682 void mpic_mask_irq(struct irq_data *d)
683 {
684 unsigned int loops = 100000;
685 struct mpic *mpic = mpic_from_irq_data(d);
686 unsigned int src = irqd_to_hwirq(d);
687
688 DBG("%s: disable_irq: %d (src %d)\n", mpic->name, d->irq, src);
689
690 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
691 mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) |
692 MPIC_VECPRI_MASK);
693
694 /* make sure mask gets to controller before we return to user */
695 do {
696 if (!loops--) {
697 printk(KERN_ERR "%s: timeout on hwirq %u\n",
698 __func__, src);
699 break;
700 }
701 } while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK));
702 }
703
704 void mpic_end_irq(struct irq_data *d)
705 {
706 struct mpic *mpic = mpic_from_irq_data(d);
707
708 #ifdef DEBUG_IRQ
709 DBG("%s: end_irq: %d\n", mpic->name, d->irq);
710 #endif
711 /* We always EOI on end_irq() even for edge interrupts since that
712 * should only lower the priority, the MPIC should have properly
713 * latched another edge interrupt coming in anyway
714 */
715
716 mpic_eoi(mpic);
717 }
718
719 #ifdef CONFIG_MPIC_U3_HT_IRQS
720
721 static void mpic_unmask_ht_irq(struct irq_data *d)
722 {
723 struct mpic *mpic = mpic_from_irq_data(d);
724 unsigned int src = irqd_to_hwirq(d);
725
726 mpic_unmask_irq(d);
727
728 if (irqd_is_level_type(d))
729 mpic_ht_end_irq(mpic, src);
730 }
731
732 static unsigned int mpic_startup_ht_irq(struct irq_data *d)
733 {
734 struct mpic *mpic = mpic_from_irq_data(d);
735 unsigned int src = irqd_to_hwirq(d);
736
737 mpic_unmask_irq(d);
738 mpic_startup_ht_interrupt(mpic, src, irqd_is_level_type(d));
739
740 return 0;
741 }
742
743 static void mpic_shutdown_ht_irq(struct irq_data *d)
744 {
745 struct mpic *mpic = mpic_from_irq_data(d);
746 unsigned int src = irqd_to_hwirq(d);
747
748 mpic_shutdown_ht_interrupt(mpic, src);
749 mpic_mask_irq(d);
750 }
751
752 static void mpic_end_ht_irq(struct irq_data *d)
753 {
754 struct mpic *mpic = mpic_from_irq_data(d);
755 unsigned int src = irqd_to_hwirq(d);
756
757 #ifdef DEBUG_IRQ
758 DBG("%s: end_irq: %d\n", mpic->name, d->irq);
759 #endif
760 /* We always EOI on end_irq() even for edge interrupts since that
761 * should only lower the priority, the MPIC should have properly
762 * latched another edge interrupt coming in anyway
763 */
764
765 if (irqd_is_level_type(d))
766 mpic_ht_end_irq(mpic, src);
767 mpic_eoi(mpic);
768 }
769 #endif /* !CONFIG_MPIC_U3_HT_IRQS */
770
771 #ifdef CONFIG_SMP
772
773 static void mpic_unmask_ipi(struct irq_data *d)
774 {
775 struct mpic *mpic = mpic_from_ipi(d);
776 unsigned int src = virq_to_hw(d->irq) - mpic->ipi_vecs[0];
777
778 DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, d->irq, src);
779 mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK);
780 }
781
782 static void mpic_mask_ipi(struct irq_data *d)
783 {
784 /* NEVER disable an IPI... that's just plain wrong! */
785 }
786
787 static void mpic_end_ipi(struct irq_data *d)
788 {
789 struct mpic *mpic = mpic_from_ipi(d);
790
791 /*
792 * IPIs are marked IRQ_PER_CPU. This has the side effect of
793 * preventing the IRQ_PENDING/IRQ_INPROGRESS logic from
794 * applying to them. We EOI them late to avoid re-entering.
795 */
796 mpic_eoi(mpic);
797 }
798
799 #endif /* CONFIG_SMP */
800
801 static void mpic_unmask_tm(struct irq_data *d)
802 {
803 struct mpic *mpic = mpic_from_irq_data(d);
804 unsigned int src = virq_to_hw(d->irq) - mpic->timer_vecs[0];
805
806 DBG("%s: enable_tm: %d (tm %d)\n", mpic->name, d->irq, src);
807 mpic_tm_write(src, mpic_tm_read(src) & ~MPIC_VECPRI_MASK);
808 mpic_tm_read(src);
809 }
810
811 static void mpic_mask_tm(struct irq_data *d)
812 {
813 struct mpic *mpic = mpic_from_irq_data(d);
814 unsigned int src = virq_to_hw(d->irq) - mpic->timer_vecs[0];
815
816 mpic_tm_write(src, mpic_tm_read(src) | MPIC_VECPRI_MASK);
817 mpic_tm_read(src);
818 }
819
820 int mpic_set_affinity(struct irq_data *d, const struct cpumask *cpumask,
821 bool force)
822 {
823 struct mpic *mpic = mpic_from_irq_data(d);
824 unsigned int src = irqd_to_hwirq(d);
825
826 if (mpic->flags & MPIC_SINGLE_DEST_CPU) {
827 int cpuid = irq_choose_cpu(cpumask);
828
829 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid);
830 } else {
831 u32 mask = cpumask_bits(cpumask)[0];
832
833 mask &= cpumask_bits(cpu_online_mask)[0];
834
835 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION),
836 mpic_physmask(mask));
837 }
838
839 return 0;
840 }
841
842 static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type)
843 {
844 /* Now convert sense value */
845 switch(type & IRQ_TYPE_SENSE_MASK) {
846 case IRQ_TYPE_EDGE_RISING:
847 return MPIC_INFO(VECPRI_SENSE_EDGE) |
848 MPIC_INFO(VECPRI_POLARITY_POSITIVE);
849 case IRQ_TYPE_EDGE_FALLING:
850 case IRQ_TYPE_EDGE_BOTH:
851 return MPIC_INFO(VECPRI_SENSE_EDGE) |
852 MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
853 case IRQ_TYPE_LEVEL_HIGH:
854 return MPIC_INFO(VECPRI_SENSE_LEVEL) |
855 MPIC_INFO(VECPRI_POLARITY_POSITIVE);
856 case IRQ_TYPE_LEVEL_LOW:
857 default:
858 return MPIC_INFO(VECPRI_SENSE_LEVEL) |
859 MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
860 }
861 }
862
863 int mpic_set_irq_type(struct irq_data *d, unsigned int flow_type)
864 {
865 struct mpic *mpic = mpic_from_irq_data(d);
866 unsigned int src = irqd_to_hwirq(d);
867 unsigned int vecpri, vold, vnew;
868
869 DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n",
870 mpic, d->irq, src, flow_type);
871
872 if (src >= mpic->num_sources)
873 return -EINVAL;
874
875 vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
876
877 /* We don't support "none" type */
878 if (flow_type == IRQ_TYPE_NONE)
879 flow_type = IRQ_TYPE_DEFAULT;
880
881 /* Default: read HW settings */
882 if (flow_type == IRQ_TYPE_DEFAULT) {
883 switch(vold & (MPIC_INFO(VECPRI_POLARITY_MASK) |
884 MPIC_INFO(VECPRI_SENSE_MASK))) {
885 case MPIC_INFO(VECPRI_SENSE_EDGE) |
886 MPIC_INFO(VECPRI_POLARITY_POSITIVE):
887 flow_type = IRQ_TYPE_EDGE_RISING;
888 break;
889 case MPIC_INFO(VECPRI_SENSE_EDGE) |
890 MPIC_INFO(VECPRI_POLARITY_NEGATIVE):
891 flow_type = IRQ_TYPE_EDGE_FALLING;
892 break;
893 case MPIC_INFO(VECPRI_SENSE_LEVEL) |
894 MPIC_INFO(VECPRI_POLARITY_POSITIVE):
895 flow_type = IRQ_TYPE_LEVEL_HIGH;
896 break;
897 case MPIC_INFO(VECPRI_SENSE_LEVEL) |
898 MPIC_INFO(VECPRI_POLARITY_NEGATIVE):
899 flow_type = IRQ_TYPE_LEVEL_LOW;
900 break;
901 }
902 }
903
904 /* Apply to irq desc */
905 irqd_set_trigger_type(d, flow_type);
906
907 /* Apply to HW */
908 if (mpic_is_ht_interrupt(mpic, src))
909 vecpri = MPIC_VECPRI_POLARITY_POSITIVE |
910 MPIC_VECPRI_SENSE_EDGE;
911 else
912 vecpri = mpic_type_to_vecpri(mpic, flow_type);
913
914 vnew = vold & ~(MPIC_INFO(VECPRI_POLARITY_MASK) |
915 MPIC_INFO(VECPRI_SENSE_MASK));
916 vnew |= vecpri;
917 if (vold != vnew)
918 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew);
919
920 return IRQ_SET_MASK_OK_NOCOPY;
921 }
922
923 void mpic_set_vector(unsigned int virq, unsigned int vector)
924 {
925 struct mpic *mpic = mpic_from_irq(virq);
926 unsigned int src = virq_to_hw(virq);
927 unsigned int vecpri;
928
929 DBG("mpic: set_vector(mpic:@%p,virq:%d,src:%d,vector:0x%x)\n",
930 mpic, virq, src, vector);
931
932 if (src >= mpic->num_sources)
933 return;
934
935 vecpri = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
936 vecpri = vecpri & ~MPIC_INFO(VECPRI_VECTOR_MASK);
937 vecpri |= vector;
938 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
939 }
940
941 void mpic_set_destination(unsigned int virq, unsigned int cpuid)
942 {
943 struct mpic *mpic = mpic_from_irq(virq);
944 unsigned int src = virq_to_hw(virq);
945
946 DBG("mpic: set_destination(mpic:@%p,virq:%d,src:%d,cpuid:0x%x)\n",
947 mpic, virq, src, cpuid);
948
949 if (src >= mpic->num_sources)
950 return;
951
952 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid);
953 }
954
955 static struct irq_chip mpic_irq_chip = {
956 .irq_mask = mpic_mask_irq,
957 .irq_unmask = mpic_unmask_irq,
958 .irq_eoi = mpic_end_irq,
959 .irq_set_type = mpic_set_irq_type,
960 };
961
962 #ifdef CONFIG_SMP
963 static struct irq_chip mpic_ipi_chip = {
964 .irq_mask = mpic_mask_ipi,
965 .irq_unmask = mpic_unmask_ipi,
966 .irq_eoi = mpic_end_ipi,
967 };
968 #endif /* CONFIG_SMP */
969
970 static struct irq_chip mpic_tm_chip = {
971 .irq_mask = mpic_mask_tm,
972 .irq_unmask = mpic_unmask_tm,
973 .irq_eoi = mpic_end_irq,
974 };
975
976 #ifdef CONFIG_MPIC_U3_HT_IRQS
977 static struct irq_chip mpic_irq_ht_chip = {
978 .irq_startup = mpic_startup_ht_irq,
979 .irq_shutdown = mpic_shutdown_ht_irq,
980 .irq_mask = mpic_mask_irq,
981 .irq_unmask = mpic_unmask_ht_irq,
982 .irq_eoi = mpic_end_ht_irq,
983 .irq_set_type = mpic_set_irq_type,
984 };
985 #endif /* CONFIG_MPIC_U3_HT_IRQS */
986
987
988 static int mpic_host_match(struct irq_domain *h, struct device_node *node)
989 {
990 /* Exact match, unless mpic node is NULL */
991 return h->of_node == NULL || h->of_node == node;
992 }
993
994 static int mpic_host_map(struct irq_domain *h, unsigned int virq,
995 irq_hw_number_t hw)
996 {
997 struct mpic *mpic = h->host_data;
998 struct irq_chip *chip;
999
1000 DBG("mpic: map virq %d, hwirq 0x%lx\n", virq, hw);
1001
1002 if (hw == mpic->spurious_vec)
1003 return -EINVAL;
1004 if (mpic->protected && test_bit(hw, mpic->protected))
1005 return -EINVAL;
1006
1007 #ifdef CONFIG_SMP
1008 else if (hw >= mpic->ipi_vecs[0]) {
1009 WARN_ON(mpic->flags & MPIC_SECONDARY);
1010
1011 DBG("mpic: mapping as IPI\n");
1012 irq_set_chip_data(virq, mpic);
1013 irq_set_chip_and_handler(virq, &mpic->hc_ipi,
1014 handle_percpu_irq);
1015 return 0;
1016 }
1017 #endif /* CONFIG_SMP */
1018
1019 if (hw >= mpic->timer_vecs[0] && hw <= mpic->timer_vecs[7]) {
1020 WARN_ON(mpic->flags & MPIC_SECONDARY);
1021
1022 DBG("mpic: mapping as timer\n");
1023 irq_set_chip_data(virq, mpic);
1024 irq_set_chip_and_handler(virq, &mpic->hc_tm,
1025 handle_fasteoi_irq);
1026 return 0;
1027 }
1028
1029 if (mpic_map_error_int(mpic, virq, hw))
1030 return 0;
1031
1032 if (hw >= mpic->num_sources)
1033 return -EINVAL;
1034
1035 mpic_msi_reserve_hwirq(mpic, hw);
1036
1037 /* Default chip */
1038 chip = &mpic->hc_irq;
1039
1040 #ifdef CONFIG_MPIC_U3_HT_IRQS
1041 /* Check for HT interrupts, override vecpri */
1042 if (mpic_is_ht_interrupt(mpic, hw))
1043 chip = &mpic->hc_ht_irq;
1044 #endif /* CONFIG_MPIC_U3_HT_IRQS */
1045
1046 DBG("mpic: mapping to irq chip @%p\n", chip);
1047
1048 irq_set_chip_data(virq, mpic);
1049 irq_set_chip_and_handler(virq, chip, handle_fasteoi_irq);
1050
1051 /* Set default irq type */
1052 irq_set_irq_type(virq, IRQ_TYPE_DEFAULT);
1053
1054 /* If the MPIC was reset, then all vectors have already been
1055 * initialized. Otherwise, a per source lazy initialization
1056 * is done here.
1057 */
1058 if (!mpic_is_ipi(mpic, hw) && (mpic->flags & MPIC_NO_RESET)) {
1059 mpic_set_vector(virq, hw);
1060 mpic_set_destination(virq, mpic_processor_id(mpic));
1061 mpic_irq_set_priority(virq, 8);
1062 }
1063
1064 return 0;
1065 }
1066
1067 static int mpic_host_xlate(struct irq_domain *h, struct device_node *ct,
1068 const u32 *intspec, unsigned int intsize,
1069 irq_hw_number_t *out_hwirq, unsigned int *out_flags)
1070
1071 {
1072 struct mpic *mpic = h->host_data;
1073 static unsigned char map_mpic_senses[4] = {
1074 IRQ_TYPE_EDGE_RISING,
1075 IRQ_TYPE_LEVEL_LOW,
1076 IRQ_TYPE_LEVEL_HIGH,
1077 IRQ_TYPE_EDGE_FALLING,
1078 };
1079
1080 *out_hwirq = intspec[0];
1081 if (intsize >= 4 && (mpic->flags & MPIC_FSL)) {
1082 /*
1083 * Freescale MPIC with extended intspec:
1084 * First two cells are as usual. Third specifies
1085 * an "interrupt type". Fourth is type-specific data.
1086 *
1087 * See Documentation/devicetree/bindings/powerpc/fsl/mpic.txt
1088 */
1089 switch (intspec[2]) {
1090 case 0:
1091 break;
1092 case 1:
1093 if (!(mpic->flags & MPIC_FSL_HAS_EIMR))
1094 break;
1095
1096 if (intspec[3] >= ARRAY_SIZE(mpic->err_int_vecs))
1097 return -EINVAL;
1098
1099 *out_hwirq = mpic->err_int_vecs[intspec[3]];
1100
1101 break;
1102 case 2:
1103 if (intspec[0] >= ARRAY_SIZE(mpic->ipi_vecs))
1104 return -EINVAL;
1105
1106 *out_hwirq = mpic->ipi_vecs[intspec[0]];
1107 break;
1108 case 3:
1109 if (intspec[0] >= ARRAY_SIZE(mpic->timer_vecs))
1110 return -EINVAL;
1111
1112 *out_hwirq = mpic->timer_vecs[intspec[0]];
1113 break;
1114 default:
1115 pr_debug("%s: unknown irq type %u\n",
1116 __func__, intspec[2]);
1117 return -EINVAL;
1118 }
1119
1120 *out_flags = map_mpic_senses[intspec[1] & 3];
1121 } else if (intsize > 1) {
1122 u32 mask = 0x3;
1123
1124 /* Apple invented a new race of encoding on machines with
1125 * an HT APIC. They encode, among others, the index within
1126 * the HT APIC. We don't care about it here since thankfully,
1127 * it appears that they have the APIC already properly
1128 * configured, and thus our current fixup code that reads the
1129 * APIC config works fine. However, we still need to mask out
1130 * bits in the specifier to make sure we only get bit 0 which
1131 * is the level/edge bit (the only sense bit exposed by Apple),
1132 * as their bit 1 means something else.
1133 */
1134 if (machine_is(powermac))
1135 mask = 0x1;
1136 *out_flags = map_mpic_senses[intspec[1] & mask];
1137 } else
1138 *out_flags = IRQ_TYPE_NONE;
1139
1140 DBG("mpic: xlate (%d cells: 0x%08x 0x%08x) to line 0x%lx sense 0x%x\n",
1141 intsize, intspec[0], intspec[1], *out_hwirq, *out_flags);
1142
1143 return 0;
1144 }
1145
1146 /* IRQ handler for a secondary MPIC cascaded from another IRQ controller */
1147 static void mpic_cascade(unsigned int irq, struct irq_desc *desc)
1148 {
1149 struct irq_chip *chip = irq_desc_get_chip(desc);
1150 struct mpic *mpic = irq_desc_get_handler_data(desc);
1151 unsigned int virq;
1152
1153 BUG_ON(!(mpic->flags & MPIC_SECONDARY));
1154
1155 virq = mpic_get_one_irq(mpic);
1156 if (virq)
1157 generic_handle_irq(virq);
1158
1159 chip->irq_eoi(&desc->irq_data);
1160 }
1161
1162 static struct irq_domain_ops mpic_host_ops = {
1163 .match = mpic_host_match,
1164 .map = mpic_host_map,
1165 .xlate = mpic_host_xlate,
1166 };
1167
1168 /*
1169 * Exported functions
1170 */
1171
1172 struct mpic * __init mpic_alloc(struct device_node *node,
1173 phys_addr_t phys_addr,
1174 unsigned int flags,
1175 unsigned int isu_size,
1176 unsigned int irq_count,
1177 const char *name)
1178 {
1179 int i, psize, intvec_top;
1180 struct mpic *mpic;
1181 u32 greg_feature;
1182 const char *vers;
1183 const u32 *psrc;
1184 u32 last_irq;
1185 u32 fsl_version = 0;
1186
1187 /* Default MPIC search parameters */
1188 static const struct of_device_id __initconst mpic_device_id[] = {
1189 { .type = "open-pic", },
1190 { .compatible = "open-pic", },
1191 {},
1192 };
1193
1194 /*
1195 * If we were not passed a device-tree node, then perform the default
1196 * search for standardized a standardized OpenPIC.
1197 */
1198 if (node) {
1199 node = of_node_get(node);
1200 } else {
1201 node = of_find_matching_node(NULL, mpic_device_id);
1202 if (!node)
1203 return NULL;
1204 }
1205
1206 /* Pick the physical address from the device tree if unspecified */
1207 if (!phys_addr) {
1208 /* Check if it is DCR-based */
1209 if (of_get_property(node, "dcr-reg", NULL)) {
1210 flags |= MPIC_USES_DCR;
1211 } else {
1212 struct resource r;
1213 if (of_address_to_resource(node, 0, &r))
1214 goto err_of_node_put;
1215 phys_addr = r.start;
1216 }
1217 }
1218
1219 /* Read extra device-tree properties into the flags variable */
1220 if (of_get_property(node, "big-endian", NULL))
1221 flags |= MPIC_BIG_ENDIAN;
1222 if (of_get_property(node, "pic-no-reset", NULL))
1223 flags |= MPIC_NO_RESET;
1224 if (of_get_property(node, "single-cpu-affinity", NULL))
1225 flags |= MPIC_SINGLE_DEST_CPU;
1226 if (of_device_is_compatible(node, "fsl,mpic"))
1227 flags |= MPIC_FSL | MPIC_LARGE_VECTORS;
1228
1229 mpic = kzalloc(sizeof(struct mpic), GFP_KERNEL);
1230 if (mpic == NULL)
1231 goto err_of_node_put;
1232
1233 mpic->name = name;
1234 mpic->node = node;
1235 mpic->paddr = phys_addr;
1236 mpic->flags = flags;
1237
1238 mpic->hc_irq = mpic_irq_chip;
1239 mpic->hc_irq.name = name;
1240 if (!(mpic->flags & MPIC_SECONDARY))
1241 mpic->hc_irq.irq_set_affinity = mpic_set_affinity;
1242 #ifdef CONFIG_MPIC_U3_HT_IRQS
1243 mpic->hc_ht_irq = mpic_irq_ht_chip;
1244 mpic->hc_ht_irq.name = name;
1245 if (!(mpic->flags & MPIC_SECONDARY))
1246 mpic->hc_ht_irq.irq_set_affinity = mpic_set_affinity;
1247 #endif /* CONFIG_MPIC_U3_HT_IRQS */
1248
1249 #ifdef CONFIG_SMP
1250 mpic->hc_ipi = mpic_ipi_chip;
1251 mpic->hc_ipi.name = name;
1252 #endif /* CONFIG_SMP */
1253
1254 mpic->hc_tm = mpic_tm_chip;
1255 mpic->hc_tm.name = name;
1256
1257 mpic->num_sources = 0; /* so far */
1258
1259 if (mpic->flags & MPIC_LARGE_VECTORS)
1260 intvec_top = 2047;
1261 else
1262 intvec_top = 255;
1263
1264 mpic->timer_vecs[0] = intvec_top - 12;
1265 mpic->timer_vecs[1] = intvec_top - 11;
1266 mpic->timer_vecs[2] = intvec_top - 10;
1267 mpic->timer_vecs[3] = intvec_top - 9;
1268 mpic->timer_vecs[4] = intvec_top - 8;
1269 mpic->timer_vecs[5] = intvec_top - 7;
1270 mpic->timer_vecs[6] = intvec_top - 6;
1271 mpic->timer_vecs[7] = intvec_top - 5;
1272 mpic->ipi_vecs[0] = intvec_top - 4;
1273 mpic->ipi_vecs[1] = intvec_top - 3;
1274 mpic->ipi_vecs[2] = intvec_top - 2;
1275 mpic->ipi_vecs[3] = intvec_top - 1;
1276 mpic->spurious_vec = intvec_top;
1277
1278 /* Look for protected sources */
1279 psrc = of_get_property(mpic->node, "protected-sources", &psize);
1280 if (psrc) {
1281 /* Allocate a bitmap with one bit per interrupt */
1282 unsigned int mapsize = BITS_TO_LONGS(intvec_top + 1);
1283 mpic->protected = kzalloc(mapsize*sizeof(long), GFP_KERNEL);
1284 BUG_ON(mpic->protected == NULL);
1285 for (i = 0; i < psize/sizeof(u32); i++) {
1286 if (psrc[i] > intvec_top)
1287 continue;
1288 __set_bit(psrc[i], mpic->protected);
1289 }
1290 }
1291
1292 #ifdef CONFIG_MPIC_WEIRD
1293 mpic->hw_set = mpic_infos[MPIC_GET_REGSET(mpic->flags)];
1294 #endif
1295
1296 /* default register type */
1297 if (mpic->flags & MPIC_BIG_ENDIAN)
1298 mpic->reg_type = mpic_access_mmio_be;
1299 else
1300 mpic->reg_type = mpic_access_mmio_le;
1301
1302 /*
1303 * An MPIC with a "dcr-reg" property must be accessed that way, but
1304 * only if the kernel includes DCR support.
1305 */
1306 #ifdef CONFIG_PPC_DCR
1307 if (mpic->flags & MPIC_USES_DCR)
1308 mpic->reg_type = mpic_access_dcr;
1309 #else
1310 BUG_ON(mpic->flags & MPIC_USES_DCR);
1311 #endif
1312
1313 /* Map the global registers */
1314 mpic_map(mpic, mpic->paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000);
1315 mpic_map(mpic, mpic->paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000);
1316
1317 if (mpic->flags & MPIC_FSL) {
1318 u32 brr1;
1319 int ret;
1320
1321 /*
1322 * Yes, Freescale really did put global registers in the
1323 * magic per-cpu area -- and they don't even show up in the
1324 * non-magic per-cpu copies that this driver normally uses.
1325 */
1326 mpic_map(mpic, mpic->paddr, &mpic->thiscpuregs,
1327 MPIC_CPU_THISBASE, 0x1000);
1328
1329 brr1 = _mpic_read(mpic->reg_type, &mpic->thiscpuregs,
1330 MPIC_FSL_BRR1);
1331 fsl_version = brr1 & MPIC_FSL_BRR1_VER;
1332
1333 /* Error interrupt mask register (EIMR) is required for
1334 * handling individual device error interrupts. EIMR
1335 * was added in MPIC version 4.1.
1336 *
1337 * Over here we reserve vector number space for error
1338 * interrupt vectors. This space is stolen from the
1339 * global vector number space, as in case of ipis
1340 * and timer interrupts.
1341 *
1342 * Available vector space = intvec_top - 12, where 12
1343 * is the number of vectors which have been consumed by
1344 * ipis and timer interrupts.
1345 */
1346 if (fsl_version >= 0x401) {
1347 ret = mpic_setup_error_int(mpic, intvec_top - 12);
1348 if (ret)
1349 return NULL;
1350 }
1351
1352 }
1353
1354 /*
1355 * EPR is only available starting with v4.0. To support
1356 * platforms that don't know the MPIC version at compile-time,
1357 * such as qemu-e500, turn off coreint if this MPIC doesn't
1358 * support it. Note that we never enable it if it wasn't
1359 * requested in the first place.
1360 *
1361 * This is done outside the MPIC_FSL check, so that we
1362 * also disable coreint if the MPIC node doesn't have
1363 * an "fsl,mpic" compatible at all. This will be the case
1364 * with device trees generated by older versions of QEMU.
1365 * fsl_version will be zero if MPIC_FSL is not set.
1366 */
1367 if (fsl_version < 0x400 && (flags & MPIC_ENABLE_COREINT)) {
1368 WARN_ON(ppc_md.get_irq != mpic_get_coreint_irq);
1369 ppc_md.get_irq = mpic_get_irq;
1370 }
1371
1372 /* Reset */
1373
1374 /* When using a device-node, reset requests are only honored if the MPIC
1375 * is allowed to reset.
1376 */
1377 if (!(mpic->flags & MPIC_NO_RESET)) {
1378 printk(KERN_DEBUG "mpic: Resetting\n");
1379 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1380 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1381 | MPIC_GREG_GCONF_RESET);
1382 while( mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1383 & MPIC_GREG_GCONF_RESET)
1384 mb();
1385 }
1386
1387 /* CoreInt */
1388 if (mpic->flags & MPIC_ENABLE_COREINT)
1389 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1390 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1391 | MPIC_GREG_GCONF_COREINT);
1392
1393 if (mpic->flags & MPIC_ENABLE_MCK)
1394 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1395 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1396 | MPIC_GREG_GCONF_MCK);
1397
1398 /*
1399 * The MPIC driver will crash if there are more cores than we
1400 * can initialize, so we may as well catch that problem here.
1401 */
1402 BUG_ON(num_possible_cpus() > MPIC_MAX_CPUS);
1403
1404 /* Map the per-CPU registers */
1405 for_each_possible_cpu(i) {
1406 unsigned int cpu = get_hard_smp_processor_id(i);
1407
1408 mpic_map(mpic, mpic->paddr, &mpic->cpuregs[cpu],
1409 MPIC_INFO(CPU_BASE) + cpu * MPIC_INFO(CPU_STRIDE),
1410 0x1000);
1411 }
1412
1413 /*
1414 * Read feature register. For non-ISU MPICs, num sources as well. On
1415 * ISU MPICs, sources are counted as ISUs are added
1416 */
1417 greg_feature = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0));
1418
1419 /*
1420 * By default, the last source number comes from the MPIC, but the
1421 * device-tree and board support code can override it on buggy hw.
1422 * If we get passed an isu_size (multi-isu MPIC) then we use that
1423 * as a default instead of the value read from the HW.
1424 */
1425 last_irq = (greg_feature & MPIC_GREG_FEATURE_LAST_SRC_MASK)
1426 >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT;
1427 if (isu_size)
1428 last_irq = isu_size * MPIC_MAX_ISU - 1;
1429 of_property_read_u32(mpic->node, "last-interrupt-source", &last_irq);
1430 if (irq_count)
1431 last_irq = irq_count - 1;
1432
1433 /* Initialize main ISU if none provided */
1434 if (!isu_size) {
1435 isu_size = last_irq + 1;
1436 mpic->num_sources = isu_size;
1437 mpic_map(mpic, mpic->paddr, &mpic->isus[0],
1438 MPIC_INFO(IRQ_BASE),
1439 MPIC_INFO(IRQ_STRIDE) * isu_size);
1440 }
1441
1442 mpic->isu_size = isu_size;
1443 mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1);
1444 mpic->isu_mask = (1 << mpic->isu_shift) - 1;
1445
1446 mpic->irqhost = irq_domain_add_linear(mpic->node,
1447 intvec_top,
1448 &mpic_host_ops, mpic);
1449
1450 /*
1451 * FIXME: The code leaks the MPIC object and mappings here; this
1452 * is very unlikely to fail but it ought to be fixed anyways.
1453 */
1454 if (mpic->irqhost == NULL)
1455 return NULL;
1456
1457 /* Display version */
1458 switch (greg_feature & MPIC_GREG_FEATURE_VERSION_MASK) {
1459 case 1:
1460 vers = "1.0";
1461 break;
1462 case 2:
1463 vers = "1.2";
1464 break;
1465 case 3:
1466 vers = "1.3";
1467 break;
1468 default:
1469 vers = "<unknown>";
1470 break;
1471 }
1472 printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %llx,"
1473 " max %d CPUs\n",
1474 name, vers, (unsigned long long)mpic->paddr, num_possible_cpus());
1475 printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n",
1476 mpic->isu_size, mpic->isu_shift, mpic->isu_mask);
1477
1478 mpic->next = mpics;
1479 mpics = mpic;
1480
1481 if (!(mpic->flags & MPIC_SECONDARY)) {
1482 mpic_primary = mpic;
1483 irq_set_default_host(mpic->irqhost);
1484 }
1485
1486 return mpic;
1487
1488 err_of_node_put:
1489 of_node_put(node);
1490 return NULL;
1491 }
1492
1493 void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
1494 phys_addr_t paddr)
1495 {
1496 unsigned int isu_first = isu_num * mpic->isu_size;
1497
1498 BUG_ON(isu_num >= MPIC_MAX_ISU);
1499
1500 mpic_map(mpic,
1501 paddr, &mpic->isus[isu_num], 0,
1502 MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
1503
1504 if ((isu_first + mpic->isu_size) > mpic->num_sources)
1505 mpic->num_sources = isu_first + mpic->isu_size;
1506 }
1507
1508 void __init mpic_init(struct mpic *mpic)
1509 {
1510 int i, cpu;
1511 int num_timers = 4;
1512
1513 BUG_ON(mpic->num_sources == 0);
1514
1515 printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources);
1516
1517 /* Set current processor priority to max */
1518 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
1519
1520 if (mpic->flags & MPIC_FSL) {
1521 u32 brr1 = _mpic_read(mpic->reg_type, &mpic->thiscpuregs,
1522 MPIC_FSL_BRR1);
1523 u32 version = brr1 & MPIC_FSL_BRR1_VER;
1524
1525 /*
1526 * Timer group B is present at the latest in MPIC 3.1 (e.g.
1527 * mpc8536). It is not present in MPIC 2.0 (e.g. mpc8544).
1528 * I don't know about the status of intermediate versions (or
1529 * whether they even exist).
1530 */
1531 if (version >= 0x0301)
1532 num_timers = 8;
1533 }
1534
1535 /* FSL mpic error interrupt intialization */
1536 if (mpic->flags & MPIC_FSL_HAS_EIMR)
1537 mpic_err_int_init(mpic, MPIC_FSL_ERR_INT);
1538
1539 /* Initialize timers to our reserved vectors and mask them for now */
1540 for (i = 0; i < num_timers; i++) {
1541 unsigned int offset = mpic_tm_offset(mpic, i);
1542
1543 mpic_write(mpic->tmregs,
1544 offset + MPIC_INFO(TIMER_DESTINATION),
1545 1 << hard_smp_processor_id());
1546 mpic_write(mpic->tmregs,
1547 offset + MPIC_INFO(TIMER_VECTOR_PRI),
1548 MPIC_VECPRI_MASK |
1549 (9 << MPIC_VECPRI_PRIORITY_SHIFT) |
1550 (mpic->timer_vecs[0] + i));
1551 }
1552
1553 /* Initialize IPIs to our reserved vectors and mark them disabled for now */
1554 mpic_test_broken_ipi(mpic);
1555 for (i = 0; i < 4; i++) {
1556 mpic_ipi_write(i,
1557 MPIC_VECPRI_MASK |
1558 (10 << MPIC_VECPRI_PRIORITY_SHIFT) |
1559 (mpic->ipi_vecs[0] + i));
1560 }
1561
1562 /* Do the HT PIC fixups on U3 broken mpic */
1563 DBG("MPIC flags: %x\n", mpic->flags);
1564 if ((mpic->flags & MPIC_U3_HT_IRQS) && !(mpic->flags & MPIC_SECONDARY)) {
1565 mpic_scan_ht_pics(mpic);
1566 mpic_u3msi_init(mpic);
1567 }
1568
1569 mpic_pasemi_msi_init(mpic);
1570
1571 cpu = mpic_processor_id(mpic);
1572
1573 if (!(mpic->flags & MPIC_NO_RESET)) {
1574 for (i = 0; i < mpic->num_sources; i++) {
1575 /* start with vector = source number, and masked */
1576 u32 vecpri = MPIC_VECPRI_MASK | i |
1577 (8 << MPIC_VECPRI_PRIORITY_SHIFT);
1578
1579 /* check if protected */
1580 if (mpic->protected && test_bit(i, mpic->protected))
1581 continue;
1582 /* init hw */
1583 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
1584 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1 << cpu);
1585 }
1586 }
1587
1588 /* Init spurious vector */
1589 mpic_write(mpic->gregs, MPIC_INFO(GREG_SPURIOUS), mpic->spurious_vec);
1590
1591 /* Disable 8259 passthrough, if supported */
1592 if (!(mpic->flags & MPIC_NO_PTHROU_DIS))
1593 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1594 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1595 | MPIC_GREG_GCONF_8259_PTHROU_DIS);
1596
1597 if (mpic->flags & MPIC_NO_BIAS)
1598 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1599 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1600 | MPIC_GREG_GCONF_NO_BIAS);
1601
1602 /* Set current processor priority to 0 */
1603 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
1604
1605 #ifdef CONFIG_PM
1606 /* allocate memory to save mpic state */
1607 mpic->save_data = kmalloc(mpic->num_sources * sizeof(*mpic->save_data),
1608 GFP_KERNEL);
1609 BUG_ON(mpic->save_data == NULL);
1610 #endif
1611
1612 /* Check if this MPIC is chained from a parent interrupt controller */
1613 if (mpic->flags & MPIC_SECONDARY) {
1614 int virq = irq_of_parse_and_map(mpic->node, 0);
1615 if (virq != NO_IRQ) {
1616 printk(KERN_INFO "%s: hooking up to IRQ %d\n",
1617 mpic->node->full_name, virq);
1618 irq_set_handler_data(virq, mpic);
1619 irq_set_chained_handler(virq, &mpic_cascade);
1620 }
1621 }
1622 }
1623
1624 void __init mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio)
1625 {
1626 u32 v;
1627
1628 v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);
1629 v &= ~MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK;
1630 v |= MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(clock_ratio);
1631 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);
1632 }
1633
1634 void __init mpic_set_serial_int(struct mpic *mpic, int enable)
1635 {
1636 unsigned long flags;
1637 u32 v;
1638
1639 raw_spin_lock_irqsave(&mpic_lock, flags);
1640 v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);
1641 if (enable)
1642 v |= MPIC_GREG_GLOBAL_CONF_1_SIE;
1643 else
1644 v &= ~MPIC_GREG_GLOBAL_CONF_1_SIE;
1645 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);
1646 raw_spin_unlock_irqrestore(&mpic_lock, flags);
1647 }
1648
1649 void mpic_irq_set_priority(unsigned int irq, unsigned int pri)
1650 {
1651 struct mpic *mpic = mpic_find(irq);
1652 unsigned int src = virq_to_hw(irq);
1653 unsigned long flags;
1654 u32 reg;
1655
1656 if (!mpic)
1657 return;
1658
1659 raw_spin_lock_irqsave(&mpic_lock, flags);
1660 if (mpic_is_ipi(mpic, src)) {
1661 reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) &
1662 ~MPIC_VECPRI_PRIORITY_MASK;
1663 mpic_ipi_write(src - mpic->ipi_vecs[0],
1664 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1665 } else if (mpic_is_tm(mpic, src)) {
1666 reg = mpic_tm_read(src - mpic->timer_vecs[0]) &
1667 ~MPIC_VECPRI_PRIORITY_MASK;
1668 mpic_tm_write(src - mpic->timer_vecs[0],
1669 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1670 } else {
1671 reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI))
1672 & ~MPIC_VECPRI_PRIORITY_MASK;
1673 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
1674 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1675 }
1676 raw_spin_unlock_irqrestore(&mpic_lock, flags);
1677 }
1678
1679 void mpic_setup_this_cpu(void)
1680 {
1681 #ifdef CONFIG_SMP
1682 struct mpic *mpic = mpic_primary;
1683 unsigned long flags;
1684 u32 msk = 1 << hard_smp_processor_id();
1685 unsigned int i;
1686
1687 BUG_ON(mpic == NULL);
1688
1689 DBG("%s: setup_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
1690
1691 raw_spin_lock_irqsave(&mpic_lock, flags);
1692
1693 /* let the mpic know we want intrs. default affinity is 0xffffffff
1694 * until changed via /proc. That's how it's done on x86. If we want
1695 * it differently, then we should make sure we also change the default
1696 * values of irq_desc[].affinity in irq.c.
1697 */
1698 if (distribute_irqs) {
1699 for (i = 0; i < mpic->num_sources ; i++)
1700 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1701 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) | msk);
1702 }
1703
1704 /* Set current processor priority to 0 */
1705 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
1706
1707 raw_spin_unlock_irqrestore(&mpic_lock, flags);
1708 #endif /* CONFIG_SMP */
1709 }
1710
1711 int mpic_cpu_get_priority(void)
1712 {
1713 struct mpic *mpic = mpic_primary;
1714
1715 return mpic_cpu_read(MPIC_INFO(CPU_CURRENT_TASK_PRI));
1716 }
1717
1718 void mpic_cpu_set_priority(int prio)
1719 {
1720 struct mpic *mpic = mpic_primary;
1721
1722 prio &= MPIC_CPU_TASKPRI_MASK;
1723 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), prio);
1724 }
1725
1726 void mpic_teardown_this_cpu(int secondary)
1727 {
1728 struct mpic *mpic = mpic_primary;
1729 unsigned long flags;
1730 u32 msk = 1 << hard_smp_processor_id();
1731 unsigned int i;
1732
1733 BUG_ON(mpic == NULL);
1734
1735 DBG("%s: teardown_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
1736 raw_spin_lock_irqsave(&mpic_lock, flags);
1737
1738 /* let the mpic know we don't want intrs. */
1739 for (i = 0; i < mpic->num_sources ; i++)
1740 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1741 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) & ~msk);
1742
1743 /* Set current processor priority to max */
1744 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
1745 /* We need to EOI the IPI since not all platforms reset the MPIC
1746 * on boot and new interrupts wouldn't get delivered otherwise.
1747 */
1748 mpic_eoi(mpic);
1749
1750 raw_spin_unlock_irqrestore(&mpic_lock, flags);
1751 }
1752
1753
1754 static unsigned int _mpic_get_one_irq(struct mpic *mpic, int reg)
1755 {
1756 u32 src;
1757
1758 src = mpic_cpu_read(reg) & MPIC_INFO(VECPRI_VECTOR_MASK);
1759 #ifdef DEBUG_LOW
1760 DBG("%s: get_one_irq(reg 0x%x): %d\n", mpic->name, reg, src);
1761 #endif
1762 if (unlikely(src == mpic->spurious_vec)) {
1763 if (mpic->flags & MPIC_SPV_EOI)
1764 mpic_eoi(mpic);
1765 return NO_IRQ;
1766 }
1767 if (unlikely(mpic->protected && test_bit(src, mpic->protected))) {
1768 printk_ratelimited(KERN_WARNING "%s: Got protected source %d !\n",
1769 mpic->name, (int)src);
1770 mpic_eoi(mpic);
1771 return NO_IRQ;
1772 }
1773
1774 return irq_linear_revmap(mpic->irqhost, src);
1775 }
1776
1777 unsigned int mpic_get_one_irq(struct mpic *mpic)
1778 {
1779 return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_INTACK));
1780 }
1781
1782 unsigned int mpic_get_irq(void)
1783 {
1784 struct mpic *mpic = mpic_primary;
1785
1786 BUG_ON(mpic == NULL);
1787
1788 return mpic_get_one_irq(mpic);
1789 }
1790
1791 unsigned int mpic_get_coreint_irq(void)
1792 {
1793 #ifdef CONFIG_BOOKE
1794 struct mpic *mpic = mpic_primary;
1795 u32 src;
1796
1797 BUG_ON(mpic == NULL);
1798
1799 src = mfspr(SPRN_EPR);
1800
1801 if (unlikely(src == mpic->spurious_vec)) {
1802 if (mpic->flags & MPIC_SPV_EOI)
1803 mpic_eoi(mpic);
1804 return NO_IRQ;
1805 }
1806 if (unlikely(mpic->protected && test_bit(src, mpic->protected))) {
1807 printk_ratelimited(KERN_WARNING "%s: Got protected source %d !\n",
1808 mpic->name, (int)src);
1809 return NO_IRQ;
1810 }
1811
1812 return irq_linear_revmap(mpic->irqhost, src);
1813 #else
1814 return NO_IRQ;
1815 #endif
1816 }
1817
1818 unsigned int mpic_get_mcirq(void)
1819 {
1820 struct mpic *mpic = mpic_primary;
1821
1822 BUG_ON(mpic == NULL);
1823
1824 return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_MCACK));
1825 }
1826
1827 #ifdef CONFIG_SMP
1828 void mpic_request_ipis(void)
1829 {
1830 struct mpic *mpic = mpic_primary;
1831 int i;
1832 BUG_ON(mpic == NULL);
1833
1834 printk(KERN_INFO "mpic: requesting IPIs...\n");
1835
1836 for (i = 0; i < 4; i++) {
1837 unsigned int vipi = irq_create_mapping(mpic->irqhost,
1838 mpic->ipi_vecs[0] + i);
1839 if (vipi == NO_IRQ) {
1840 printk(KERN_ERR "Failed to map %s\n", smp_ipi_name[i]);
1841 continue;
1842 }
1843 smp_request_message_ipi(vipi, i);
1844 }
1845 }
1846
1847 void smp_mpic_message_pass(int cpu, int msg)
1848 {
1849 struct mpic *mpic = mpic_primary;
1850 u32 physmask;
1851
1852 BUG_ON(mpic == NULL);
1853
1854 /* make sure we're sending something that translates to an IPI */
1855 if ((unsigned int)msg > 3) {
1856 printk("SMP %d: smp_message_pass: unknown msg %d\n",
1857 smp_processor_id(), msg);
1858 return;
1859 }
1860
1861 #ifdef DEBUG_IPI
1862 DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, msg);
1863 #endif
1864
1865 physmask = 1 << get_hard_smp_processor_id(cpu);
1866
1867 mpic_cpu_write(MPIC_INFO(CPU_IPI_DISPATCH_0) +
1868 msg * MPIC_INFO(CPU_IPI_DISPATCH_STRIDE), physmask);
1869 }
1870
1871 int __init smp_mpic_probe(void)
1872 {
1873 int nr_cpus;
1874
1875 DBG("smp_mpic_probe()...\n");
1876
1877 nr_cpus = cpumask_weight(cpu_possible_mask);
1878
1879 DBG("nr_cpus: %d\n", nr_cpus);
1880
1881 if (nr_cpus > 1)
1882 mpic_request_ipis();
1883
1884 return nr_cpus;
1885 }
1886
1887 void smp_mpic_setup_cpu(int cpu)
1888 {
1889 mpic_setup_this_cpu();
1890 }
1891
1892 void mpic_reset_core(int cpu)
1893 {
1894 struct mpic *mpic = mpic_primary;
1895 u32 pir;
1896 int cpuid = get_hard_smp_processor_id(cpu);
1897 int i;
1898
1899 /* Set target bit for core reset */
1900 pir = mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
1901 pir |= (1 << cpuid);
1902 mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir);
1903 mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
1904
1905 /* Restore target bit after reset complete */
1906 pir &= ~(1 << cpuid);
1907 mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir);
1908 mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
1909
1910 /* Perform 15 EOI on each reset core to clear pending interrupts.
1911 * This is required for FSL CoreNet based devices */
1912 if (mpic->flags & MPIC_FSL) {
1913 for (i = 0; i < 15; i++) {
1914 _mpic_write(mpic->reg_type, &mpic->cpuregs[cpuid],
1915 MPIC_CPU_EOI, 0);
1916 }
1917 }
1918 }
1919 #endif /* CONFIG_SMP */
1920
1921 #ifdef CONFIG_PM
1922 static void mpic_suspend_one(struct mpic *mpic)
1923 {
1924 int i;
1925
1926 for (i = 0; i < mpic->num_sources; i++) {
1927 mpic->save_data[i].vecprio =
1928 mpic_irq_read(i, MPIC_INFO(IRQ_VECTOR_PRI));
1929 mpic->save_data[i].dest =
1930 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION));
1931 }
1932 }
1933
1934 static int mpic_suspend(void)
1935 {
1936 struct mpic *mpic = mpics;
1937
1938 while (mpic) {
1939 mpic_suspend_one(mpic);
1940 mpic = mpic->next;
1941 }
1942
1943 return 0;
1944 }
1945
1946 static void mpic_resume_one(struct mpic *mpic)
1947 {
1948 int i;
1949
1950 for (i = 0; i < mpic->num_sources; i++) {
1951 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI),
1952 mpic->save_data[i].vecprio);
1953 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1954 mpic->save_data[i].dest);
1955
1956 #ifdef CONFIG_MPIC_U3_HT_IRQS
1957 if (mpic->fixups) {
1958 struct mpic_irq_fixup *fixup = &mpic->fixups[i];
1959
1960 if (fixup->base) {
1961 /* we use the lowest bit in an inverted meaning */
1962 if ((mpic->save_data[i].fixup_data & 1) == 0)
1963 continue;
1964
1965 /* Enable and configure */
1966 writeb(0x10 + 2 * fixup->index, fixup->base + 2);
1967
1968 writel(mpic->save_data[i].fixup_data & ~1,
1969 fixup->base + 4);
1970 }
1971 }
1972 #endif
1973 } /* end for loop */
1974 }
1975
1976 static void mpic_resume(void)
1977 {
1978 struct mpic *mpic = mpics;
1979
1980 while (mpic) {
1981 mpic_resume_one(mpic);
1982 mpic = mpic->next;
1983 }
1984 }
1985
1986 static struct syscore_ops mpic_syscore_ops = {
1987 .resume = mpic_resume,
1988 .suspend = mpic_suspend,
1989 };
1990
1991 static int mpic_init_sys(void)
1992 {
1993 register_syscore_ops(&mpic_syscore_ops);
1994 return 0;
1995 }
1996
1997 device_initcall(mpic_init_sys);
1998 #endif
Linux kernel - Deliverables
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