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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wirel...
[deliverable/linux.git] / arch / powerpc / sysdev / mpic.c
1 /*
2 * arch/powerpc/kernel/mpic.c
3 *
4 * Driver for interrupt controllers following the OpenPIC standard, the
5 * common implementation beeing IBM's MPIC. This driver also can deal
6 * with various broken implementations of this HW.
7 *
8 * Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp.
9 *
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file COPYING in the main directory of this archive
12 * for more details.
13 */
14
15 #undef DEBUG
16 #undef DEBUG_IPI
17 #undef DEBUG_IRQ
18 #undef DEBUG_LOW
19
20 #include <linux/types.h>
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/irq.h>
24 #include <linux/smp.h>
25 #include <linux/interrupt.h>
26 #include <linux/bootmem.h>
27 #include <linux/spinlock.h>
28 #include <linux/pci.h>
29 #include <linux/slab.h>
30
31 #include <asm/ptrace.h>
32 #include <asm/signal.h>
33 #include <asm/io.h>
34 #include <asm/pgtable.h>
35 #include <asm/irq.h>
36 #include <asm/machdep.h>
37 #include <asm/mpic.h>
38 #include <asm/smp.h>
39
40 #include "mpic.h"
41
42 #ifdef DEBUG
43 #define DBG(fmt...) printk(fmt)
44 #else
45 #define DBG(fmt...)
46 #endif
47
48 static struct mpic *mpics;
49 static struct mpic *mpic_primary;
50 static DEFINE_RAW_SPINLOCK(mpic_lock);
51
52 #ifdef CONFIG_PPC32 /* XXX for now */
53 #ifdef CONFIG_IRQ_ALL_CPUS
54 #define distribute_irqs (1)
55 #else
56 #define distribute_irqs (0)
57 #endif
58 #endif
59
60 #ifdef CONFIG_MPIC_WEIRD
61 static u32 mpic_infos[][MPIC_IDX_END] = {
62 [0] = { /* Original OpenPIC compatible MPIC */
63 MPIC_GREG_BASE,
64 MPIC_GREG_FEATURE_0,
65 MPIC_GREG_GLOBAL_CONF_0,
66 MPIC_GREG_VENDOR_ID,
67 MPIC_GREG_IPI_VECTOR_PRI_0,
68 MPIC_GREG_IPI_STRIDE,
69 MPIC_GREG_SPURIOUS,
70 MPIC_GREG_TIMER_FREQ,
71
72 MPIC_TIMER_BASE,
73 MPIC_TIMER_STRIDE,
74 MPIC_TIMER_CURRENT_CNT,
75 MPIC_TIMER_BASE_CNT,
76 MPIC_TIMER_VECTOR_PRI,
77 MPIC_TIMER_DESTINATION,
78
79 MPIC_CPU_BASE,
80 MPIC_CPU_STRIDE,
81 MPIC_CPU_IPI_DISPATCH_0,
82 MPIC_CPU_IPI_DISPATCH_STRIDE,
83 MPIC_CPU_CURRENT_TASK_PRI,
84 MPIC_CPU_WHOAMI,
85 MPIC_CPU_INTACK,
86 MPIC_CPU_EOI,
87 MPIC_CPU_MCACK,
88
89 MPIC_IRQ_BASE,
90 MPIC_IRQ_STRIDE,
91 MPIC_IRQ_VECTOR_PRI,
92 MPIC_VECPRI_VECTOR_MASK,
93 MPIC_VECPRI_POLARITY_POSITIVE,
94 MPIC_VECPRI_POLARITY_NEGATIVE,
95 MPIC_VECPRI_SENSE_LEVEL,
96 MPIC_VECPRI_SENSE_EDGE,
97 MPIC_VECPRI_POLARITY_MASK,
98 MPIC_VECPRI_SENSE_MASK,
99 MPIC_IRQ_DESTINATION
100 },
101 [1] = { /* Tsi108/109 PIC */
102 TSI108_GREG_BASE,
103 TSI108_GREG_FEATURE_0,
104 TSI108_GREG_GLOBAL_CONF_0,
105 TSI108_GREG_VENDOR_ID,
106 TSI108_GREG_IPI_VECTOR_PRI_0,
107 TSI108_GREG_IPI_STRIDE,
108 TSI108_GREG_SPURIOUS,
109 TSI108_GREG_TIMER_FREQ,
110
111 TSI108_TIMER_BASE,
112 TSI108_TIMER_STRIDE,
113 TSI108_TIMER_CURRENT_CNT,
114 TSI108_TIMER_BASE_CNT,
115 TSI108_TIMER_VECTOR_PRI,
116 TSI108_TIMER_DESTINATION,
117
118 TSI108_CPU_BASE,
119 TSI108_CPU_STRIDE,
120 TSI108_CPU_IPI_DISPATCH_0,
121 TSI108_CPU_IPI_DISPATCH_STRIDE,
122 TSI108_CPU_CURRENT_TASK_PRI,
123 TSI108_CPU_WHOAMI,
124 TSI108_CPU_INTACK,
125 TSI108_CPU_EOI,
126 TSI108_CPU_MCACK,
127
128 TSI108_IRQ_BASE,
129 TSI108_IRQ_STRIDE,
130 TSI108_IRQ_VECTOR_PRI,
131 TSI108_VECPRI_VECTOR_MASK,
132 TSI108_VECPRI_POLARITY_POSITIVE,
133 TSI108_VECPRI_POLARITY_NEGATIVE,
134 TSI108_VECPRI_SENSE_LEVEL,
135 TSI108_VECPRI_SENSE_EDGE,
136 TSI108_VECPRI_POLARITY_MASK,
137 TSI108_VECPRI_SENSE_MASK,
138 TSI108_IRQ_DESTINATION
139 },
140 };
141
142 #define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name]
143
144 #else /* CONFIG_MPIC_WEIRD */
145
146 #define MPIC_INFO(name) MPIC_##name
147
148 #endif /* CONFIG_MPIC_WEIRD */
149
150 /*
151 * Register accessor functions
152 */
153
154
155 static inline u32 _mpic_read(enum mpic_reg_type type,
156 struct mpic_reg_bank *rb,
157 unsigned int reg)
158 {
159 switch(type) {
160 #ifdef CONFIG_PPC_DCR
161 case mpic_access_dcr:
162 return dcr_read(rb->dhost, reg);
163 #endif
164 case mpic_access_mmio_be:
165 return in_be32(rb->base + (reg >> 2));
166 case mpic_access_mmio_le:
167 default:
168 return in_le32(rb->base + (reg >> 2));
169 }
170 }
171
172 static inline void _mpic_write(enum mpic_reg_type type,
173 struct mpic_reg_bank *rb,
174 unsigned int reg, u32 value)
175 {
176 switch(type) {
177 #ifdef CONFIG_PPC_DCR
178 case mpic_access_dcr:
179 dcr_write(rb->dhost, reg, value);
180 break;
181 #endif
182 case mpic_access_mmio_be:
183 out_be32(rb->base + (reg >> 2), value);
184 break;
185 case mpic_access_mmio_le:
186 default:
187 out_le32(rb->base + (reg >> 2), value);
188 break;
189 }
190 }
191
192 static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi)
193 {
194 enum mpic_reg_type type = mpic->reg_type;
195 unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
196 (ipi * MPIC_INFO(GREG_IPI_STRIDE));
197
198 if ((mpic->flags & MPIC_BROKEN_IPI) && type == mpic_access_mmio_le)
199 type = mpic_access_mmio_be;
200 return _mpic_read(type, &mpic->gregs, offset);
201 }
202
203 static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value)
204 {
205 unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
206 (ipi * MPIC_INFO(GREG_IPI_STRIDE));
207
208 _mpic_write(mpic->reg_type, &mpic->gregs, offset, value);
209 }
210
211 static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg)
212 {
213 unsigned int cpu = 0;
214
215 if (mpic->flags & MPIC_PRIMARY)
216 cpu = hard_smp_processor_id();
217 return _mpic_read(mpic->reg_type, &mpic->cpuregs[cpu], reg);
218 }
219
220 static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value)
221 {
222 unsigned int cpu = 0;
223
224 if (mpic->flags & MPIC_PRIMARY)
225 cpu = hard_smp_processor_id();
226
227 _mpic_write(mpic->reg_type, &mpic->cpuregs[cpu], reg, value);
228 }
229
230 static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigned int reg)
231 {
232 unsigned int isu = src_no >> mpic->isu_shift;
233 unsigned int idx = src_no & mpic->isu_mask;
234 unsigned int val;
235
236 val = _mpic_read(mpic->reg_type, &mpic->isus[isu],
237 reg + (idx * MPIC_INFO(IRQ_STRIDE)));
238 #ifdef CONFIG_MPIC_BROKEN_REGREAD
239 if (reg == 0)
240 val = (val & (MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY)) |
241 mpic->isu_reg0_shadow[src_no];
242 #endif
243 return val;
244 }
245
246 static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no,
247 unsigned int reg, u32 value)
248 {
249 unsigned int isu = src_no >> mpic->isu_shift;
250 unsigned int idx = src_no & mpic->isu_mask;
251
252 _mpic_write(mpic->reg_type, &mpic->isus[isu],
253 reg + (idx * MPIC_INFO(IRQ_STRIDE)), value);
254
255 #ifdef CONFIG_MPIC_BROKEN_REGREAD
256 if (reg == 0)
257 mpic->isu_reg0_shadow[src_no] =
258 value & ~(MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY);
259 #endif
260 }
261
262 #define mpic_read(b,r) _mpic_read(mpic->reg_type,&(b),(r))
263 #define mpic_write(b,r,v) _mpic_write(mpic->reg_type,&(b),(r),(v))
264 #define mpic_ipi_read(i) _mpic_ipi_read(mpic,(i))
265 #define mpic_ipi_write(i,v) _mpic_ipi_write(mpic,(i),(v))
266 #define mpic_cpu_read(i) _mpic_cpu_read(mpic,(i))
267 #define mpic_cpu_write(i,v) _mpic_cpu_write(mpic,(i),(v))
268 #define mpic_irq_read(s,r) _mpic_irq_read(mpic,(s),(r))
269 #define mpic_irq_write(s,r,v) _mpic_irq_write(mpic,(s),(r),(v))
270
271
272 /*
273 * Low level utility functions
274 */
275
276
277 static void _mpic_map_mmio(struct mpic *mpic, phys_addr_t phys_addr,
278 struct mpic_reg_bank *rb, unsigned int offset,
279 unsigned int size)
280 {
281 rb->base = ioremap(phys_addr + offset, size);
282 BUG_ON(rb->base == NULL);
283 }
284
285 #ifdef CONFIG_PPC_DCR
286 static void _mpic_map_dcr(struct mpic *mpic, struct device_node *node,
287 struct mpic_reg_bank *rb,
288 unsigned int offset, unsigned int size)
289 {
290 const u32 *dbasep;
291
292 dbasep = of_get_property(node, "dcr-reg", NULL);
293
294 rb->dhost = dcr_map(node, *dbasep + offset, size);
295 BUG_ON(!DCR_MAP_OK(rb->dhost));
296 }
297
298 static inline void mpic_map(struct mpic *mpic, struct device_node *node,
299 phys_addr_t phys_addr, struct mpic_reg_bank *rb,
300 unsigned int offset, unsigned int size)
301 {
302 if (mpic->flags & MPIC_USES_DCR)
303 _mpic_map_dcr(mpic, node, rb, offset, size);
304 else
305 _mpic_map_mmio(mpic, phys_addr, rb, offset, size);
306 }
307 #else /* CONFIG_PPC_DCR */
308 #define mpic_map(m,n,p,b,o,s) _mpic_map_mmio(m,p,b,o,s)
309 #endif /* !CONFIG_PPC_DCR */
310
311
312
313 /* Check if we have one of those nice broken MPICs with a flipped endian on
314 * reads from IPI registers
315 */
316 static void __init mpic_test_broken_ipi(struct mpic *mpic)
317 {
318 u32 r;
319
320 mpic_write(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0), MPIC_VECPRI_MASK);
321 r = mpic_read(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0));
322
323 if (r == le32_to_cpu(MPIC_VECPRI_MASK)) {
324 printk(KERN_INFO "mpic: Detected reversed IPI registers\n");
325 mpic->flags |= MPIC_BROKEN_IPI;
326 }
327 }
328
329 #ifdef CONFIG_MPIC_U3_HT_IRQS
330
331 /* Test if an interrupt is sourced from HyperTransport (used on broken U3s)
332 * to force the edge setting on the MPIC and do the ack workaround.
333 */
334 static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
335 {
336 if (source >= 128 || !mpic->fixups)
337 return 0;
338 return mpic->fixups[source].base != NULL;
339 }
340
341
342 static inline void mpic_ht_end_irq(struct mpic *mpic, unsigned int source)
343 {
344 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
345
346 if (fixup->applebase) {
347 unsigned int soff = (fixup->index >> 3) & ~3;
348 unsigned int mask = 1U << (fixup->index & 0x1f);
349 writel(mask, fixup->applebase + soff);
350 } else {
351 raw_spin_lock(&mpic->fixup_lock);
352 writeb(0x11 + 2 * fixup->index, fixup->base + 2);
353 writel(fixup->data, fixup->base + 4);
354 raw_spin_unlock(&mpic->fixup_lock);
355 }
356 }
357
358 static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source,
359 unsigned int irqflags)
360 {
361 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
362 unsigned long flags;
363 u32 tmp;
364
365 if (fixup->base == NULL)
366 return;
367
368 DBG("startup_ht_interrupt(0x%x, 0x%x) index: %d\n",
369 source, irqflags, fixup->index);
370 raw_spin_lock_irqsave(&mpic->fixup_lock, flags);
371 /* Enable and configure */
372 writeb(0x10 + 2 * fixup->index, fixup->base + 2);
373 tmp = readl(fixup->base + 4);
374 tmp &= ~(0x23U);
375 if (irqflags & IRQ_LEVEL)
376 tmp |= 0x22;
377 writel(tmp, fixup->base + 4);
378 raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags);
379
380 #ifdef CONFIG_PM
381 /* use the lowest bit inverted to the actual HW,
382 * set if this fixup was enabled, clear otherwise */
383 mpic->save_data[source].fixup_data = tmp | 1;
384 #endif
385 }
386
387 static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source,
388 unsigned int irqflags)
389 {
390 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
391 unsigned long flags;
392 u32 tmp;
393
394 if (fixup->base == NULL)
395 return;
396
397 DBG("shutdown_ht_interrupt(0x%x, 0x%x)\n", source, irqflags);
398
399 /* Disable */
400 raw_spin_lock_irqsave(&mpic->fixup_lock, flags);
401 writeb(0x10 + 2 * fixup->index, fixup->base + 2);
402 tmp = readl(fixup->base + 4);
403 tmp |= 1;
404 writel(tmp, fixup->base + 4);
405 raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags);
406
407 #ifdef CONFIG_PM
408 /* use the lowest bit inverted to the actual HW,
409 * set if this fixup was enabled, clear otherwise */
410 mpic->save_data[source].fixup_data = tmp & ~1;
411 #endif
412 }
413
414 #ifdef CONFIG_PCI_MSI
415 static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
416 unsigned int devfn)
417 {
418 u8 __iomem *base;
419 u8 pos, flags;
420 u64 addr = 0;
421
422 for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
423 pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
424 u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
425 if (id == PCI_CAP_ID_HT) {
426 id = readb(devbase + pos + 3);
427 if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_MSI_MAPPING)
428 break;
429 }
430 }
431
432 if (pos == 0)
433 return;
434
435 base = devbase + pos;
436
437 flags = readb(base + HT_MSI_FLAGS);
438 if (!(flags & HT_MSI_FLAGS_FIXED)) {
439 addr = readl(base + HT_MSI_ADDR_LO) & HT_MSI_ADDR_LO_MASK;
440 addr = addr | ((u64)readl(base + HT_MSI_ADDR_HI) << 32);
441 }
442
443 printk(KERN_DEBUG "mpic: - HT:%02x.%x %s MSI mapping found @ 0x%llx\n",
444 PCI_SLOT(devfn), PCI_FUNC(devfn),
445 flags & HT_MSI_FLAGS_ENABLE ? "enabled" : "disabled", addr);
446
447 if (!(flags & HT_MSI_FLAGS_ENABLE))
448 writeb(flags | HT_MSI_FLAGS_ENABLE, base + HT_MSI_FLAGS);
449 }
450 #else
451 static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
452 unsigned int devfn)
453 {
454 return;
455 }
456 #endif
457
458 static void __init mpic_scan_ht_pic(struct mpic *mpic, u8 __iomem *devbase,
459 unsigned int devfn, u32 vdid)
460 {
461 int i, irq, n;
462 u8 __iomem *base;
463 u32 tmp;
464 u8 pos;
465
466 for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
467 pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
468 u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
469 if (id == PCI_CAP_ID_HT) {
470 id = readb(devbase + pos + 3);
471 if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_IRQ)
472 break;
473 }
474 }
475 if (pos == 0)
476 return;
477
478 base = devbase + pos;
479 writeb(0x01, base + 2);
480 n = (readl(base + 4) >> 16) & 0xff;
481
482 printk(KERN_INFO "mpic: - HT:%02x.%x [0x%02x] vendor %04x device %04x"
483 " has %d irqs\n",
484 devfn >> 3, devfn & 0x7, pos, vdid & 0xffff, vdid >> 16, n + 1);
485
486 for (i = 0; i <= n; i++) {
487 writeb(0x10 + 2 * i, base + 2);
488 tmp = readl(base + 4);
489 irq = (tmp >> 16) & 0xff;
490 DBG("HT PIC index 0x%x, irq 0x%x, tmp: %08x\n", i, irq, tmp);
491 /* mask it , will be unmasked later */
492 tmp |= 0x1;
493 writel(tmp, base + 4);
494 mpic->fixups[irq].index = i;
495 mpic->fixups[irq].base = base;
496 /* Apple HT PIC has a non-standard way of doing EOIs */
497 if ((vdid & 0xffff) == 0x106b)
498 mpic->fixups[irq].applebase = devbase + 0x60;
499 else
500 mpic->fixups[irq].applebase = NULL;
501 writeb(0x11 + 2 * i, base + 2);
502 mpic->fixups[irq].data = readl(base + 4) | 0x80000000;
503 }
504 }
505
506
507 static void __init mpic_scan_ht_pics(struct mpic *mpic)
508 {
509 unsigned int devfn;
510 u8 __iomem *cfgspace;
511
512 printk(KERN_INFO "mpic: Setting up HT PICs workarounds for U3/U4\n");
513
514 /* Allocate fixups array */
515 mpic->fixups = kzalloc(128 * sizeof(*mpic->fixups), GFP_KERNEL);
516 BUG_ON(mpic->fixups == NULL);
517
518 /* Init spinlock */
519 raw_spin_lock_init(&mpic->fixup_lock);
520
521 /* Map U3 config space. We assume all IO-APICs are on the primary bus
522 * so we only need to map 64kB.
523 */
524 cfgspace = ioremap(0xf2000000, 0x10000);
525 BUG_ON(cfgspace == NULL);
526
527 /* Now we scan all slots. We do a very quick scan, we read the header
528 * type, vendor ID and device ID only, that's plenty enough
529 */
530 for (devfn = 0; devfn < 0x100; devfn++) {
531 u8 __iomem *devbase = cfgspace + (devfn << 8);
532 u8 hdr_type = readb(devbase + PCI_HEADER_TYPE);
533 u32 l = readl(devbase + PCI_VENDOR_ID);
534 u16 s;
535
536 DBG("devfn %x, l: %x\n", devfn, l);
537
538 /* If no device, skip */
539 if (l == 0xffffffff || l == 0x00000000 ||
540 l == 0x0000ffff || l == 0xffff0000)
541 goto next;
542 /* Check if is supports capability lists */
543 s = readw(devbase + PCI_STATUS);
544 if (!(s & PCI_STATUS_CAP_LIST))
545 goto next;
546
547 mpic_scan_ht_pic(mpic, devbase, devfn, l);
548 mpic_scan_ht_msi(mpic, devbase, devfn);
549
550 next:
551 /* next device, if function 0 */
552 if (PCI_FUNC(devfn) == 0 && (hdr_type & 0x80) == 0)
553 devfn += 7;
554 }
555 }
556
557 #else /* CONFIG_MPIC_U3_HT_IRQS */
558
559 static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
560 {
561 return 0;
562 }
563
564 static void __init mpic_scan_ht_pics(struct mpic *mpic)
565 {
566 }
567
568 #endif /* CONFIG_MPIC_U3_HT_IRQS */
569
570 #ifdef CONFIG_SMP
571 static int irq_choose_cpu(const struct cpumask *mask)
572 {
573 int cpuid;
574
575 if (cpumask_equal(mask, cpu_all_mask)) {
576 static int irq_rover = 0;
577 static DEFINE_RAW_SPINLOCK(irq_rover_lock);
578 unsigned long flags;
579
580 /* Round-robin distribution... */
581 do_round_robin:
582 raw_spin_lock_irqsave(&irq_rover_lock, flags);
583
584 irq_rover = cpumask_next(irq_rover, cpu_online_mask);
585 if (irq_rover >= nr_cpu_ids)
586 irq_rover = cpumask_first(cpu_online_mask);
587
588 cpuid = irq_rover;
589
590 raw_spin_unlock_irqrestore(&irq_rover_lock, flags);
591 } else {
592 cpuid = cpumask_first_and(mask, cpu_online_mask);
593 if (cpuid >= nr_cpu_ids)
594 goto do_round_robin;
595 }
596
597 return get_hard_smp_processor_id(cpuid);
598 }
599 #else
600 static int irq_choose_cpu(const struct cpumask *mask)
601 {
602 return hard_smp_processor_id();
603 }
604 #endif
605
606 #define mpic_irq_to_hw(virq) ((unsigned int)irq_map[virq].hwirq)
607
608 /* Find an mpic associated with a given linux interrupt */
609 static struct mpic *mpic_find(unsigned int irq)
610 {
611 if (irq < NUM_ISA_INTERRUPTS)
612 return NULL;
613
614 return irq_to_desc(irq)->chip_data;
615 }
616
617 /* Determine if the linux irq is an IPI */
618 static unsigned int mpic_is_ipi(struct mpic *mpic, unsigned int irq)
619 {
620 unsigned int src = mpic_irq_to_hw(irq);
621
622 return (src >= mpic->ipi_vecs[0] && src <= mpic->ipi_vecs[3]);
623 }
624
625
626 /* Convert a cpu mask from logical to physical cpu numbers. */
627 static inline u32 mpic_physmask(u32 cpumask)
628 {
629 int i;
630 u32 mask = 0;
631
632 for (i = 0; i < NR_CPUS; ++i, cpumask >>= 1)
633 mask |= (cpumask & 1) << get_hard_smp_processor_id(i);
634 return mask;
635 }
636
637 #ifdef CONFIG_SMP
638 /* Get the mpic structure from the IPI number */
639 static inline struct mpic * mpic_from_ipi(unsigned int ipi)
640 {
641 return irq_to_desc(ipi)->chip_data;
642 }
643 #endif
644
645 /* Get the mpic structure from the irq number */
646 static inline struct mpic * mpic_from_irq(unsigned int irq)
647 {
648 return irq_to_desc(irq)->chip_data;
649 }
650
651 /* Send an EOI */
652 static inline void mpic_eoi(struct mpic *mpic)
653 {
654 mpic_cpu_write(MPIC_INFO(CPU_EOI), 0);
655 (void)mpic_cpu_read(MPIC_INFO(CPU_WHOAMI));
656 }
657
658 /*
659 * Linux descriptor level callbacks
660 */
661
662
663 void mpic_unmask_irq(unsigned int irq)
664 {
665 unsigned int loops = 100000;
666 struct mpic *mpic = mpic_from_irq(irq);
667 unsigned int src = mpic_irq_to_hw(irq);
668
669 DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, irq, src);
670
671 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
672 mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) &
673 ~MPIC_VECPRI_MASK);
674 /* make sure mask gets to controller before we return to user */
675 do {
676 if (!loops--) {
677 printk(KERN_ERR "%s: timeout on hwirq %u\n",
678 __func__, src);
679 break;
680 }
681 } while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK);
682 }
683
684 void mpic_mask_irq(unsigned int irq)
685 {
686 unsigned int loops = 100000;
687 struct mpic *mpic = mpic_from_irq(irq);
688 unsigned int src = mpic_irq_to_hw(irq);
689
690 DBG("%s: disable_irq: %d (src %d)\n", mpic->name, irq, src);
691
692 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
693 mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) |
694 MPIC_VECPRI_MASK);
695
696 /* make sure mask gets to controller before we return to user */
697 do {
698 if (!loops--) {
699 printk(KERN_ERR "%s: timeout on hwirq %u\n",
700 __func__, src);
701 break;
702 }
703 } while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK));
704 }
705
706 void mpic_end_irq(unsigned int irq)
707 {
708 struct mpic *mpic = mpic_from_irq(irq);
709
710 #ifdef DEBUG_IRQ
711 DBG("%s: end_irq: %d\n", mpic->name, irq);
712 #endif
713 /* We always EOI on end_irq() even for edge interrupts since that
714 * should only lower the priority, the MPIC should have properly
715 * latched another edge interrupt coming in anyway
716 */
717
718 mpic_eoi(mpic);
719 }
720
721 #ifdef CONFIG_MPIC_U3_HT_IRQS
722
723 static void mpic_unmask_ht_irq(unsigned int irq)
724 {
725 struct mpic *mpic = mpic_from_irq(irq);
726 unsigned int src = mpic_irq_to_hw(irq);
727
728 mpic_unmask_irq(irq);
729
730 if (irq_to_desc(irq)->status & IRQ_LEVEL)
731 mpic_ht_end_irq(mpic, src);
732 }
733
734 static unsigned int mpic_startup_ht_irq(unsigned int irq)
735 {
736 struct mpic *mpic = mpic_from_irq(irq);
737 unsigned int src = mpic_irq_to_hw(irq);
738
739 mpic_unmask_irq(irq);
740 mpic_startup_ht_interrupt(mpic, src, irq_to_desc(irq)->status);
741
742 return 0;
743 }
744
745 static void mpic_shutdown_ht_irq(unsigned int irq)
746 {
747 struct mpic *mpic = mpic_from_irq(irq);
748 unsigned int src = mpic_irq_to_hw(irq);
749
750 mpic_shutdown_ht_interrupt(mpic, src, irq_to_desc(irq)->status);
751 mpic_mask_irq(irq);
752 }
753
754 static void mpic_end_ht_irq(unsigned int irq)
755 {
756 struct mpic *mpic = mpic_from_irq(irq);
757 unsigned int src = mpic_irq_to_hw(irq);
758
759 #ifdef DEBUG_IRQ
760 DBG("%s: end_irq: %d\n", mpic->name, irq);
761 #endif
762 /* We always EOI on end_irq() even for edge interrupts since that
763 * should only lower the priority, the MPIC should have properly
764 * latched another edge interrupt coming in anyway
765 */
766
767 if (irq_to_desc(irq)->status & IRQ_LEVEL)
768 mpic_ht_end_irq(mpic, src);
769 mpic_eoi(mpic);
770 }
771 #endif /* !CONFIG_MPIC_U3_HT_IRQS */
772
773 #ifdef CONFIG_SMP
774
775 static void mpic_unmask_ipi(unsigned int irq)
776 {
777 struct mpic *mpic = mpic_from_ipi(irq);
778 unsigned int src = mpic_irq_to_hw(irq) - mpic->ipi_vecs[0];
779
780 DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, irq, src);
781 mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK);
782 }
783
784 static void mpic_mask_ipi(unsigned int irq)
785 {
786 /* NEVER disable an IPI... that's just plain wrong! */
787 }
788
789 static void mpic_end_ipi(unsigned int irq)
790 {
791 struct mpic *mpic = mpic_from_ipi(irq);
792
793 /*
794 * IPIs are marked IRQ_PER_CPU. This has the side effect of
795 * preventing the IRQ_PENDING/IRQ_INPROGRESS logic from
796 * applying to them. We EOI them late to avoid re-entering.
797 * We mark IPI's with IRQF_DISABLED as they must run with
798 * irqs disabled.
799 */
800 mpic_eoi(mpic);
801 }
802
803 #endif /* CONFIG_SMP */
804
805 int mpic_set_affinity(unsigned int irq, const struct cpumask *cpumask)
806 {
807 struct mpic *mpic = mpic_from_irq(irq);
808 unsigned int src = mpic_irq_to_hw(irq);
809
810 if (mpic->flags & MPIC_SINGLE_DEST_CPU) {
811 int cpuid = irq_choose_cpu(cpumask);
812
813 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid);
814 } else {
815 cpumask_var_t tmp;
816
817 alloc_cpumask_var(&tmp, GFP_KERNEL);
818
819 cpumask_and(tmp, cpumask, cpu_online_mask);
820
821 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION),
822 mpic_physmask(cpumask_bits(tmp)[0]));
823
824 free_cpumask_var(tmp);
825 }
826
827 return 0;
828 }
829
830 static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type)
831 {
832 /* Now convert sense value */
833 switch(type & IRQ_TYPE_SENSE_MASK) {
834 case IRQ_TYPE_EDGE_RISING:
835 return MPIC_INFO(VECPRI_SENSE_EDGE) |
836 MPIC_INFO(VECPRI_POLARITY_POSITIVE);
837 case IRQ_TYPE_EDGE_FALLING:
838 case IRQ_TYPE_EDGE_BOTH:
839 return MPIC_INFO(VECPRI_SENSE_EDGE) |
840 MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
841 case IRQ_TYPE_LEVEL_HIGH:
842 return MPIC_INFO(VECPRI_SENSE_LEVEL) |
843 MPIC_INFO(VECPRI_POLARITY_POSITIVE);
844 case IRQ_TYPE_LEVEL_LOW:
845 default:
846 return MPIC_INFO(VECPRI_SENSE_LEVEL) |
847 MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
848 }
849 }
850
851 int mpic_set_irq_type(unsigned int virq, unsigned int flow_type)
852 {
853 struct mpic *mpic = mpic_from_irq(virq);
854 unsigned int src = mpic_irq_to_hw(virq);
855 struct irq_desc *desc = irq_to_desc(virq);
856 unsigned int vecpri, vold, vnew;
857
858 DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n",
859 mpic, virq, src, flow_type);
860
861 if (src >= mpic->irq_count)
862 return -EINVAL;
863
864 if (flow_type == IRQ_TYPE_NONE)
865 if (mpic->senses && src < mpic->senses_count)
866 flow_type = mpic->senses[src];
867 if (flow_type == IRQ_TYPE_NONE)
868 flow_type = IRQ_TYPE_LEVEL_LOW;
869
870 desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
871 desc->status |= flow_type & IRQ_TYPE_SENSE_MASK;
872 if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
873 desc->status |= IRQ_LEVEL;
874
875 if (mpic_is_ht_interrupt(mpic, src))
876 vecpri = MPIC_VECPRI_POLARITY_POSITIVE |
877 MPIC_VECPRI_SENSE_EDGE;
878 else
879 vecpri = mpic_type_to_vecpri(mpic, flow_type);
880
881 vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
882 vnew = vold & ~(MPIC_INFO(VECPRI_POLARITY_MASK) |
883 MPIC_INFO(VECPRI_SENSE_MASK));
884 vnew |= vecpri;
885 if (vold != vnew)
886 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew);
887
888 return 0;
889 }
890
891 void mpic_set_vector(unsigned int virq, unsigned int vector)
892 {
893 struct mpic *mpic = mpic_from_irq(virq);
894 unsigned int src = mpic_irq_to_hw(virq);
895 unsigned int vecpri;
896
897 DBG("mpic: set_vector(mpic:@%p,virq:%d,src:%d,vector:0x%x)\n",
898 mpic, virq, src, vector);
899
900 if (src >= mpic->irq_count)
901 return;
902
903 vecpri = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
904 vecpri = vecpri & ~MPIC_INFO(VECPRI_VECTOR_MASK);
905 vecpri |= vector;
906 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
907 }
908
909 static struct irq_chip mpic_irq_chip = {
910 .mask = mpic_mask_irq,
911 .unmask = mpic_unmask_irq,
912 .eoi = mpic_end_irq,
913 .set_type = mpic_set_irq_type,
914 };
915
916 #ifdef CONFIG_SMP
917 static struct irq_chip mpic_ipi_chip = {
918 .mask = mpic_mask_ipi,
919 .unmask = mpic_unmask_ipi,
920 .eoi = mpic_end_ipi,
921 };
922 #endif /* CONFIG_SMP */
923
924 #ifdef CONFIG_MPIC_U3_HT_IRQS
925 static struct irq_chip mpic_irq_ht_chip = {
926 .startup = mpic_startup_ht_irq,
927 .shutdown = mpic_shutdown_ht_irq,
928 .mask = mpic_mask_irq,
929 .unmask = mpic_unmask_ht_irq,
930 .eoi = mpic_end_ht_irq,
931 .set_type = mpic_set_irq_type,
932 };
933 #endif /* CONFIG_MPIC_U3_HT_IRQS */
934
935
936 static int mpic_host_match(struct irq_host *h, struct device_node *node)
937 {
938 /* Exact match, unless mpic node is NULL */
939 return h->of_node == NULL || h->of_node == node;
940 }
941
942 static int mpic_host_map(struct irq_host *h, unsigned int virq,
943 irq_hw_number_t hw)
944 {
945 struct mpic *mpic = h->host_data;
946 struct irq_chip *chip;
947
948 DBG("mpic: map virq %d, hwirq 0x%lx\n", virq, hw);
949
950 if (hw == mpic->spurious_vec)
951 return -EINVAL;
952 if (mpic->protected && test_bit(hw, mpic->protected))
953 return -EINVAL;
954
955 #ifdef CONFIG_SMP
956 else if (hw >= mpic->ipi_vecs[0]) {
957 WARN_ON(!(mpic->flags & MPIC_PRIMARY));
958
959 DBG("mpic: mapping as IPI\n");
960 set_irq_chip_data(virq, mpic);
961 set_irq_chip_and_handler(virq, &mpic->hc_ipi,
962 handle_percpu_irq);
963 return 0;
964 }
965 #endif /* CONFIG_SMP */
966
967 if (hw >= mpic->irq_count)
968 return -EINVAL;
969
970 mpic_msi_reserve_hwirq(mpic, hw);
971
972 /* Default chip */
973 chip = &mpic->hc_irq;
974
975 #ifdef CONFIG_MPIC_U3_HT_IRQS
976 /* Check for HT interrupts, override vecpri */
977 if (mpic_is_ht_interrupt(mpic, hw))
978 chip = &mpic->hc_ht_irq;
979 #endif /* CONFIG_MPIC_U3_HT_IRQS */
980
981 DBG("mpic: mapping to irq chip @%p\n", chip);
982
983 set_irq_chip_data(virq, mpic);
984 set_irq_chip_and_handler(virq, chip, handle_fasteoi_irq);
985
986 /* Set default irq type */
987 set_irq_type(virq, IRQ_TYPE_NONE);
988
989 return 0;
990 }
991
992 static int mpic_host_xlate(struct irq_host *h, struct device_node *ct,
993 const u32 *intspec, unsigned int intsize,
994 irq_hw_number_t *out_hwirq, unsigned int *out_flags)
995
996 {
997 static unsigned char map_mpic_senses[4] = {
998 IRQ_TYPE_EDGE_RISING,
999 IRQ_TYPE_LEVEL_LOW,
1000 IRQ_TYPE_LEVEL_HIGH,
1001 IRQ_TYPE_EDGE_FALLING,
1002 };
1003
1004 *out_hwirq = intspec[0];
1005 if (intsize > 1) {
1006 u32 mask = 0x3;
1007
1008 /* Apple invented a new race of encoding on machines with
1009 * an HT APIC. They encode, among others, the index within
1010 * the HT APIC. We don't care about it here since thankfully,
1011 * it appears that they have the APIC already properly
1012 * configured, and thus our current fixup code that reads the
1013 * APIC config works fine. However, we still need to mask out
1014 * bits in the specifier to make sure we only get bit 0 which
1015 * is the level/edge bit (the only sense bit exposed by Apple),
1016 * as their bit 1 means something else.
1017 */
1018 if (machine_is(powermac))
1019 mask = 0x1;
1020 *out_flags = map_mpic_senses[intspec[1] & mask];
1021 } else
1022 *out_flags = IRQ_TYPE_NONE;
1023
1024 DBG("mpic: xlate (%d cells: 0x%08x 0x%08x) to line 0x%lx sense 0x%x\n",
1025 intsize, intspec[0], intspec[1], *out_hwirq, *out_flags);
1026
1027 return 0;
1028 }
1029
1030 static struct irq_host_ops mpic_host_ops = {
1031 .match = mpic_host_match,
1032 .map = mpic_host_map,
1033 .xlate = mpic_host_xlate,
1034 };
1035
1036 /*
1037 * Exported functions
1038 */
1039
1040 struct mpic * __init mpic_alloc(struct device_node *node,
1041 phys_addr_t phys_addr,
1042 unsigned int flags,
1043 unsigned int isu_size,
1044 unsigned int irq_count,
1045 const char *name)
1046 {
1047 struct mpic *mpic;
1048 u32 greg_feature;
1049 const char *vers;
1050 int i;
1051 int intvec_top;
1052 u64 paddr = phys_addr;
1053
1054 mpic = kzalloc(sizeof(struct mpic), GFP_KERNEL);
1055 if (mpic == NULL)
1056 return NULL;
1057
1058 mpic->name = name;
1059
1060 mpic->hc_irq = mpic_irq_chip;
1061 mpic->hc_irq.name = name;
1062 if (flags & MPIC_PRIMARY)
1063 mpic->hc_irq.set_affinity = mpic_set_affinity;
1064 #ifdef CONFIG_MPIC_U3_HT_IRQS
1065 mpic->hc_ht_irq = mpic_irq_ht_chip;
1066 mpic->hc_ht_irq.name = name;
1067 if (flags & MPIC_PRIMARY)
1068 mpic->hc_ht_irq.set_affinity = mpic_set_affinity;
1069 #endif /* CONFIG_MPIC_U3_HT_IRQS */
1070
1071 #ifdef CONFIG_SMP
1072 mpic->hc_ipi = mpic_ipi_chip;
1073 mpic->hc_ipi.name = name;
1074 #endif /* CONFIG_SMP */
1075
1076 mpic->flags = flags;
1077 mpic->isu_size = isu_size;
1078 mpic->irq_count = irq_count;
1079 mpic->num_sources = 0; /* so far */
1080
1081 if (flags & MPIC_LARGE_VECTORS)
1082 intvec_top = 2047;
1083 else
1084 intvec_top = 255;
1085
1086 mpic->timer_vecs[0] = intvec_top - 8;
1087 mpic->timer_vecs[1] = intvec_top - 7;
1088 mpic->timer_vecs[2] = intvec_top - 6;
1089 mpic->timer_vecs[3] = intvec_top - 5;
1090 mpic->ipi_vecs[0] = intvec_top - 4;
1091 mpic->ipi_vecs[1] = intvec_top - 3;
1092 mpic->ipi_vecs[2] = intvec_top - 2;
1093 mpic->ipi_vecs[3] = intvec_top - 1;
1094 mpic->spurious_vec = intvec_top;
1095
1096 /* Check for "big-endian" in device-tree */
1097 if (node && of_get_property(node, "big-endian", NULL) != NULL)
1098 mpic->flags |= MPIC_BIG_ENDIAN;
1099
1100 /* Look for protected sources */
1101 if (node) {
1102 int psize;
1103 unsigned int bits, mapsize;
1104 const u32 *psrc =
1105 of_get_property(node, "protected-sources", &psize);
1106 if (psrc) {
1107 psize /= 4;
1108 bits = intvec_top + 1;
1109 mapsize = BITS_TO_LONGS(bits) * sizeof(unsigned long);
1110 mpic->protected = kzalloc(mapsize, GFP_KERNEL);
1111 BUG_ON(mpic->protected == NULL);
1112 for (i = 0; i < psize; i++) {
1113 if (psrc[i] > intvec_top)
1114 continue;
1115 __set_bit(psrc[i], mpic->protected);
1116 }
1117 }
1118 }
1119
1120 #ifdef CONFIG_MPIC_WEIRD
1121 mpic->hw_set = mpic_infos[MPIC_GET_REGSET(flags)];
1122 #endif
1123
1124 /* default register type */
1125 mpic->reg_type = (flags & MPIC_BIG_ENDIAN) ?
1126 mpic_access_mmio_be : mpic_access_mmio_le;
1127
1128 /* If no physical address is passed in, a device-node is mandatory */
1129 BUG_ON(paddr == 0 && node == NULL);
1130
1131 /* If no physical address passed in, check if it's dcr based */
1132 if (paddr == 0 && of_get_property(node, "dcr-reg", NULL) != NULL) {
1133 #ifdef CONFIG_PPC_DCR
1134 mpic->flags |= MPIC_USES_DCR;
1135 mpic->reg_type = mpic_access_dcr;
1136 #else
1137 BUG();
1138 #endif /* CONFIG_PPC_DCR */
1139 }
1140
1141 /* If the MPIC is not DCR based, and no physical address was passed
1142 * in, try to obtain one
1143 */
1144 if (paddr == 0 && !(mpic->flags & MPIC_USES_DCR)) {
1145 const u32 *reg = of_get_property(node, "reg", NULL);
1146 BUG_ON(reg == NULL);
1147 paddr = of_translate_address(node, reg);
1148 BUG_ON(paddr == OF_BAD_ADDR);
1149 }
1150
1151 /* Map the global registers */
1152 mpic_map(mpic, node, paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000);
1153 mpic_map(mpic, node, paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000);
1154
1155 /* Reset */
1156 if (flags & MPIC_WANTS_RESET) {
1157 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1158 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1159 | MPIC_GREG_GCONF_RESET);
1160 while( mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1161 & MPIC_GREG_GCONF_RESET)
1162 mb();
1163 }
1164
1165 /* CoreInt */
1166 if (flags & MPIC_ENABLE_COREINT)
1167 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1168 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1169 | MPIC_GREG_GCONF_COREINT);
1170
1171 if (flags & MPIC_ENABLE_MCK)
1172 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1173 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1174 | MPIC_GREG_GCONF_MCK);
1175
1176 /* Read feature register, calculate num CPUs and, for non-ISU
1177 * MPICs, num sources as well. On ISU MPICs, sources are counted
1178 * as ISUs are added
1179 */
1180 greg_feature = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0));
1181 mpic->num_cpus = ((greg_feature & MPIC_GREG_FEATURE_LAST_CPU_MASK)
1182 >> MPIC_GREG_FEATURE_LAST_CPU_SHIFT) + 1;
1183 if (isu_size == 0) {
1184 if (flags & MPIC_BROKEN_FRR_NIRQS)
1185 mpic->num_sources = mpic->irq_count;
1186 else
1187 mpic->num_sources =
1188 ((greg_feature & MPIC_GREG_FEATURE_LAST_SRC_MASK)
1189 >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT) + 1;
1190 }
1191
1192 /* Map the per-CPU registers */
1193 for (i = 0; i < mpic->num_cpus; i++) {
1194 mpic_map(mpic, node, paddr, &mpic->cpuregs[i],
1195 MPIC_INFO(CPU_BASE) + i * MPIC_INFO(CPU_STRIDE),
1196 0x1000);
1197 }
1198
1199 /* Initialize main ISU if none provided */
1200 if (mpic->isu_size == 0) {
1201 mpic->isu_size = mpic->num_sources;
1202 mpic_map(mpic, node, paddr, &mpic->isus[0],
1203 MPIC_INFO(IRQ_BASE), MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
1204 }
1205 mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1);
1206 mpic->isu_mask = (1 << mpic->isu_shift) - 1;
1207
1208 mpic->irqhost = irq_alloc_host(node, IRQ_HOST_MAP_LINEAR,
1209 isu_size ? isu_size : mpic->num_sources,
1210 &mpic_host_ops,
1211 flags & MPIC_LARGE_VECTORS ? 2048 : 256);
1212 if (mpic->irqhost == NULL)
1213 return NULL;
1214
1215 mpic->irqhost->host_data = mpic;
1216
1217 /* Display version */
1218 switch (greg_feature & MPIC_GREG_FEATURE_VERSION_MASK) {
1219 case 1:
1220 vers = "1.0";
1221 break;
1222 case 2:
1223 vers = "1.2";
1224 break;
1225 case 3:
1226 vers = "1.3";
1227 break;
1228 default:
1229 vers = "<unknown>";
1230 break;
1231 }
1232 printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %llx,"
1233 " max %d CPUs\n",
1234 name, vers, (unsigned long long)paddr, mpic->num_cpus);
1235 printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n",
1236 mpic->isu_size, mpic->isu_shift, mpic->isu_mask);
1237
1238 mpic->next = mpics;
1239 mpics = mpic;
1240
1241 if (flags & MPIC_PRIMARY) {
1242 mpic_primary = mpic;
1243 irq_set_default_host(mpic->irqhost);
1244 }
1245
1246 return mpic;
1247 }
1248
1249 void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
1250 phys_addr_t paddr)
1251 {
1252 unsigned int isu_first = isu_num * mpic->isu_size;
1253
1254 BUG_ON(isu_num >= MPIC_MAX_ISU);
1255
1256 mpic_map(mpic, mpic->irqhost->of_node,
1257 paddr, &mpic->isus[isu_num], 0,
1258 MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
1259
1260 if ((isu_first + mpic->isu_size) > mpic->num_sources)
1261 mpic->num_sources = isu_first + mpic->isu_size;
1262 }
1263
1264 void __init mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count)
1265 {
1266 mpic->senses = senses;
1267 mpic->senses_count = count;
1268 }
1269
1270 void __init mpic_init(struct mpic *mpic)
1271 {
1272 int i;
1273 int cpu;
1274
1275 BUG_ON(mpic->num_sources == 0);
1276
1277 printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources);
1278
1279 /* Set current processor priority to max */
1280 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
1281
1282 /* Initialize timers: just disable them all */
1283 for (i = 0; i < 4; i++) {
1284 mpic_write(mpic->tmregs,
1285 i * MPIC_INFO(TIMER_STRIDE) +
1286 MPIC_INFO(TIMER_DESTINATION), 0);
1287 mpic_write(mpic->tmregs,
1288 i * MPIC_INFO(TIMER_STRIDE) +
1289 MPIC_INFO(TIMER_VECTOR_PRI),
1290 MPIC_VECPRI_MASK |
1291 (mpic->timer_vecs[0] + i));
1292 }
1293
1294 /* Initialize IPIs to our reserved vectors and mark them disabled for now */
1295 mpic_test_broken_ipi(mpic);
1296 for (i = 0; i < 4; i++) {
1297 mpic_ipi_write(i,
1298 MPIC_VECPRI_MASK |
1299 (10 << MPIC_VECPRI_PRIORITY_SHIFT) |
1300 (mpic->ipi_vecs[0] + i));
1301 }
1302
1303 /* Initialize interrupt sources */
1304 if (mpic->irq_count == 0)
1305 mpic->irq_count = mpic->num_sources;
1306
1307 /* Do the HT PIC fixups on U3 broken mpic */
1308 DBG("MPIC flags: %x\n", mpic->flags);
1309 if ((mpic->flags & MPIC_U3_HT_IRQS) && (mpic->flags & MPIC_PRIMARY)) {
1310 mpic_scan_ht_pics(mpic);
1311 mpic_u3msi_init(mpic);
1312 }
1313
1314 mpic_pasemi_msi_init(mpic);
1315
1316 if (mpic->flags & MPIC_PRIMARY)
1317 cpu = hard_smp_processor_id();
1318 else
1319 cpu = 0;
1320
1321 for (i = 0; i < mpic->num_sources; i++) {
1322 /* start with vector = source number, and masked */
1323 u32 vecpri = MPIC_VECPRI_MASK | i |
1324 (8 << MPIC_VECPRI_PRIORITY_SHIFT);
1325
1326 /* check if protected */
1327 if (mpic->protected && test_bit(i, mpic->protected))
1328 continue;
1329 /* init hw */
1330 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
1331 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1 << cpu);
1332 }
1333
1334 /* Init spurious vector */
1335 mpic_write(mpic->gregs, MPIC_INFO(GREG_SPURIOUS), mpic->spurious_vec);
1336
1337 /* Disable 8259 passthrough, if supported */
1338 if (!(mpic->flags & MPIC_NO_PTHROU_DIS))
1339 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1340 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1341 | MPIC_GREG_GCONF_8259_PTHROU_DIS);
1342
1343 if (mpic->flags & MPIC_NO_BIAS)
1344 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1345 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1346 | MPIC_GREG_GCONF_NO_BIAS);
1347
1348 /* Set current processor priority to 0 */
1349 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
1350
1351 #ifdef CONFIG_PM
1352 /* allocate memory to save mpic state */
1353 mpic->save_data = kmalloc(mpic->num_sources * sizeof(*mpic->save_data),
1354 GFP_KERNEL);
1355 BUG_ON(mpic->save_data == NULL);
1356 #endif
1357 }
1358
1359 void __init mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio)
1360 {
1361 u32 v;
1362
1363 v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);
1364 v &= ~MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK;
1365 v |= MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(clock_ratio);
1366 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);
1367 }
1368
1369 void __init mpic_set_serial_int(struct mpic *mpic, int enable)
1370 {
1371 unsigned long flags;
1372 u32 v;
1373
1374 raw_spin_lock_irqsave(&mpic_lock, flags);
1375 v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);
1376 if (enable)
1377 v |= MPIC_GREG_GLOBAL_CONF_1_SIE;
1378 else
1379 v &= ~MPIC_GREG_GLOBAL_CONF_1_SIE;
1380 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);
1381 raw_spin_unlock_irqrestore(&mpic_lock, flags);
1382 }
1383
1384 void mpic_irq_set_priority(unsigned int irq, unsigned int pri)
1385 {
1386 struct mpic *mpic = mpic_find(irq);
1387 unsigned int src = mpic_irq_to_hw(irq);
1388 unsigned long flags;
1389 u32 reg;
1390
1391 if (!mpic)
1392 return;
1393
1394 raw_spin_lock_irqsave(&mpic_lock, flags);
1395 if (mpic_is_ipi(mpic, irq)) {
1396 reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) &
1397 ~MPIC_VECPRI_PRIORITY_MASK;
1398 mpic_ipi_write(src - mpic->ipi_vecs[0],
1399 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1400 } else {
1401 reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI))
1402 & ~MPIC_VECPRI_PRIORITY_MASK;
1403 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
1404 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1405 }
1406 raw_spin_unlock_irqrestore(&mpic_lock, flags);
1407 }
1408
1409 void mpic_setup_this_cpu(void)
1410 {
1411 #ifdef CONFIG_SMP
1412 struct mpic *mpic = mpic_primary;
1413 unsigned long flags;
1414 u32 msk = 1 << hard_smp_processor_id();
1415 unsigned int i;
1416
1417 BUG_ON(mpic == NULL);
1418
1419 DBG("%s: setup_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
1420
1421 raw_spin_lock_irqsave(&mpic_lock, flags);
1422
1423 /* let the mpic know we want intrs. default affinity is 0xffffffff
1424 * until changed via /proc. That's how it's done on x86. If we want
1425 * it differently, then we should make sure we also change the default
1426 * values of irq_desc[].affinity in irq.c.
1427 */
1428 if (distribute_irqs) {
1429 for (i = 0; i < mpic->num_sources ; i++)
1430 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1431 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) | msk);
1432 }
1433
1434 /* Set current processor priority to 0 */
1435 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
1436
1437 raw_spin_unlock_irqrestore(&mpic_lock, flags);
1438 #endif /* CONFIG_SMP */
1439 }
1440
1441 int mpic_cpu_get_priority(void)
1442 {
1443 struct mpic *mpic = mpic_primary;
1444
1445 return mpic_cpu_read(MPIC_INFO(CPU_CURRENT_TASK_PRI));
1446 }
1447
1448 void mpic_cpu_set_priority(int prio)
1449 {
1450 struct mpic *mpic = mpic_primary;
1451
1452 prio &= MPIC_CPU_TASKPRI_MASK;
1453 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), prio);
1454 }
1455
1456 void mpic_teardown_this_cpu(int secondary)
1457 {
1458 struct mpic *mpic = mpic_primary;
1459 unsigned long flags;
1460 u32 msk = 1 << hard_smp_processor_id();
1461 unsigned int i;
1462
1463 BUG_ON(mpic == NULL);
1464
1465 DBG("%s: teardown_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
1466 raw_spin_lock_irqsave(&mpic_lock, flags);
1467
1468 /* let the mpic know we don't want intrs. */
1469 for (i = 0; i < mpic->num_sources ; i++)
1470 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1471 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) & ~msk);
1472
1473 /* Set current processor priority to max */
1474 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
1475 /* We need to EOI the IPI since not all platforms reset the MPIC
1476 * on boot and new interrupts wouldn't get delivered otherwise.
1477 */
1478 mpic_eoi(mpic);
1479
1480 raw_spin_unlock_irqrestore(&mpic_lock, flags);
1481 }
1482
1483
1484 static unsigned int _mpic_get_one_irq(struct mpic *mpic, int reg)
1485 {
1486 u32 src;
1487
1488 src = mpic_cpu_read(reg) & MPIC_INFO(VECPRI_VECTOR_MASK);
1489 #ifdef DEBUG_LOW
1490 DBG("%s: get_one_irq(reg 0x%x): %d\n", mpic->name, reg, src);
1491 #endif
1492 if (unlikely(src == mpic->spurious_vec)) {
1493 if (mpic->flags & MPIC_SPV_EOI)
1494 mpic_eoi(mpic);
1495 return NO_IRQ;
1496 }
1497 if (unlikely(mpic->protected && test_bit(src, mpic->protected))) {
1498 if (printk_ratelimit())
1499 printk(KERN_WARNING "%s: Got protected source %d !\n",
1500 mpic->name, (int)src);
1501 mpic_eoi(mpic);
1502 return NO_IRQ;
1503 }
1504
1505 return irq_linear_revmap(mpic->irqhost, src);
1506 }
1507
1508 unsigned int mpic_get_one_irq(struct mpic *mpic)
1509 {
1510 return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_INTACK));
1511 }
1512
1513 unsigned int mpic_get_irq(void)
1514 {
1515 struct mpic *mpic = mpic_primary;
1516
1517 BUG_ON(mpic == NULL);
1518
1519 return mpic_get_one_irq(mpic);
1520 }
1521
1522 unsigned int mpic_get_coreint_irq(void)
1523 {
1524 #ifdef CONFIG_BOOKE
1525 struct mpic *mpic = mpic_primary;
1526 u32 src;
1527
1528 BUG_ON(mpic == NULL);
1529
1530 src = mfspr(SPRN_EPR);
1531
1532 if (unlikely(src == mpic->spurious_vec)) {
1533 if (mpic->flags & MPIC_SPV_EOI)
1534 mpic_eoi(mpic);
1535 return NO_IRQ;
1536 }
1537 if (unlikely(mpic->protected && test_bit(src, mpic->protected))) {
1538 if (printk_ratelimit())
1539 printk(KERN_WARNING "%s: Got protected source %d !\n",
1540 mpic->name, (int)src);
1541 return NO_IRQ;
1542 }
1543
1544 return irq_linear_revmap(mpic->irqhost, src);
1545 #else
1546 return NO_IRQ;
1547 #endif
1548 }
1549
1550 unsigned int mpic_get_mcirq(void)
1551 {
1552 struct mpic *mpic = mpic_primary;
1553
1554 BUG_ON(mpic == NULL);
1555
1556 return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_MCACK));
1557 }
1558
1559 #ifdef CONFIG_SMP
1560 void mpic_request_ipis(void)
1561 {
1562 struct mpic *mpic = mpic_primary;
1563 int i;
1564 BUG_ON(mpic == NULL);
1565
1566 printk(KERN_INFO "mpic: requesting IPIs...\n");
1567
1568 for (i = 0; i < 4; i++) {
1569 unsigned int vipi = irq_create_mapping(mpic->irqhost,
1570 mpic->ipi_vecs[0] + i);
1571 if (vipi == NO_IRQ) {
1572 printk(KERN_ERR "Failed to map %s\n", smp_ipi_name[i]);
1573 continue;
1574 }
1575 smp_request_message_ipi(vipi, i);
1576 }
1577 }
1578
1579 static void mpic_send_ipi(unsigned int ipi_no, const struct cpumask *cpu_mask)
1580 {
1581 struct mpic *mpic = mpic_primary;
1582
1583 BUG_ON(mpic == NULL);
1584
1585 #ifdef DEBUG_IPI
1586 DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, ipi_no);
1587 #endif
1588
1589 mpic_cpu_write(MPIC_INFO(CPU_IPI_DISPATCH_0) +
1590 ipi_no * MPIC_INFO(CPU_IPI_DISPATCH_STRIDE),
1591 mpic_physmask(cpumask_bits(cpu_mask)[0]));
1592 }
1593
1594 void smp_mpic_message_pass(int target, int msg)
1595 {
1596 cpumask_var_t tmp;
1597
1598 /* make sure we're sending something that translates to an IPI */
1599 if ((unsigned int)msg > 3) {
1600 printk("SMP %d: smp_message_pass: unknown msg %d\n",
1601 smp_processor_id(), msg);
1602 return;
1603 }
1604 switch (target) {
1605 case MSG_ALL:
1606 mpic_send_ipi(msg, cpu_online_mask);
1607 break;
1608 case MSG_ALL_BUT_SELF:
1609 alloc_cpumask_var(&tmp, GFP_NOWAIT);
1610 cpumask_andnot(tmp, cpu_online_mask,
1611 cpumask_of(smp_processor_id()));
1612 mpic_send_ipi(msg, tmp);
1613 free_cpumask_var(tmp);
1614 break;
1615 default:
1616 mpic_send_ipi(msg, cpumask_of(target));
1617 break;
1618 }
1619 }
1620
1621 int __init smp_mpic_probe(void)
1622 {
1623 int nr_cpus;
1624
1625 DBG("smp_mpic_probe()...\n");
1626
1627 nr_cpus = cpumask_weight(cpu_possible_mask);
1628
1629 DBG("nr_cpus: %d\n", nr_cpus);
1630
1631 if (nr_cpus > 1)
1632 mpic_request_ipis();
1633
1634 return nr_cpus;
1635 }
1636
1637 void __devinit smp_mpic_setup_cpu(int cpu)
1638 {
1639 mpic_setup_this_cpu();
1640 }
1641
1642 void mpic_reset_core(int cpu)
1643 {
1644 struct mpic *mpic = mpic_primary;
1645 u32 pir;
1646 int cpuid = get_hard_smp_processor_id(cpu);
1647
1648 /* Set target bit for core reset */
1649 pir = mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
1650 pir |= (1 << cpuid);
1651 mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir);
1652 mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
1653
1654 /* Restore target bit after reset complete */
1655 pir &= ~(1 << cpuid);
1656 mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir);
1657 mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
1658 }
1659 #endif /* CONFIG_SMP */
1660
1661 #ifdef CONFIG_PM
1662 static int mpic_suspend(struct sys_device *dev, pm_message_t state)
1663 {
1664 struct mpic *mpic = container_of(dev, struct mpic, sysdev);
1665 int i;
1666
1667 for (i = 0; i < mpic->num_sources; i++) {
1668 mpic->save_data[i].vecprio =
1669 mpic_irq_read(i, MPIC_INFO(IRQ_VECTOR_PRI));
1670 mpic->save_data[i].dest =
1671 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION));
1672 }
1673
1674 return 0;
1675 }
1676
1677 static int mpic_resume(struct sys_device *dev)
1678 {
1679 struct mpic *mpic = container_of(dev, struct mpic, sysdev);
1680 int i;
1681
1682 for (i = 0; i < mpic->num_sources; i++) {
1683 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI),
1684 mpic->save_data[i].vecprio);
1685 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1686 mpic->save_data[i].dest);
1687
1688 #ifdef CONFIG_MPIC_U3_HT_IRQS
1689 if (mpic->fixups) {
1690 struct mpic_irq_fixup *fixup = &mpic->fixups[i];
1691
1692 if (fixup->base) {
1693 /* we use the lowest bit in an inverted meaning */
1694 if ((mpic->save_data[i].fixup_data & 1) == 0)
1695 continue;
1696
1697 /* Enable and configure */
1698 writeb(0x10 + 2 * fixup->index, fixup->base + 2);
1699
1700 writel(mpic->save_data[i].fixup_data & ~1,
1701 fixup->base + 4);
1702 }
1703 }
1704 #endif
1705 } /* end for loop */
1706
1707 return 0;
1708 }
1709 #endif
1710
1711 static struct sysdev_class mpic_sysclass = {
1712 #ifdef CONFIG_PM
1713 .resume = mpic_resume,
1714 .suspend = mpic_suspend,
1715 #endif
1716 .name = "mpic",
1717 };
1718
1719 static int mpic_init_sys(void)
1720 {
1721 struct mpic *mpic = mpics;
1722 int error, id = 0;
1723
1724 error = sysdev_class_register(&mpic_sysclass);
1725
1726 while (mpic && !error) {
1727 mpic->sysdev.cls = &mpic_sysclass;
1728 mpic->sysdev.id = id++;
1729 error = sysdev_register(&mpic->sysdev);
1730 mpic = mpic->next;
1731 }
1732 return error;
1733 }
1734
1735 device_initcall(mpic_init_sys);
Linux kernel - Deliverables
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