2 * arch/powerpc/kernel/mpic.c
4 * Driver for interrupt controllers following the OpenPIC standard, the
5 * common implementation beeing IBM's MPIC. This driver also can deal
6 * with various broken implementations of this HW.
8 * Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp.
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file COPYING in the main directory of this archive
20 #include <linux/types.h>
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/irq.h>
24 #include <linux/smp.h>
25 #include <linux/interrupt.h>
26 #include <linux/bootmem.h>
27 #include <linux/spinlock.h>
28 #include <linux/pci.h>
29 #include <linux/slab.h>
31 #include <asm/ptrace.h>
32 #include <asm/signal.h>
34 #include <asm/pgtable.h>
36 #include <asm/machdep.h>
43 #define DBG(fmt...) printk(fmt)
48 static struct mpic
*mpics
;
49 static struct mpic
*mpic_primary
;
50 static DEFINE_RAW_SPINLOCK(mpic_lock
);
52 #ifdef CONFIG_PPC32 /* XXX for now */
53 #ifdef CONFIG_IRQ_ALL_CPUS
54 #define distribute_irqs (1)
56 #define distribute_irqs (0)
60 #ifdef CONFIG_MPIC_WEIRD
61 static u32 mpic_infos
[][MPIC_IDX_END
] = {
62 [0] = { /* Original OpenPIC compatible MPIC */
65 MPIC_GREG_GLOBAL_CONF_0
,
67 MPIC_GREG_IPI_VECTOR_PRI_0
,
74 MPIC_TIMER_CURRENT_CNT
,
76 MPIC_TIMER_VECTOR_PRI
,
77 MPIC_TIMER_DESTINATION
,
81 MPIC_CPU_IPI_DISPATCH_0
,
82 MPIC_CPU_IPI_DISPATCH_STRIDE
,
83 MPIC_CPU_CURRENT_TASK_PRI
,
92 MPIC_VECPRI_VECTOR_MASK
,
93 MPIC_VECPRI_POLARITY_POSITIVE
,
94 MPIC_VECPRI_POLARITY_NEGATIVE
,
95 MPIC_VECPRI_SENSE_LEVEL
,
96 MPIC_VECPRI_SENSE_EDGE
,
97 MPIC_VECPRI_POLARITY_MASK
,
98 MPIC_VECPRI_SENSE_MASK
,
101 [1] = { /* Tsi108/109 PIC */
103 TSI108_GREG_FEATURE_0
,
104 TSI108_GREG_GLOBAL_CONF_0
,
105 TSI108_GREG_VENDOR_ID
,
106 TSI108_GREG_IPI_VECTOR_PRI_0
,
107 TSI108_GREG_IPI_STRIDE
,
108 TSI108_GREG_SPURIOUS
,
109 TSI108_GREG_TIMER_FREQ
,
113 TSI108_TIMER_CURRENT_CNT
,
114 TSI108_TIMER_BASE_CNT
,
115 TSI108_TIMER_VECTOR_PRI
,
116 TSI108_TIMER_DESTINATION
,
120 TSI108_CPU_IPI_DISPATCH_0
,
121 TSI108_CPU_IPI_DISPATCH_STRIDE
,
122 TSI108_CPU_CURRENT_TASK_PRI
,
130 TSI108_IRQ_VECTOR_PRI
,
131 TSI108_VECPRI_VECTOR_MASK
,
132 TSI108_VECPRI_POLARITY_POSITIVE
,
133 TSI108_VECPRI_POLARITY_NEGATIVE
,
134 TSI108_VECPRI_SENSE_LEVEL
,
135 TSI108_VECPRI_SENSE_EDGE
,
136 TSI108_VECPRI_POLARITY_MASK
,
137 TSI108_VECPRI_SENSE_MASK
,
138 TSI108_IRQ_DESTINATION
142 #define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name]
144 #else /* CONFIG_MPIC_WEIRD */
146 #define MPIC_INFO(name) MPIC_##name
148 #endif /* CONFIG_MPIC_WEIRD */
151 * Register accessor functions
155 static inline u32
_mpic_read(enum mpic_reg_type type
,
156 struct mpic_reg_bank
*rb
,
160 #ifdef CONFIG_PPC_DCR
161 case mpic_access_dcr
:
162 return dcr_read(rb
->dhost
, reg
);
164 case mpic_access_mmio_be
:
165 return in_be32(rb
->base
+ (reg
>> 2));
166 case mpic_access_mmio_le
:
168 return in_le32(rb
->base
+ (reg
>> 2));
172 static inline void _mpic_write(enum mpic_reg_type type
,
173 struct mpic_reg_bank
*rb
,
174 unsigned int reg
, u32 value
)
177 #ifdef CONFIG_PPC_DCR
178 case mpic_access_dcr
:
179 dcr_write(rb
->dhost
, reg
, value
);
182 case mpic_access_mmio_be
:
183 out_be32(rb
->base
+ (reg
>> 2), value
);
185 case mpic_access_mmio_le
:
187 out_le32(rb
->base
+ (reg
>> 2), value
);
192 static inline u32
_mpic_ipi_read(struct mpic
*mpic
, unsigned int ipi
)
194 enum mpic_reg_type type
= mpic
->reg_type
;
195 unsigned int offset
= MPIC_INFO(GREG_IPI_VECTOR_PRI_0
) +
196 (ipi
* MPIC_INFO(GREG_IPI_STRIDE
));
198 if ((mpic
->flags
& MPIC_BROKEN_IPI
) && type
== mpic_access_mmio_le
)
199 type
= mpic_access_mmio_be
;
200 return _mpic_read(type
, &mpic
->gregs
, offset
);
203 static inline void _mpic_ipi_write(struct mpic
*mpic
, unsigned int ipi
, u32 value
)
205 unsigned int offset
= MPIC_INFO(GREG_IPI_VECTOR_PRI_0
) +
206 (ipi
* MPIC_INFO(GREG_IPI_STRIDE
));
208 _mpic_write(mpic
->reg_type
, &mpic
->gregs
, offset
, value
);
211 static inline u32
_mpic_cpu_read(struct mpic
*mpic
, unsigned int reg
)
213 unsigned int cpu
= 0;
215 if (mpic
->flags
& MPIC_PRIMARY
)
216 cpu
= hard_smp_processor_id();
217 return _mpic_read(mpic
->reg_type
, &mpic
->cpuregs
[cpu
], reg
);
220 static inline void _mpic_cpu_write(struct mpic
*mpic
, unsigned int reg
, u32 value
)
222 unsigned int cpu
= 0;
224 if (mpic
->flags
& MPIC_PRIMARY
)
225 cpu
= hard_smp_processor_id();
227 _mpic_write(mpic
->reg_type
, &mpic
->cpuregs
[cpu
], reg
, value
);
230 static inline u32
_mpic_irq_read(struct mpic
*mpic
, unsigned int src_no
, unsigned int reg
)
232 unsigned int isu
= src_no
>> mpic
->isu_shift
;
233 unsigned int idx
= src_no
& mpic
->isu_mask
;
236 val
= _mpic_read(mpic
->reg_type
, &mpic
->isus
[isu
],
237 reg
+ (idx
* MPIC_INFO(IRQ_STRIDE
)));
238 #ifdef CONFIG_MPIC_BROKEN_REGREAD
240 val
= (val
& (MPIC_VECPRI_MASK
| MPIC_VECPRI_ACTIVITY
)) |
241 mpic
->isu_reg0_shadow
[src_no
];
246 static inline void _mpic_irq_write(struct mpic
*mpic
, unsigned int src_no
,
247 unsigned int reg
, u32 value
)
249 unsigned int isu
= src_no
>> mpic
->isu_shift
;
250 unsigned int idx
= src_no
& mpic
->isu_mask
;
252 _mpic_write(mpic
->reg_type
, &mpic
->isus
[isu
],
253 reg
+ (idx
* MPIC_INFO(IRQ_STRIDE
)), value
);
255 #ifdef CONFIG_MPIC_BROKEN_REGREAD
257 mpic
->isu_reg0_shadow
[src_no
] =
258 value
& ~(MPIC_VECPRI_MASK
| MPIC_VECPRI_ACTIVITY
);
262 #define mpic_read(b,r) _mpic_read(mpic->reg_type,&(b),(r))
263 #define mpic_write(b,r,v) _mpic_write(mpic->reg_type,&(b),(r),(v))
264 #define mpic_ipi_read(i) _mpic_ipi_read(mpic,(i))
265 #define mpic_ipi_write(i,v) _mpic_ipi_write(mpic,(i),(v))
266 #define mpic_cpu_read(i) _mpic_cpu_read(mpic,(i))
267 #define mpic_cpu_write(i,v) _mpic_cpu_write(mpic,(i),(v))
268 #define mpic_irq_read(s,r) _mpic_irq_read(mpic,(s),(r))
269 #define mpic_irq_write(s,r,v) _mpic_irq_write(mpic,(s),(r),(v))
273 * Low level utility functions
277 static void _mpic_map_mmio(struct mpic
*mpic
, phys_addr_t phys_addr
,
278 struct mpic_reg_bank
*rb
, unsigned int offset
,
281 rb
->base
= ioremap(phys_addr
+ offset
, size
);
282 BUG_ON(rb
->base
== NULL
);
285 #ifdef CONFIG_PPC_DCR
286 static void _mpic_map_dcr(struct mpic
*mpic
, struct device_node
*node
,
287 struct mpic_reg_bank
*rb
,
288 unsigned int offset
, unsigned int size
)
292 dbasep
= of_get_property(node
, "dcr-reg", NULL
);
294 rb
->dhost
= dcr_map(node
, *dbasep
+ offset
, size
);
295 BUG_ON(!DCR_MAP_OK(rb
->dhost
));
298 static inline void mpic_map(struct mpic
*mpic
, struct device_node
*node
,
299 phys_addr_t phys_addr
, struct mpic_reg_bank
*rb
,
300 unsigned int offset
, unsigned int size
)
302 if (mpic
->flags
& MPIC_USES_DCR
)
303 _mpic_map_dcr(mpic
, node
, rb
, offset
, size
);
305 _mpic_map_mmio(mpic
, phys_addr
, rb
, offset
, size
);
307 #else /* CONFIG_PPC_DCR */
308 #define mpic_map(m,n,p,b,o,s) _mpic_map_mmio(m,p,b,o,s)
309 #endif /* !CONFIG_PPC_DCR */
313 /* Check if we have one of those nice broken MPICs with a flipped endian on
314 * reads from IPI registers
316 static void __init
mpic_test_broken_ipi(struct mpic
*mpic
)
320 mpic_write(mpic
->gregs
, MPIC_INFO(GREG_IPI_VECTOR_PRI_0
), MPIC_VECPRI_MASK
);
321 r
= mpic_read(mpic
->gregs
, MPIC_INFO(GREG_IPI_VECTOR_PRI_0
));
323 if (r
== le32_to_cpu(MPIC_VECPRI_MASK
)) {
324 printk(KERN_INFO
"mpic: Detected reversed IPI registers\n");
325 mpic
->flags
|= MPIC_BROKEN_IPI
;
329 #ifdef CONFIG_MPIC_U3_HT_IRQS
331 /* Test if an interrupt is sourced from HyperTransport (used on broken U3s)
332 * to force the edge setting on the MPIC and do the ack workaround.
334 static inline int mpic_is_ht_interrupt(struct mpic
*mpic
, unsigned int source
)
336 if (source
>= 128 || !mpic
->fixups
)
338 return mpic
->fixups
[source
].base
!= NULL
;
342 static inline void mpic_ht_end_irq(struct mpic
*mpic
, unsigned int source
)
344 struct mpic_irq_fixup
*fixup
= &mpic
->fixups
[source
];
346 if (fixup
->applebase
) {
347 unsigned int soff
= (fixup
->index
>> 3) & ~3;
348 unsigned int mask
= 1U << (fixup
->index
& 0x1f);
349 writel(mask
, fixup
->applebase
+ soff
);
351 raw_spin_lock(&mpic
->fixup_lock
);
352 writeb(0x11 + 2 * fixup
->index
, fixup
->base
+ 2);
353 writel(fixup
->data
, fixup
->base
+ 4);
354 raw_spin_unlock(&mpic
->fixup_lock
);
358 static void mpic_startup_ht_interrupt(struct mpic
*mpic
, unsigned int source
,
359 unsigned int irqflags
)
361 struct mpic_irq_fixup
*fixup
= &mpic
->fixups
[source
];
365 if (fixup
->base
== NULL
)
368 DBG("startup_ht_interrupt(0x%x, 0x%x) index: %d\n",
369 source
, irqflags
, fixup
->index
);
370 raw_spin_lock_irqsave(&mpic
->fixup_lock
, flags
);
371 /* Enable and configure */
372 writeb(0x10 + 2 * fixup
->index
, fixup
->base
+ 2);
373 tmp
= readl(fixup
->base
+ 4);
375 if (irqflags
& IRQ_LEVEL
)
377 writel(tmp
, fixup
->base
+ 4);
378 raw_spin_unlock_irqrestore(&mpic
->fixup_lock
, flags
);
381 /* use the lowest bit inverted to the actual HW,
382 * set if this fixup was enabled, clear otherwise */
383 mpic
->save_data
[source
].fixup_data
= tmp
| 1;
387 static void mpic_shutdown_ht_interrupt(struct mpic
*mpic
, unsigned int source
,
388 unsigned int irqflags
)
390 struct mpic_irq_fixup
*fixup
= &mpic
->fixups
[source
];
394 if (fixup
->base
== NULL
)
397 DBG("shutdown_ht_interrupt(0x%x, 0x%x)\n", source
, irqflags
);
400 raw_spin_lock_irqsave(&mpic
->fixup_lock
, flags
);
401 writeb(0x10 + 2 * fixup
->index
, fixup
->base
+ 2);
402 tmp
= readl(fixup
->base
+ 4);
404 writel(tmp
, fixup
->base
+ 4);
405 raw_spin_unlock_irqrestore(&mpic
->fixup_lock
, flags
);
408 /* use the lowest bit inverted to the actual HW,
409 * set if this fixup was enabled, clear otherwise */
410 mpic
->save_data
[source
].fixup_data
= tmp
& ~1;
414 #ifdef CONFIG_PCI_MSI
415 static void __init
mpic_scan_ht_msi(struct mpic
*mpic
, u8 __iomem
*devbase
,
422 for (pos
= readb(devbase
+ PCI_CAPABILITY_LIST
); pos
!= 0;
423 pos
= readb(devbase
+ pos
+ PCI_CAP_LIST_NEXT
)) {
424 u8 id
= readb(devbase
+ pos
+ PCI_CAP_LIST_ID
);
425 if (id
== PCI_CAP_ID_HT
) {
426 id
= readb(devbase
+ pos
+ 3);
427 if ((id
& HT_5BIT_CAP_MASK
) == HT_CAPTYPE_MSI_MAPPING
)
435 base
= devbase
+ pos
;
437 flags
= readb(base
+ HT_MSI_FLAGS
);
438 if (!(flags
& HT_MSI_FLAGS_FIXED
)) {
439 addr
= readl(base
+ HT_MSI_ADDR_LO
) & HT_MSI_ADDR_LO_MASK
;
440 addr
= addr
| ((u64
)readl(base
+ HT_MSI_ADDR_HI
) << 32);
443 printk(KERN_DEBUG
"mpic: - HT:%02x.%x %s MSI mapping found @ 0x%llx\n",
444 PCI_SLOT(devfn
), PCI_FUNC(devfn
),
445 flags
& HT_MSI_FLAGS_ENABLE
? "enabled" : "disabled", addr
);
447 if (!(flags
& HT_MSI_FLAGS_ENABLE
))
448 writeb(flags
| HT_MSI_FLAGS_ENABLE
, base
+ HT_MSI_FLAGS
);
451 static void __init
mpic_scan_ht_msi(struct mpic
*mpic
, u8 __iomem
*devbase
,
458 static void __init
mpic_scan_ht_pic(struct mpic
*mpic
, u8 __iomem
*devbase
,
459 unsigned int devfn
, u32 vdid
)
466 for (pos
= readb(devbase
+ PCI_CAPABILITY_LIST
); pos
!= 0;
467 pos
= readb(devbase
+ pos
+ PCI_CAP_LIST_NEXT
)) {
468 u8 id
= readb(devbase
+ pos
+ PCI_CAP_LIST_ID
);
469 if (id
== PCI_CAP_ID_HT
) {
470 id
= readb(devbase
+ pos
+ 3);
471 if ((id
& HT_5BIT_CAP_MASK
) == HT_CAPTYPE_IRQ
)
478 base
= devbase
+ pos
;
479 writeb(0x01, base
+ 2);
480 n
= (readl(base
+ 4) >> 16) & 0xff;
482 printk(KERN_INFO
"mpic: - HT:%02x.%x [0x%02x] vendor %04x device %04x"
484 devfn
>> 3, devfn
& 0x7, pos
, vdid
& 0xffff, vdid
>> 16, n
+ 1);
486 for (i
= 0; i
<= n
; i
++) {
487 writeb(0x10 + 2 * i
, base
+ 2);
488 tmp
= readl(base
+ 4);
489 irq
= (tmp
>> 16) & 0xff;
490 DBG("HT PIC index 0x%x, irq 0x%x, tmp: %08x\n", i
, irq
, tmp
);
491 /* mask it , will be unmasked later */
493 writel(tmp
, base
+ 4);
494 mpic
->fixups
[irq
].index
= i
;
495 mpic
->fixups
[irq
].base
= base
;
496 /* Apple HT PIC has a non-standard way of doing EOIs */
497 if ((vdid
& 0xffff) == 0x106b)
498 mpic
->fixups
[irq
].applebase
= devbase
+ 0x60;
500 mpic
->fixups
[irq
].applebase
= NULL
;
501 writeb(0x11 + 2 * i
, base
+ 2);
502 mpic
->fixups
[irq
].data
= readl(base
+ 4) | 0x80000000;
507 static void __init
mpic_scan_ht_pics(struct mpic
*mpic
)
510 u8 __iomem
*cfgspace
;
512 printk(KERN_INFO
"mpic: Setting up HT PICs workarounds for U3/U4\n");
514 /* Allocate fixups array */
515 mpic
->fixups
= kzalloc(128 * sizeof(*mpic
->fixups
), GFP_KERNEL
);
516 BUG_ON(mpic
->fixups
== NULL
);
519 raw_spin_lock_init(&mpic
->fixup_lock
);
521 /* Map U3 config space. We assume all IO-APICs are on the primary bus
522 * so we only need to map 64kB.
524 cfgspace
= ioremap(0xf2000000, 0x10000);
525 BUG_ON(cfgspace
== NULL
);
527 /* Now we scan all slots. We do a very quick scan, we read the header
528 * type, vendor ID and device ID only, that's plenty enough
530 for (devfn
= 0; devfn
< 0x100; devfn
++) {
531 u8 __iomem
*devbase
= cfgspace
+ (devfn
<< 8);
532 u8 hdr_type
= readb(devbase
+ PCI_HEADER_TYPE
);
533 u32 l
= readl(devbase
+ PCI_VENDOR_ID
);
536 DBG("devfn %x, l: %x\n", devfn
, l
);
538 /* If no device, skip */
539 if (l
== 0xffffffff || l
== 0x00000000 ||
540 l
== 0x0000ffff || l
== 0xffff0000)
542 /* Check if is supports capability lists */
543 s
= readw(devbase
+ PCI_STATUS
);
544 if (!(s
& PCI_STATUS_CAP_LIST
))
547 mpic_scan_ht_pic(mpic
, devbase
, devfn
, l
);
548 mpic_scan_ht_msi(mpic
, devbase
, devfn
);
551 /* next device, if function 0 */
552 if (PCI_FUNC(devfn
) == 0 && (hdr_type
& 0x80) == 0)
557 #else /* CONFIG_MPIC_U3_HT_IRQS */
559 static inline int mpic_is_ht_interrupt(struct mpic
*mpic
, unsigned int source
)
564 static void __init
mpic_scan_ht_pics(struct mpic
*mpic
)
568 #endif /* CONFIG_MPIC_U3_HT_IRQS */
571 static int irq_choose_cpu(const struct cpumask
*mask
)
575 if (cpumask_equal(mask
, cpu_all_mask
)) {
576 static int irq_rover
= 0;
577 static DEFINE_RAW_SPINLOCK(irq_rover_lock
);
580 /* Round-robin distribution... */
582 raw_spin_lock_irqsave(&irq_rover_lock
, flags
);
584 irq_rover
= cpumask_next(irq_rover
, cpu_online_mask
);
585 if (irq_rover
>= nr_cpu_ids
)
586 irq_rover
= cpumask_first(cpu_online_mask
);
590 raw_spin_unlock_irqrestore(&irq_rover_lock
, flags
);
592 cpuid
= cpumask_first_and(mask
, cpu_online_mask
);
593 if (cpuid
>= nr_cpu_ids
)
597 return get_hard_smp_processor_id(cpuid
);
600 static int irq_choose_cpu(const struct cpumask
*mask
)
602 return hard_smp_processor_id();
606 #define mpic_irq_to_hw(virq) ((unsigned int)irq_map[virq].hwirq)
608 /* Find an mpic associated with a given linux interrupt */
609 static struct mpic
*mpic_find(unsigned int irq
)
611 if (irq
< NUM_ISA_INTERRUPTS
)
614 return get_irq_chip_data(irq
);
617 /* Determine if the linux irq is an IPI */
618 static unsigned int mpic_is_ipi(struct mpic
*mpic
, unsigned int irq
)
620 unsigned int src
= mpic_irq_to_hw(irq
);
622 return (src
>= mpic
->ipi_vecs
[0] && src
<= mpic
->ipi_vecs
[3]);
626 /* Convert a cpu mask from logical to physical cpu numbers. */
627 static inline u32
mpic_physmask(u32 cpumask
)
632 for (i
= 0; i
< NR_CPUS
; ++i
, cpumask
>>= 1)
633 mask
|= (cpumask
& 1) << get_hard_smp_processor_id(i
);
638 /* Get the mpic structure from the IPI number */
639 static inline struct mpic
* mpic_from_ipi(struct irq_data
*d
)
641 return irq_data_get_irq_chip_data(d
);
645 /* Get the mpic structure from the irq number */
646 static inline struct mpic
* mpic_from_irq(unsigned int irq
)
648 return get_irq_chip_data(irq
);
651 /* Get the mpic structure from the irq data */
652 static inline struct mpic
* mpic_from_irq_data(struct irq_data
*d
)
654 return irq_data_get_irq_chip_data(d
);
658 static inline void mpic_eoi(struct mpic
*mpic
)
660 mpic_cpu_write(MPIC_INFO(CPU_EOI
), 0);
661 (void)mpic_cpu_read(MPIC_INFO(CPU_WHOAMI
));
665 * Linux descriptor level callbacks
669 void mpic_unmask_irq(struct irq_data
*d
)
671 unsigned int loops
= 100000;
672 struct mpic
*mpic
= mpic_from_irq_data(d
);
673 unsigned int src
= mpic_irq_to_hw(d
->irq
);
675 DBG("%p: %s: enable_irq: %d (src %d)\n", mpic
, mpic
->name
, d
->irq
, src
);
677 mpic_irq_write(src
, MPIC_INFO(IRQ_VECTOR_PRI
),
678 mpic_irq_read(src
, MPIC_INFO(IRQ_VECTOR_PRI
)) &
680 /* make sure mask gets to controller before we return to user */
683 printk(KERN_ERR
"%s: timeout on hwirq %u\n",
687 } while(mpic_irq_read(src
, MPIC_INFO(IRQ_VECTOR_PRI
)) & MPIC_VECPRI_MASK
);
690 void mpic_mask_irq(struct irq_data
*d
)
692 unsigned int loops
= 100000;
693 struct mpic
*mpic
= mpic_from_irq_data(d
);
694 unsigned int src
= mpic_irq_to_hw(d
->irq
);
696 DBG("%s: disable_irq: %d (src %d)\n", mpic
->name
, d
->irq
, src
);
698 mpic_irq_write(src
, MPIC_INFO(IRQ_VECTOR_PRI
),
699 mpic_irq_read(src
, MPIC_INFO(IRQ_VECTOR_PRI
)) |
702 /* make sure mask gets to controller before we return to user */
705 printk(KERN_ERR
"%s: timeout on hwirq %u\n",
709 } while(!(mpic_irq_read(src
, MPIC_INFO(IRQ_VECTOR_PRI
)) & MPIC_VECPRI_MASK
));
712 void mpic_end_irq(struct irq_data
*d
)
714 struct mpic
*mpic
= mpic_from_irq_data(d
);
717 DBG("%s: end_irq: %d\n", mpic
->name
, d
->irq
);
719 /* We always EOI on end_irq() even for edge interrupts since that
720 * should only lower the priority, the MPIC should have properly
721 * latched another edge interrupt coming in anyway
727 #ifdef CONFIG_MPIC_U3_HT_IRQS
729 static void mpic_unmask_ht_irq(struct irq_data
*d
)
731 struct mpic
*mpic
= mpic_from_irq_data(d
);
732 unsigned int src
= mpic_irq_to_hw(d
->irq
);
736 if (irq_to_desc(d
->irq
)->status
& IRQ_LEVEL
)
737 mpic_ht_end_irq(mpic
, src
);
740 static unsigned int mpic_startup_ht_irq(struct irq_data
*d
)
742 struct mpic
*mpic
= mpic_from_irq_data(d
);
743 unsigned int src
= mpic_irq_to_hw(d
->irq
);
746 mpic_startup_ht_interrupt(mpic
, src
, irq_to_desc(d
->irq
)->status
);
751 static void mpic_shutdown_ht_irq(struct irq_data
*d
)
753 struct mpic
*mpic
= mpic_from_irq_data(d
);
754 unsigned int src
= mpic_irq_to_hw(d
->irq
);
756 mpic_shutdown_ht_interrupt(mpic
, src
, irq_to_desc(d
->irq
)->status
);
760 static void mpic_end_ht_irq(struct irq_data
*d
)
762 struct mpic
*mpic
= mpic_from_irq_data(d
);
763 unsigned int src
= mpic_irq_to_hw(d
->irq
);
766 DBG("%s: end_irq: %d\n", mpic
->name
, d
->irq
);
768 /* We always EOI on end_irq() even for edge interrupts since that
769 * should only lower the priority, the MPIC should have properly
770 * latched another edge interrupt coming in anyway
773 if (irq_to_desc(d
->irq
)->status
& IRQ_LEVEL
)
774 mpic_ht_end_irq(mpic
, src
);
777 #endif /* !CONFIG_MPIC_U3_HT_IRQS */
781 static void mpic_unmask_ipi(struct irq_data
*d
)
783 struct mpic
*mpic
= mpic_from_ipi(d
);
784 unsigned int src
= mpic_irq_to_hw(d
->irq
) - mpic
->ipi_vecs
[0];
786 DBG("%s: enable_ipi: %d (ipi %d)\n", mpic
->name
, d
->irq
, src
);
787 mpic_ipi_write(src
, mpic_ipi_read(src
) & ~MPIC_VECPRI_MASK
);
790 static void mpic_mask_ipi(struct irq_data
*d
)
792 /* NEVER disable an IPI... that's just plain wrong! */
795 static void mpic_end_ipi(struct irq_data
*d
)
797 struct mpic
*mpic
= mpic_from_ipi(d
);
800 * IPIs are marked IRQ_PER_CPU. This has the side effect of
801 * preventing the IRQ_PENDING/IRQ_INPROGRESS logic from
802 * applying to them. We EOI them late to avoid re-entering.
803 * We mark IPI's with IRQF_DISABLED as they must run with
809 #endif /* CONFIG_SMP */
811 int mpic_set_affinity(struct irq_data
*d
, const struct cpumask
*cpumask
,
814 struct mpic
*mpic
= mpic_from_irq_data(d
);
815 unsigned int src
= mpic_irq_to_hw(d
->irq
);
817 if (mpic
->flags
& MPIC_SINGLE_DEST_CPU
) {
818 int cpuid
= irq_choose_cpu(cpumask
);
820 mpic_irq_write(src
, MPIC_INFO(IRQ_DESTINATION
), 1 << cpuid
);
824 alloc_cpumask_var(&tmp
, GFP_KERNEL
);
826 cpumask_and(tmp
, cpumask
, cpu_online_mask
);
828 mpic_irq_write(src
, MPIC_INFO(IRQ_DESTINATION
),
829 mpic_physmask(cpumask_bits(tmp
)[0]));
831 free_cpumask_var(tmp
);
837 static unsigned int mpic_type_to_vecpri(struct mpic
*mpic
, unsigned int type
)
839 /* Now convert sense value */
840 switch(type
& IRQ_TYPE_SENSE_MASK
) {
841 case IRQ_TYPE_EDGE_RISING
:
842 return MPIC_INFO(VECPRI_SENSE_EDGE
) |
843 MPIC_INFO(VECPRI_POLARITY_POSITIVE
);
844 case IRQ_TYPE_EDGE_FALLING
:
845 case IRQ_TYPE_EDGE_BOTH
:
846 return MPIC_INFO(VECPRI_SENSE_EDGE
) |
847 MPIC_INFO(VECPRI_POLARITY_NEGATIVE
);
848 case IRQ_TYPE_LEVEL_HIGH
:
849 return MPIC_INFO(VECPRI_SENSE_LEVEL
) |
850 MPIC_INFO(VECPRI_POLARITY_POSITIVE
);
851 case IRQ_TYPE_LEVEL_LOW
:
853 return MPIC_INFO(VECPRI_SENSE_LEVEL
) |
854 MPIC_INFO(VECPRI_POLARITY_NEGATIVE
);
858 int mpic_set_irq_type(struct irq_data
*d
, unsigned int flow_type
)
860 struct mpic
*mpic
= mpic_from_irq_data(d
);
861 unsigned int src
= mpic_irq_to_hw(d
->irq
);
862 struct irq_desc
*desc
= irq_to_desc(d
->irq
);
863 unsigned int vecpri
, vold
, vnew
;
865 DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n",
866 mpic
, d
->irq
, src
, flow_type
);
868 if (src
>= mpic
->irq_count
)
871 if (flow_type
== IRQ_TYPE_NONE
)
872 if (mpic
->senses
&& src
< mpic
->senses_count
)
873 flow_type
= mpic
->senses
[src
];
874 if (flow_type
== IRQ_TYPE_NONE
)
875 flow_type
= IRQ_TYPE_LEVEL_LOW
;
877 desc
->status
&= ~(IRQ_TYPE_SENSE_MASK
| IRQ_LEVEL
);
878 desc
->status
|= flow_type
& IRQ_TYPE_SENSE_MASK
;
879 if (flow_type
& (IRQ_TYPE_LEVEL_HIGH
| IRQ_TYPE_LEVEL_LOW
))
880 desc
->status
|= IRQ_LEVEL
;
882 if (mpic_is_ht_interrupt(mpic
, src
))
883 vecpri
= MPIC_VECPRI_POLARITY_POSITIVE
|
884 MPIC_VECPRI_SENSE_EDGE
;
886 vecpri
= mpic_type_to_vecpri(mpic
, flow_type
);
888 vold
= mpic_irq_read(src
, MPIC_INFO(IRQ_VECTOR_PRI
));
889 vnew
= vold
& ~(MPIC_INFO(VECPRI_POLARITY_MASK
) |
890 MPIC_INFO(VECPRI_SENSE_MASK
));
893 mpic_irq_write(src
, MPIC_INFO(IRQ_VECTOR_PRI
), vnew
);
898 void mpic_set_vector(unsigned int virq
, unsigned int vector
)
900 struct mpic
*mpic
= mpic_from_irq(virq
);
901 unsigned int src
= mpic_irq_to_hw(virq
);
904 DBG("mpic: set_vector(mpic:@%p,virq:%d,src:%d,vector:0x%x)\n",
905 mpic
, virq
, src
, vector
);
907 if (src
>= mpic
->irq_count
)
910 vecpri
= mpic_irq_read(src
, MPIC_INFO(IRQ_VECTOR_PRI
));
911 vecpri
= vecpri
& ~MPIC_INFO(VECPRI_VECTOR_MASK
);
913 mpic_irq_write(src
, MPIC_INFO(IRQ_VECTOR_PRI
), vecpri
);
916 static struct irq_chip mpic_irq_chip
= {
917 .irq_mask
= mpic_mask_irq
,
918 .irq_unmask
= mpic_unmask_irq
,
919 .irq_eoi
= mpic_end_irq
,
920 .irq_set_type
= mpic_set_irq_type
,
924 static struct irq_chip mpic_ipi_chip
= {
925 .irq_mask
= mpic_mask_ipi
,
926 .irq_unmask
= mpic_unmask_ipi
,
927 .irq_eoi
= mpic_end_ipi
,
929 #endif /* CONFIG_SMP */
931 #ifdef CONFIG_MPIC_U3_HT_IRQS
932 static struct irq_chip mpic_irq_ht_chip
= {
933 .irq_startup
= mpic_startup_ht_irq
,
934 .irq_shutdown
= mpic_shutdown_ht_irq
,
935 .irq_mask
= mpic_mask_irq
,
936 .irq_unmask
= mpic_unmask_ht_irq
,
937 .irq_eoi
= mpic_end_ht_irq
,
938 .irq_set_type
= mpic_set_irq_type
,
940 #endif /* CONFIG_MPIC_U3_HT_IRQS */
943 static int mpic_host_match(struct irq_host
*h
, struct device_node
*node
)
945 /* Exact match, unless mpic node is NULL */
946 return h
->of_node
== NULL
|| h
->of_node
== node
;
949 static int mpic_host_map(struct irq_host
*h
, unsigned int virq
,
952 struct mpic
*mpic
= h
->host_data
;
953 struct irq_chip
*chip
;
955 DBG("mpic: map virq %d, hwirq 0x%lx\n", virq
, hw
);
957 if (hw
== mpic
->spurious_vec
)
959 if (mpic
->protected && test_bit(hw
, mpic
->protected))
963 else if (hw
>= mpic
->ipi_vecs
[0]) {
964 WARN_ON(!(mpic
->flags
& MPIC_PRIMARY
));
966 DBG("mpic: mapping as IPI\n");
967 set_irq_chip_data(virq
, mpic
);
968 set_irq_chip_and_handler(virq
, &mpic
->hc_ipi
,
972 #endif /* CONFIG_SMP */
974 if (hw
>= mpic
->irq_count
)
977 mpic_msi_reserve_hwirq(mpic
, hw
);
980 chip
= &mpic
->hc_irq
;
982 #ifdef CONFIG_MPIC_U3_HT_IRQS
983 /* Check for HT interrupts, override vecpri */
984 if (mpic_is_ht_interrupt(mpic
, hw
))
985 chip
= &mpic
->hc_ht_irq
;
986 #endif /* CONFIG_MPIC_U3_HT_IRQS */
988 DBG("mpic: mapping to irq chip @%p\n", chip
);
990 set_irq_chip_data(virq
, mpic
);
991 set_irq_chip_and_handler(virq
, chip
, handle_fasteoi_irq
);
993 /* Set default irq type */
994 set_irq_type(virq
, IRQ_TYPE_NONE
);
999 static int mpic_host_xlate(struct irq_host
*h
, struct device_node
*ct
,
1000 const u32
*intspec
, unsigned int intsize
,
1001 irq_hw_number_t
*out_hwirq
, unsigned int *out_flags
)
1004 static unsigned char map_mpic_senses
[4] = {
1005 IRQ_TYPE_EDGE_RISING
,
1007 IRQ_TYPE_LEVEL_HIGH
,
1008 IRQ_TYPE_EDGE_FALLING
,
1011 *out_hwirq
= intspec
[0];
1015 /* Apple invented a new race of encoding on machines with
1016 * an HT APIC. They encode, among others, the index within
1017 * the HT APIC. We don't care about it here since thankfully,
1018 * it appears that they have the APIC already properly
1019 * configured, and thus our current fixup code that reads the
1020 * APIC config works fine. However, we still need to mask out
1021 * bits in the specifier to make sure we only get bit 0 which
1022 * is the level/edge bit (the only sense bit exposed by Apple),
1023 * as their bit 1 means something else.
1025 if (machine_is(powermac
))
1027 *out_flags
= map_mpic_senses
[intspec
[1] & mask
];
1029 *out_flags
= IRQ_TYPE_NONE
;
1031 DBG("mpic: xlate (%d cells: 0x%08x 0x%08x) to line 0x%lx sense 0x%x\n",
1032 intsize
, intspec
[0], intspec
[1], *out_hwirq
, *out_flags
);
1037 static struct irq_host_ops mpic_host_ops
= {
1038 .match
= mpic_host_match
,
1039 .map
= mpic_host_map
,
1040 .xlate
= mpic_host_xlate
,
1044 * Exported functions
1047 struct mpic
* __init
mpic_alloc(struct device_node
*node
,
1048 phys_addr_t phys_addr
,
1050 unsigned int isu_size
,
1051 unsigned int irq_count
,
1059 u64 paddr
= phys_addr
;
1061 mpic
= kzalloc(sizeof(struct mpic
), GFP_KERNEL
);
1067 mpic
->hc_irq
= mpic_irq_chip
;
1068 mpic
->hc_irq
.name
= name
;
1069 if (flags
& MPIC_PRIMARY
)
1070 mpic
->hc_irq
.irq_set_affinity
= mpic_set_affinity
;
1071 #ifdef CONFIG_MPIC_U3_HT_IRQS
1072 mpic
->hc_ht_irq
= mpic_irq_ht_chip
;
1073 mpic
->hc_ht_irq
.name
= name
;
1074 if (flags
& MPIC_PRIMARY
)
1075 mpic
->hc_ht_irq
.irq_set_affinity
= mpic_set_affinity
;
1076 #endif /* CONFIG_MPIC_U3_HT_IRQS */
1079 mpic
->hc_ipi
= mpic_ipi_chip
;
1080 mpic
->hc_ipi
.name
= name
;
1081 #endif /* CONFIG_SMP */
1083 mpic
->flags
= flags
;
1084 mpic
->isu_size
= isu_size
;
1085 mpic
->irq_count
= irq_count
;
1086 mpic
->num_sources
= 0; /* so far */
1088 if (flags
& MPIC_LARGE_VECTORS
)
1093 mpic
->timer_vecs
[0] = intvec_top
- 8;
1094 mpic
->timer_vecs
[1] = intvec_top
- 7;
1095 mpic
->timer_vecs
[2] = intvec_top
- 6;
1096 mpic
->timer_vecs
[3] = intvec_top
- 5;
1097 mpic
->ipi_vecs
[0] = intvec_top
- 4;
1098 mpic
->ipi_vecs
[1] = intvec_top
- 3;
1099 mpic
->ipi_vecs
[2] = intvec_top
- 2;
1100 mpic
->ipi_vecs
[3] = intvec_top
- 1;
1101 mpic
->spurious_vec
= intvec_top
;
1103 /* Check for "big-endian" in device-tree */
1104 if (node
&& of_get_property(node
, "big-endian", NULL
) != NULL
)
1105 mpic
->flags
|= MPIC_BIG_ENDIAN
;
1107 /* Look for protected sources */
1110 unsigned int bits
, mapsize
;
1112 of_get_property(node
, "protected-sources", &psize
);
1115 bits
= intvec_top
+ 1;
1116 mapsize
= BITS_TO_LONGS(bits
) * sizeof(unsigned long);
1117 mpic
->protected = kzalloc(mapsize
, GFP_KERNEL
);
1118 BUG_ON(mpic
->protected == NULL
);
1119 for (i
= 0; i
< psize
; i
++) {
1120 if (psrc
[i
] > intvec_top
)
1122 __set_bit(psrc
[i
], mpic
->protected);
1127 #ifdef CONFIG_MPIC_WEIRD
1128 mpic
->hw_set
= mpic_infos
[MPIC_GET_REGSET(flags
)];
1131 /* default register type */
1132 mpic
->reg_type
= (flags
& MPIC_BIG_ENDIAN
) ?
1133 mpic_access_mmio_be
: mpic_access_mmio_le
;
1135 /* If no physical address is passed in, a device-node is mandatory */
1136 BUG_ON(paddr
== 0 && node
== NULL
);
1138 /* If no physical address passed in, check if it's dcr based */
1139 if (paddr
== 0 && of_get_property(node
, "dcr-reg", NULL
) != NULL
) {
1140 #ifdef CONFIG_PPC_DCR
1141 mpic
->flags
|= MPIC_USES_DCR
;
1142 mpic
->reg_type
= mpic_access_dcr
;
1145 #endif /* CONFIG_PPC_DCR */
1148 /* If the MPIC is not DCR based, and no physical address was passed
1149 * in, try to obtain one
1151 if (paddr
== 0 && !(mpic
->flags
& MPIC_USES_DCR
)) {
1152 const u32
*reg
= of_get_property(node
, "reg", NULL
);
1153 BUG_ON(reg
== NULL
);
1154 paddr
= of_translate_address(node
, reg
);
1155 BUG_ON(paddr
== OF_BAD_ADDR
);
1158 /* Map the global registers */
1159 mpic_map(mpic
, node
, paddr
, &mpic
->gregs
, MPIC_INFO(GREG_BASE
), 0x1000);
1160 mpic_map(mpic
, node
, paddr
, &mpic
->tmregs
, MPIC_INFO(TIMER_BASE
), 0x1000);
1163 if (flags
& MPIC_WANTS_RESET
) {
1164 mpic_write(mpic
->gregs
, MPIC_INFO(GREG_GLOBAL_CONF_0
),
1165 mpic_read(mpic
->gregs
, MPIC_INFO(GREG_GLOBAL_CONF_0
))
1166 | MPIC_GREG_GCONF_RESET
);
1167 while( mpic_read(mpic
->gregs
, MPIC_INFO(GREG_GLOBAL_CONF_0
))
1168 & MPIC_GREG_GCONF_RESET
)
1173 if (flags
& MPIC_ENABLE_COREINT
)
1174 mpic_write(mpic
->gregs
, MPIC_INFO(GREG_GLOBAL_CONF_0
),
1175 mpic_read(mpic
->gregs
, MPIC_INFO(GREG_GLOBAL_CONF_0
))
1176 | MPIC_GREG_GCONF_COREINT
);
1178 if (flags
& MPIC_ENABLE_MCK
)
1179 mpic_write(mpic
->gregs
, MPIC_INFO(GREG_GLOBAL_CONF_0
),
1180 mpic_read(mpic
->gregs
, MPIC_INFO(GREG_GLOBAL_CONF_0
))
1181 | MPIC_GREG_GCONF_MCK
);
1183 /* Read feature register, calculate num CPUs and, for non-ISU
1184 * MPICs, num sources as well. On ISU MPICs, sources are counted
1187 greg_feature
= mpic_read(mpic
->gregs
, MPIC_INFO(GREG_FEATURE_0
));
1188 mpic
->num_cpus
= ((greg_feature
& MPIC_GREG_FEATURE_LAST_CPU_MASK
)
1189 >> MPIC_GREG_FEATURE_LAST_CPU_SHIFT
) + 1;
1190 if (isu_size
== 0) {
1191 if (flags
& MPIC_BROKEN_FRR_NIRQS
)
1192 mpic
->num_sources
= mpic
->irq_count
;
1195 ((greg_feature
& MPIC_GREG_FEATURE_LAST_SRC_MASK
)
1196 >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT
) + 1;
1199 /* Map the per-CPU registers */
1200 for (i
= 0; i
< mpic
->num_cpus
; i
++) {
1201 mpic_map(mpic
, node
, paddr
, &mpic
->cpuregs
[i
],
1202 MPIC_INFO(CPU_BASE
) + i
* MPIC_INFO(CPU_STRIDE
),
1206 /* Initialize main ISU if none provided */
1207 if (mpic
->isu_size
== 0) {
1208 mpic
->isu_size
= mpic
->num_sources
;
1209 mpic_map(mpic
, node
, paddr
, &mpic
->isus
[0],
1210 MPIC_INFO(IRQ_BASE
), MPIC_INFO(IRQ_STRIDE
) * mpic
->isu_size
);
1212 mpic
->isu_shift
= 1 + __ilog2(mpic
->isu_size
- 1);
1213 mpic
->isu_mask
= (1 << mpic
->isu_shift
) - 1;
1215 mpic
->irqhost
= irq_alloc_host(node
, IRQ_HOST_MAP_LINEAR
,
1216 isu_size
? isu_size
: mpic
->num_sources
,
1218 flags
& MPIC_LARGE_VECTORS
? 2048 : 256);
1219 if (mpic
->irqhost
== NULL
)
1222 mpic
->irqhost
->host_data
= mpic
;
1224 /* Display version */
1225 switch (greg_feature
& MPIC_GREG_FEATURE_VERSION_MASK
) {
1239 printk(KERN_INFO
"mpic: Setting up MPIC \"%s\" version %s at %llx,"
1241 name
, vers
, (unsigned long long)paddr
, mpic
->num_cpus
);
1242 printk(KERN_INFO
"mpic: ISU size: %d, shift: %d, mask: %x\n",
1243 mpic
->isu_size
, mpic
->isu_shift
, mpic
->isu_mask
);
1248 if (flags
& MPIC_PRIMARY
) {
1249 mpic_primary
= mpic
;
1250 irq_set_default_host(mpic
->irqhost
);
1256 void __init
mpic_assign_isu(struct mpic
*mpic
, unsigned int isu_num
,
1259 unsigned int isu_first
= isu_num
* mpic
->isu_size
;
1261 BUG_ON(isu_num
>= MPIC_MAX_ISU
);
1263 mpic_map(mpic
, mpic
->irqhost
->of_node
,
1264 paddr
, &mpic
->isus
[isu_num
], 0,
1265 MPIC_INFO(IRQ_STRIDE
) * mpic
->isu_size
);
1267 if ((isu_first
+ mpic
->isu_size
) > mpic
->num_sources
)
1268 mpic
->num_sources
= isu_first
+ mpic
->isu_size
;
1271 void __init
mpic_set_default_senses(struct mpic
*mpic
, u8
*senses
, int count
)
1273 mpic
->senses
= senses
;
1274 mpic
->senses_count
= count
;
1277 void __init
mpic_init(struct mpic
*mpic
)
1282 BUG_ON(mpic
->num_sources
== 0);
1284 printk(KERN_INFO
"mpic: Initializing for %d sources\n", mpic
->num_sources
);
1286 /* Set current processor priority to max */
1287 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI
), 0xf);
1289 /* Initialize timers: just disable them all */
1290 for (i
= 0; i
< 4; i
++) {
1291 mpic_write(mpic
->tmregs
,
1292 i
* MPIC_INFO(TIMER_STRIDE
) +
1293 MPIC_INFO(TIMER_DESTINATION
), 0);
1294 mpic_write(mpic
->tmregs
,
1295 i
* MPIC_INFO(TIMER_STRIDE
) +
1296 MPIC_INFO(TIMER_VECTOR_PRI
),
1298 (mpic
->timer_vecs
[0] + i
));
1301 /* Initialize IPIs to our reserved vectors and mark them disabled for now */
1302 mpic_test_broken_ipi(mpic
);
1303 for (i
= 0; i
< 4; i
++) {
1306 (10 << MPIC_VECPRI_PRIORITY_SHIFT
) |
1307 (mpic
->ipi_vecs
[0] + i
));
1310 /* Initialize interrupt sources */
1311 if (mpic
->irq_count
== 0)
1312 mpic
->irq_count
= mpic
->num_sources
;
1314 /* Do the HT PIC fixups on U3 broken mpic */
1315 DBG("MPIC flags: %x\n", mpic
->flags
);
1316 if ((mpic
->flags
& MPIC_U3_HT_IRQS
) && (mpic
->flags
& MPIC_PRIMARY
)) {
1317 mpic_scan_ht_pics(mpic
);
1318 mpic_u3msi_init(mpic
);
1321 mpic_pasemi_msi_init(mpic
);
1323 if (mpic
->flags
& MPIC_PRIMARY
)
1324 cpu
= hard_smp_processor_id();
1328 for (i
= 0; i
< mpic
->num_sources
; i
++) {
1329 /* start with vector = source number, and masked */
1330 u32 vecpri
= MPIC_VECPRI_MASK
| i
|
1331 (8 << MPIC_VECPRI_PRIORITY_SHIFT
);
1333 /* check if protected */
1334 if (mpic
->protected && test_bit(i
, mpic
->protected))
1337 mpic_irq_write(i
, MPIC_INFO(IRQ_VECTOR_PRI
), vecpri
);
1338 mpic_irq_write(i
, MPIC_INFO(IRQ_DESTINATION
), 1 << cpu
);
1341 /* Init spurious vector */
1342 mpic_write(mpic
->gregs
, MPIC_INFO(GREG_SPURIOUS
), mpic
->spurious_vec
);
1344 /* Disable 8259 passthrough, if supported */
1345 if (!(mpic
->flags
& MPIC_NO_PTHROU_DIS
))
1346 mpic_write(mpic
->gregs
, MPIC_INFO(GREG_GLOBAL_CONF_0
),
1347 mpic_read(mpic
->gregs
, MPIC_INFO(GREG_GLOBAL_CONF_0
))
1348 | MPIC_GREG_GCONF_8259_PTHROU_DIS
);
1350 if (mpic
->flags
& MPIC_NO_BIAS
)
1351 mpic_write(mpic
->gregs
, MPIC_INFO(GREG_GLOBAL_CONF_0
),
1352 mpic_read(mpic
->gregs
, MPIC_INFO(GREG_GLOBAL_CONF_0
))
1353 | MPIC_GREG_GCONF_NO_BIAS
);
1355 /* Set current processor priority to 0 */
1356 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI
), 0);
1359 /* allocate memory to save mpic state */
1360 mpic
->save_data
= kmalloc(mpic
->num_sources
* sizeof(*mpic
->save_data
),
1362 BUG_ON(mpic
->save_data
== NULL
);
1366 void __init
mpic_set_clk_ratio(struct mpic
*mpic
, u32 clock_ratio
)
1370 v
= mpic_read(mpic
->gregs
, MPIC_GREG_GLOBAL_CONF_1
);
1371 v
&= ~MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK
;
1372 v
|= MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(clock_ratio
);
1373 mpic_write(mpic
->gregs
, MPIC_GREG_GLOBAL_CONF_1
, v
);
1376 void __init
mpic_set_serial_int(struct mpic
*mpic
, int enable
)
1378 unsigned long flags
;
1381 raw_spin_lock_irqsave(&mpic_lock
, flags
);
1382 v
= mpic_read(mpic
->gregs
, MPIC_GREG_GLOBAL_CONF_1
);
1384 v
|= MPIC_GREG_GLOBAL_CONF_1_SIE
;
1386 v
&= ~MPIC_GREG_GLOBAL_CONF_1_SIE
;
1387 mpic_write(mpic
->gregs
, MPIC_GREG_GLOBAL_CONF_1
, v
);
1388 raw_spin_unlock_irqrestore(&mpic_lock
, flags
);
1391 void mpic_irq_set_priority(unsigned int irq
, unsigned int pri
)
1393 struct mpic
*mpic
= mpic_find(irq
);
1394 unsigned int src
= mpic_irq_to_hw(irq
);
1395 unsigned long flags
;
1401 raw_spin_lock_irqsave(&mpic_lock
, flags
);
1402 if (mpic_is_ipi(mpic
, irq
)) {
1403 reg
= mpic_ipi_read(src
- mpic
->ipi_vecs
[0]) &
1404 ~MPIC_VECPRI_PRIORITY_MASK
;
1405 mpic_ipi_write(src
- mpic
->ipi_vecs
[0],
1406 reg
| (pri
<< MPIC_VECPRI_PRIORITY_SHIFT
));
1408 reg
= mpic_irq_read(src
, MPIC_INFO(IRQ_VECTOR_PRI
))
1409 & ~MPIC_VECPRI_PRIORITY_MASK
;
1410 mpic_irq_write(src
, MPIC_INFO(IRQ_VECTOR_PRI
),
1411 reg
| (pri
<< MPIC_VECPRI_PRIORITY_SHIFT
));
1413 raw_spin_unlock_irqrestore(&mpic_lock
, flags
);
1416 void mpic_setup_this_cpu(void)
1419 struct mpic
*mpic
= mpic_primary
;
1420 unsigned long flags
;
1421 u32 msk
= 1 << hard_smp_processor_id();
1424 BUG_ON(mpic
== NULL
);
1426 DBG("%s: setup_this_cpu(%d)\n", mpic
->name
, hard_smp_processor_id());
1428 raw_spin_lock_irqsave(&mpic_lock
, flags
);
1430 /* let the mpic know we want intrs. default affinity is 0xffffffff
1431 * until changed via /proc. That's how it's done on x86. If we want
1432 * it differently, then we should make sure we also change the default
1433 * values of irq_desc[].affinity in irq.c.
1435 if (distribute_irqs
) {
1436 for (i
= 0; i
< mpic
->num_sources
; i
++)
1437 mpic_irq_write(i
, MPIC_INFO(IRQ_DESTINATION
),
1438 mpic_irq_read(i
, MPIC_INFO(IRQ_DESTINATION
)) | msk
);
1441 /* Set current processor priority to 0 */
1442 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI
), 0);
1444 raw_spin_unlock_irqrestore(&mpic_lock
, flags
);
1445 #endif /* CONFIG_SMP */
1448 int mpic_cpu_get_priority(void)
1450 struct mpic
*mpic
= mpic_primary
;
1452 return mpic_cpu_read(MPIC_INFO(CPU_CURRENT_TASK_PRI
));
1455 void mpic_cpu_set_priority(int prio
)
1457 struct mpic
*mpic
= mpic_primary
;
1459 prio
&= MPIC_CPU_TASKPRI_MASK
;
1460 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI
), prio
);
1463 void mpic_teardown_this_cpu(int secondary
)
1465 struct mpic
*mpic
= mpic_primary
;
1466 unsigned long flags
;
1467 u32 msk
= 1 << hard_smp_processor_id();
1470 BUG_ON(mpic
== NULL
);
1472 DBG("%s: teardown_this_cpu(%d)\n", mpic
->name
, hard_smp_processor_id());
1473 raw_spin_lock_irqsave(&mpic_lock
, flags
);
1475 /* let the mpic know we don't want intrs. */
1476 for (i
= 0; i
< mpic
->num_sources
; i
++)
1477 mpic_irq_write(i
, MPIC_INFO(IRQ_DESTINATION
),
1478 mpic_irq_read(i
, MPIC_INFO(IRQ_DESTINATION
)) & ~msk
);
1480 /* Set current processor priority to max */
1481 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI
), 0xf);
1482 /* We need to EOI the IPI since not all platforms reset the MPIC
1483 * on boot and new interrupts wouldn't get delivered otherwise.
1487 raw_spin_unlock_irqrestore(&mpic_lock
, flags
);
1491 static unsigned int _mpic_get_one_irq(struct mpic
*mpic
, int reg
)
1495 src
= mpic_cpu_read(reg
) & MPIC_INFO(VECPRI_VECTOR_MASK
);
1497 DBG("%s: get_one_irq(reg 0x%x): %d\n", mpic
->name
, reg
, src
);
1499 if (unlikely(src
== mpic
->spurious_vec
)) {
1500 if (mpic
->flags
& MPIC_SPV_EOI
)
1504 if (unlikely(mpic
->protected && test_bit(src
, mpic
->protected))) {
1505 if (printk_ratelimit())
1506 printk(KERN_WARNING
"%s: Got protected source %d !\n",
1507 mpic
->name
, (int)src
);
1512 return irq_linear_revmap(mpic
->irqhost
, src
);
1515 unsigned int mpic_get_one_irq(struct mpic
*mpic
)
1517 return _mpic_get_one_irq(mpic
, MPIC_INFO(CPU_INTACK
));
1520 unsigned int mpic_get_irq(void)
1522 struct mpic
*mpic
= mpic_primary
;
1524 BUG_ON(mpic
== NULL
);
1526 return mpic_get_one_irq(mpic
);
1529 unsigned int mpic_get_coreint_irq(void)
1532 struct mpic
*mpic
= mpic_primary
;
1535 BUG_ON(mpic
== NULL
);
1537 src
= mfspr(SPRN_EPR
);
1539 if (unlikely(src
== mpic
->spurious_vec
)) {
1540 if (mpic
->flags
& MPIC_SPV_EOI
)
1544 if (unlikely(mpic
->protected && test_bit(src
, mpic
->protected))) {
1545 if (printk_ratelimit())
1546 printk(KERN_WARNING
"%s: Got protected source %d !\n",
1547 mpic
->name
, (int)src
);
1551 return irq_linear_revmap(mpic
->irqhost
, src
);
1557 unsigned int mpic_get_mcirq(void)
1559 struct mpic
*mpic
= mpic_primary
;
1561 BUG_ON(mpic
== NULL
);
1563 return _mpic_get_one_irq(mpic
, MPIC_INFO(CPU_MCACK
));
1567 void mpic_request_ipis(void)
1569 struct mpic
*mpic
= mpic_primary
;
1571 BUG_ON(mpic
== NULL
);
1573 printk(KERN_INFO
"mpic: requesting IPIs...\n");
1575 for (i
= 0; i
< 4; i
++) {
1576 unsigned int vipi
= irq_create_mapping(mpic
->irqhost
,
1577 mpic
->ipi_vecs
[0] + i
);
1578 if (vipi
== NO_IRQ
) {
1579 printk(KERN_ERR
"Failed to map %s\n", smp_ipi_name
[i
]);
1582 smp_request_message_ipi(vipi
, i
);
1586 static void mpic_send_ipi(unsigned int ipi_no
, const struct cpumask
*cpu_mask
)
1588 struct mpic
*mpic
= mpic_primary
;
1590 BUG_ON(mpic
== NULL
);
1593 DBG("%s: send_ipi(ipi_no: %d)\n", mpic
->name
, ipi_no
);
1596 mpic_cpu_write(MPIC_INFO(CPU_IPI_DISPATCH_0
) +
1597 ipi_no
* MPIC_INFO(CPU_IPI_DISPATCH_STRIDE
),
1598 mpic_physmask(cpumask_bits(cpu_mask
)[0]));
1601 void smp_mpic_message_pass(int target
, int msg
)
1605 /* make sure we're sending something that translates to an IPI */
1606 if ((unsigned int)msg
> 3) {
1607 printk("SMP %d: smp_message_pass: unknown msg %d\n",
1608 smp_processor_id(), msg
);
1613 mpic_send_ipi(msg
, cpu_online_mask
);
1615 case MSG_ALL_BUT_SELF
:
1616 alloc_cpumask_var(&tmp
, GFP_NOWAIT
);
1617 cpumask_andnot(tmp
, cpu_online_mask
,
1618 cpumask_of(smp_processor_id()));
1619 mpic_send_ipi(msg
, tmp
);
1620 free_cpumask_var(tmp
);
1623 mpic_send_ipi(msg
, cpumask_of(target
));
1628 int __init
smp_mpic_probe(void)
1632 DBG("smp_mpic_probe()...\n");
1634 nr_cpus
= cpumask_weight(cpu_possible_mask
);
1636 DBG("nr_cpus: %d\n", nr_cpus
);
1639 mpic_request_ipis();
1644 void __devinit
smp_mpic_setup_cpu(int cpu
)
1646 mpic_setup_this_cpu();
1649 void mpic_reset_core(int cpu
)
1651 struct mpic
*mpic
= mpic_primary
;
1653 int cpuid
= get_hard_smp_processor_id(cpu
);
1655 /* Set target bit for core reset */
1656 pir
= mpic_read(mpic
->gregs
, MPIC_INFO(GREG_PROCESSOR_INIT
));
1657 pir
|= (1 << cpuid
);
1658 mpic_write(mpic
->gregs
, MPIC_INFO(GREG_PROCESSOR_INIT
), pir
);
1659 mpic_read(mpic
->gregs
, MPIC_INFO(GREG_PROCESSOR_INIT
));
1661 /* Restore target bit after reset complete */
1662 pir
&= ~(1 << cpuid
);
1663 mpic_write(mpic
->gregs
, MPIC_INFO(GREG_PROCESSOR_INIT
), pir
);
1664 mpic_read(mpic
->gregs
, MPIC_INFO(GREG_PROCESSOR_INIT
));
1666 #endif /* CONFIG_SMP */
1669 static int mpic_suspend(struct sys_device
*dev
, pm_message_t state
)
1671 struct mpic
*mpic
= container_of(dev
, struct mpic
, sysdev
);
1674 for (i
= 0; i
< mpic
->num_sources
; i
++) {
1675 mpic
->save_data
[i
].vecprio
=
1676 mpic_irq_read(i
, MPIC_INFO(IRQ_VECTOR_PRI
));
1677 mpic
->save_data
[i
].dest
=
1678 mpic_irq_read(i
, MPIC_INFO(IRQ_DESTINATION
));
1684 static int mpic_resume(struct sys_device
*dev
)
1686 struct mpic
*mpic
= container_of(dev
, struct mpic
, sysdev
);
1689 for (i
= 0; i
< mpic
->num_sources
; i
++) {
1690 mpic_irq_write(i
, MPIC_INFO(IRQ_VECTOR_PRI
),
1691 mpic
->save_data
[i
].vecprio
);
1692 mpic_irq_write(i
, MPIC_INFO(IRQ_DESTINATION
),
1693 mpic
->save_data
[i
].dest
);
1695 #ifdef CONFIG_MPIC_U3_HT_IRQS
1697 struct mpic_irq_fixup
*fixup
= &mpic
->fixups
[i
];
1700 /* we use the lowest bit in an inverted meaning */
1701 if ((mpic
->save_data
[i
].fixup_data
& 1) == 0)
1704 /* Enable and configure */
1705 writeb(0x10 + 2 * fixup
->index
, fixup
->base
+ 2);
1707 writel(mpic
->save_data
[i
].fixup_data
& ~1,
1712 } /* end for loop */
1718 static struct sysdev_class mpic_sysclass
= {
1720 .resume
= mpic_resume
,
1721 .suspend
= mpic_suspend
,
1726 static int mpic_init_sys(void)
1728 struct mpic
*mpic
= mpics
;
1731 error
= sysdev_class_register(&mpic_sysclass
);
1733 while (mpic
&& !error
) {
1734 mpic
->sysdev
.cls
= &mpic_sysclass
;
1735 mpic
->sysdev
.id
= id
++;
1736 error
= sysdev_register(&mpic
->sysdev
);
1742 device_initcall(mpic_init_sys
);