arch/powerpc/sysdev/ppc4xx_gpio.c

   1 /*
   2  * PPC4xx gpio driver
   3  *
   4  * Copyright (c) 2008 Harris Corporation
   5  * Copyright (c) 2008 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
   6  * Copyright (c) MontaVista Software, Inc. 2008.
   7  *
   8  * Author: Steve Falco <sfalco@harris.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2
  12  * as published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  22  */
  23
  24 #include <linux/kernel.h>
  25 #include <linux/init.h>
  26 #include <linux/spinlock.h>
  27 #include <linux/io.h>
  28 #include <linux/of.h>
  29 #include <linux/of_gpio.h>
  30 #include <linux/gpio/driver.h>
  31 #include <linux/types.h>
  32 #include <linux/slab.h>
  33
  34 #define GPIO_MASK(gpio)         (0x80000000 >> (gpio))
  35 #define GPIO_MASK2(gpio)        (0xc0000000 >> ((gpio) * 2))
  36
  37 /* Physical GPIO register layout */
  38 struct ppc4xx_gpio {
  39         __be32 or;
  40         __be32 tcr;
  41         __be32 osrl;
  42         __be32 osrh;
  43         __be32 tsrl;
  44         __be32 tsrh;
  45         __be32 odr;
  46         __be32 ir;
  47         __be32 rr1;
  48         __be32 rr2;
  49         __be32 rr3;
  50         __be32 reserved1;
  51         __be32 isr1l;
  52         __be32 isr1h;
  53         __be32 isr2l;
  54         __be32 isr2h;
  55         __be32 isr3l;
  56         __be32 isr3h;
  57 };
  58
  59 struct ppc4xx_gpio_chip {
  60         struct of_mm_gpio_chip mm_gc;
  61         spinlock_t lock;
  62 };
  63
  64 /*
  65  * GPIO LIB API implementation for GPIOs
  66  *
  67  * There are a maximum of 32 gpios in each gpio controller.
  68  */
  69
  70 static int ppc4xx_gpio_get(struct gpio_chip *gc, unsigned int gpio)
  71 {
  72         struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
  73         struct ppc4xx_gpio __iomem *regs = mm_gc->regs;
  74
  75         return !!(in_be32(&regs->ir) & GPIO_MASK(gpio));
  76 }
  77
  78 static inline void
  79 __ppc4xx_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
  80 {
  81         struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
  82         struct ppc4xx_gpio __iomem *regs = mm_gc->regs;
  83
  84         if (val)
  85                 setbits32(&regs->or, GPIO_MASK(gpio));
  86         else
  87                 clrbits32(&regs->or, GPIO_MASK(gpio));
  88 }
  89
  90 static void
  91 ppc4xx_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
  92 {
  93         struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
  94         struct ppc4xx_gpio_chip *chip = gpiochip_get_data(gc);
  95         unsigned long flags;
  96
  97         spin_lock_irqsave(&chip->lock, flags);
  98
  99         __ppc4xx_gpio_set(gc, gpio, val);
 100
 101         spin_unlock_irqrestore(&chip->lock, flags);
 102
 103         pr_debug("%s: gpio: %d val: %d\n", __func__, gpio, val);
 104 }
 105
 106 static int ppc4xx_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
 107 {
 108         struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
 109         struct ppc4xx_gpio_chip *chip = gpiochip_get_data(gc);
 110         struct ppc4xx_gpio __iomem *regs = mm_gc->regs;
 111         unsigned long flags;
 112
 113         spin_lock_irqsave(&chip->lock, flags);
 114
 115         /* Disable open-drain function */
 116         clrbits32(&regs->odr, GPIO_MASK(gpio));
 117
 118         /* Float the pin */
 119         clrbits32(&regs->tcr, GPIO_MASK(gpio));
 120
 121         /* Bits 0-15 use TSRL/OSRL, bits 16-31 use TSRH/OSRH */
 122         if (gpio < 16) {
 123                 clrbits32(&regs->osrl, GPIO_MASK2(gpio));
 124                 clrbits32(&regs->tsrl, GPIO_MASK2(gpio));
 125         } else {
 126                 clrbits32(&regs->osrh, GPIO_MASK2(gpio));
 127                 clrbits32(&regs->tsrh, GPIO_MASK2(gpio));
 128         }
 129
 130         spin_unlock_irqrestore(&chip->lock, flags);
 131
 132         return 0;
 133 }
 134
 135 static int
 136 ppc4xx_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
 137 {
 138         struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
 139         struct ppc4xx_gpio_chip *chip = gpiochip_get_data(gc);
 140         struct ppc4xx_gpio __iomem *regs = mm_gc->regs;
 141         unsigned long flags;
 142
 143         spin_lock_irqsave(&chip->lock, flags);
 144
 145         /* First set initial value */
 146         __ppc4xx_gpio_set(gc, gpio, val);
 147
 148         /* Disable open-drain function */
 149         clrbits32(&regs->odr, GPIO_MASK(gpio));
 150
 151         /* Drive the pin */
 152         setbits32(&regs->tcr, GPIO_MASK(gpio));
 153
 154         /* Bits 0-15 use TSRL, bits 16-31 use TSRH */
 155         if (gpio < 16) {
 156                 clrbits32(&regs->osrl, GPIO_MASK2(gpio));
 157                 clrbits32(&regs->tsrl, GPIO_MASK2(gpio));
 158         } else {
 159                 clrbits32(&regs->osrh, GPIO_MASK2(gpio));
 160                 clrbits32(&regs->tsrh, GPIO_MASK2(gpio));
 161         }
 162
 163         spin_unlock_irqrestore(&chip->lock, flags);
 164
 165         pr_debug("%s: gpio: %d val: %d\n", __func__, gpio, val);
 166
 167         return 0;
 168 }
 169
 170 static int __init ppc4xx_add_gpiochips(void)
 171 {
 172         struct device_node *np;
 173
 174         for_each_compatible_node(np, NULL, "ibm,ppc4xx-gpio") {
 175                 int ret;
 176                 struct ppc4xx_gpio_chip *ppc4xx_gc;
 177                 struct of_mm_gpio_chip *mm_gc;
 178                 struct gpio_chip *gc;
 179
 180                 ppc4xx_gc = kzalloc(sizeof(*ppc4xx_gc), GFP_KERNEL);
 181                 if (!ppc4xx_gc) {
 182                         ret = -ENOMEM;
 183                         goto err;
 184                 }
 185
 186                 spin_lock_init(&ppc4xx_gc->lock);
 187
 188                 mm_gc = &ppc4xx_gc->mm_gc;
 189                 gc = &mm_gc->gc;
 190
 191                 gc->ngpio = 32;
 192                 gc->direction_input = ppc4xx_gpio_dir_in;
 193                 gc->direction_output = ppc4xx_gpio_dir_out;
 194                 gc->get = ppc4xx_gpio_get;
 195                 gc->set = ppc4xx_gpio_set;
 196
 197                 ret = of_mm_gpiochip_add_data(np, mm_gc, ppc4xx_gc);
 198                 if (ret)
 199                         goto err;
 200                 continue;
 201 err:
 202                 pr_err("%s: registration failed with status %d\n",
 203                        np->full_name, ret);
 204                 kfree(ppc4xx_gc);
 205                 /* try others anyway */
 206         }
 207         return 0;
 208 }
 209 arch_initcall(ppc4xx_add_gpiochips);