2 * PCI / PCI-X / PCI-Express support for 4xx parts
4 * Copyright 2007 Ben. Herrenschmidt <benh@kernel.crashing.org>, IBM Corp.
6 * Most PCI Express code is coming from Stefan Roese implementation for
7 * arch/ppc in the Denx tree, slightly reworked by me.
9 * Copyright 2007 DENX Software Engineering, Stefan Roese <sr@denx.de>
11 * Some of that comes itself from a previous implementation for 440SPE only
14 * Copyright (c) 2005 Cisco Systems. All rights reserved.
15 * Roland Dreier <rolandd@cisco.com>
21 #include <linux/kernel.h>
22 #include <linux/pci.h>
23 #include <linux/init.h>
25 #include <linux/bootmem.h>
26 #include <linux/delay.h>
29 #include <asm/pci-bridge.h>
30 #include <asm/machdep.h>
32 #include <asm/dcr-regs.h>
33 #include <mm/mmu_decl.h>
35 #include "ppc4xx_pci.h"
37 static int dma_offset_set
;
39 #define U64_TO_U32_LOW(val) ((u32)((val) & 0x00000000ffffffffULL))
40 #define U64_TO_U32_HIGH(val) ((u32)((val) >> 32))
42 #define RES_TO_U32_LOW(val) \
43 ((sizeof(resource_size_t) > sizeof(u32)) ? U64_TO_U32_LOW(val) : (val))
44 #define RES_TO_U32_HIGH(val) \
45 ((sizeof(resource_size_t) > sizeof(u32)) ? U64_TO_U32_HIGH(val) : (0))
47 static inline int ppc440spe_revA(void)
49 /* Catch both 440SPe variants, with and without RAID6 support */
50 if ((mfspr(SPRN_PVR
) & 0xffefffff) == 0x53421890)
56 static void fixup_ppc4xx_pci_bridge(struct pci_dev
*dev
)
58 struct pci_controller
*hose
;
61 if (dev
->devfn
!= 0 || dev
->bus
->self
!= NULL
)
64 hose
= pci_bus_to_host(dev
->bus
);
68 if (!of_device_is_compatible(hose
->dn
, "ibm,plb-pciex") &&
69 !of_device_is_compatible(hose
->dn
, "ibm,plb-pcix") &&
70 !of_device_is_compatible(hose
->dn
, "ibm,plb-pci"))
73 if (of_device_is_compatible(hose
->dn
, "ibm,plb440epx-pci") ||
74 of_device_is_compatible(hose
->dn
, "ibm,plb440grx-pci")) {
75 hose
->indirect_type
|= PPC_INDIRECT_TYPE_BROKEN_MRM
;
78 /* Hide the PCI host BARs from the kernel as their content doesn't
79 * fit well in the resource management
81 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++) {
82 dev
->resource
[i
].start
= dev
->resource
[i
].end
= 0;
83 dev
->resource
[i
].flags
= 0;
86 printk(KERN_INFO
"PCI: Hiding 4xx host bridge resources %s\n",
89 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID
, PCI_ANY_ID
, fixup_ppc4xx_pci_bridge
);
91 static int __init
ppc4xx_parse_dma_ranges(struct pci_controller
*hose
,
98 int pna
= of_n_addr_cells(hose
->dn
);
105 res
->flags
= IORESOURCE_MEM
| IORESOURCE_PREFETCH
;
107 /* Get dma-ranges property */
108 ranges
= of_get_property(hose
->dn
, "dma-ranges", &rlen
);
113 while ((rlen
-= np
* 4) >= 0) {
114 u32 pci_space
= ranges
[0];
115 u64 pci_addr
= of_read_number(ranges
+ 1, 2);
116 u64 cpu_addr
= of_translate_dma_address(hose
->dn
, ranges
+ 3);
117 size
= of_read_number(ranges
+ pna
+ 3, 2);
119 if (cpu_addr
== OF_BAD_ADDR
|| size
== 0)
122 /* We only care about memory */
123 if ((pci_space
& 0x03000000) != 0x02000000)
126 /* We currently only support memory at 0, and pci_addr
127 * within 32 bits space
129 if (cpu_addr
!= 0 || pci_addr
> 0xffffffff) {
130 printk(KERN_WARNING
"%s: Ignored unsupported dma range"
131 " 0x%016llx...0x%016llx -> 0x%016llx\n",
133 pci_addr
, pci_addr
+ size
- 1, cpu_addr
);
137 /* Check if not prefetchable */
138 if (!(pci_space
& 0x40000000))
139 res
->flags
&= ~IORESOURCE_PREFETCH
;
143 res
->start
= pci_addr
;
144 /* Beware of 32 bits resources */
145 if (sizeof(resource_size_t
) == sizeof(u32
) &&
146 (pci_addr
+ size
) > 0x100000000ull
)
147 res
->end
= 0xffffffff;
149 res
->end
= res
->start
+ size
- 1;
153 /* We only support one global DMA offset */
154 if (dma_offset_set
&& pci_dram_offset
!= res
->start
) {
155 printk(KERN_ERR
"%s: dma-ranges(s) mismatch\n",
156 hose
->dn
->full_name
);
160 /* Check that we can fit all of memory as we don't support
163 if (size
< total_memory
) {
164 printk(KERN_ERR
"%s: dma-ranges too small "
165 "(size=%llx total_memory=%llx)\n",
166 hose
->dn
->full_name
, size
, (u64
)total_memory
);
170 /* Check we are a power of 2 size and that base is a multiple of size*/
171 if ((size
& (size
- 1)) != 0 ||
172 (res
->start
& (size
- 1)) != 0) {
173 printk(KERN_ERR
"%s: dma-ranges unaligned\n",
174 hose
->dn
->full_name
);
178 /* Check that we are fully contained within 32 bits space */
179 if (res
->end
> 0xffffffff) {
180 printk(KERN_ERR
"%s: dma-ranges outside of 32 bits space\n",
181 hose
->dn
->full_name
);
186 pci_dram_offset
= res
->start
;
188 printk(KERN_INFO
"4xx PCI DMA offset set to 0x%08lx\n",
197 static int __init
ppc4xx_setup_one_pci_PMM(struct pci_controller
*hose
,
205 u32 ma
, pcila
, pciha
;
207 if ((plb_addr
+ size
) > 0xffffffffull
|| !is_power_of_2(size
) ||
208 size
< 0x1000 || (plb_addr
& (size
- 1)) != 0) {
209 printk(KERN_WARNING
"%s: Resource out of range\n",
210 hose
->dn
->full_name
);
213 ma
= (0xffffffffu
<< ilog2(size
)) | 1;
214 if (flags
& IORESOURCE_PREFETCH
)
217 pciha
= RES_TO_U32_HIGH(pci_addr
);
218 pcila
= RES_TO_U32_LOW(pci_addr
);
220 writel(plb_addr
, reg
+ PCIL0_PMM0LA
+ (0x10 * index
));
221 writel(pcila
, reg
+ PCIL0_PMM0PCILA
+ (0x10 * index
));
222 writel(pciha
, reg
+ PCIL0_PMM0PCIHA
+ (0x10 * index
));
223 writel(ma
, reg
+ PCIL0_PMM0MA
+ (0x10 * index
));
228 static void __init
ppc4xx_configure_pci_PMMs(struct pci_controller
*hose
,
231 int i
, j
, found_isa_hole
= 0;
233 /* Setup outbound memory windows */
234 for (i
= j
= 0; i
< 3; i
++) {
235 struct resource
*res
= &hose
->mem_resources
[i
];
237 /* we only care about memory windows */
238 if (!(res
->flags
& IORESOURCE_MEM
))
241 printk(KERN_WARNING
"%s: Too many ranges\n",
242 hose
->dn
->full_name
);
246 /* Configure the resource */
247 if (ppc4xx_setup_one_pci_PMM(hose
, reg
,
249 res
->start
- hose
->pci_mem_offset
,
250 res
->end
+ 1 - res
->start
,
255 /* If the resource PCI address is 0 then we have our
258 if (res
->start
== hose
->pci_mem_offset
)
263 /* Handle ISA memory hole if not already covered */
264 if (j
<= 2 && !found_isa_hole
&& hose
->isa_mem_size
)
265 if (ppc4xx_setup_one_pci_PMM(hose
, reg
, hose
->isa_mem_phys
, 0,
266 hose
->isa_mem_size
, 0, j
) == 0)
267 printk(KERN_INFO
"%s: Legacy ISA memory support enabled\n",
268 hose
->dn
->full_name
);
271 static void __init
ppc4xx_configure_pci_PTMs(struct pci_controller
*hose
,
273 const struct resource
*res
)
275 resource_size_t size
= res
->end
- res
->start
+ 1;
278 /* Calculate window size */
279 sa
= (0xffffffffu
<< ilog2(size
)) | 1;
282 /* RAM is always at 0 local for now */
283 writel(0, reg
+ PCIL0_PTM1LA
);
284 writel(sa
, reg
+ PCIL0_PTM1MS
);
286 /* Map on PCI side */
287 early_write_config_dword(hose
, hose
->first_busno
, 0,
288 PCI_BASE_ADDRESS_1
, res
->start
);
289 early_write_config_dword(hose
, hose
->first_busno
, 0,
290 PCI_BASE_ADDRESS_2
, 0x00000000);
291 early_write_config_word(hose
, hose
->first_busno
, 0,
292 PCI_COMMAND
, 0x0006);
295 static void __init
ppc4xx_probe_pci_bridge(struct device_node
*np
)
298 struct resource rsrc_cfg
;
299 struct resource rsrc_reg
;
300 struct resource dma_window
;
301 struct pci_controller
*hose
= NULL
;
302 void __iomem
*reg
= NULL
;
303 const int *bus_range
;
306 /* Check if device is enabled */
307 if (!of_device_is_available(np
)) {
308 printk(KERN_INFO
"%s: Port disabled via device-tree\n",
313 /* Fetch config space registers address */
314 if (of_address_to_resource(np
, 0, &rsrc_cfg
)) {
315 printk(KERN_ERR
"%s: Can't get PCI config register base !",
319 /* Fetch host bridge internal registers address */
320 if (of_address_to_resource(np
, 3, &rsrc_reg
)) {
321 printk(KERN_ERR
"%s: Can't get PCI internal register base !",
326 /* Check if primary bridge */
327 if (of_get_property(np
, "primary", NULL
))
330 /* Get bus range if any */
331 bus_range
= of_get_property(np
, "bus-range", NULL
);
334 reg
= ioremap(rsrc_reg
.start
, rsrc_reg
.end
+ 1 - rsrc_reg
.start
);
336 printk(KERN_ERR
"%s: Can't map registers !", np
->full_name
);
340 /* Allocate the host controller data structure */
341 hose
= pcibios_alloc_controller(np
);
345 hose
->first_busno
= bus_range
? bus_range
[0] : 0x0;
346 hose
->last_busno
= bus_range
? bus_range
[1] : 0xff;
348 /* Setup config space */
349 setup_indirect_pci(hose
, rsrc_cfg
.start
, rsrc_cfg
.start
+ 0x4, 0);
351 /* Disable all windows */
352 writel(0, reg
+ PCIL0_PMM0MA
);
353 writel(0, reg
+ PCIL0_PMM1MA
);
354 writel(0, reg
+ PCIL0_PMM2MA
);
355 writel(0, reg
+ PCIL0_PTM1MS
);
356 writel(0, reg
+ PCIL0_PTM2MS
);
358 /* Parse outbound mapping resources */
359 pci_process_bridge_OF_ranges(hose
, np
, primary
);
361 /* Parse inbound mapping resources */
362 if (ppc4xx_parse_dma_ranges(hose
, reg
, &dma_window
) != 0)
365 /* Configure outbound ranges POMs */
366 ppc4xx_configure_pci_PMMs(hose
, reg
);
368 /* Configure inbound ranges PIMs */
369 ppc4xx_configure_pci_PTMs(hose
, reg
, &dma_window
);
371 /* We don't need the registers anymore */
377 pcibios_free_controller(hose
);
386 static int __init
ppc4xx_setup_one_pcix_POM(struct pci_controller
*hose
,
394 u32 lah
, lal
, pciah
, pcial
, sa
;
396 if (!is_power_of_2(size
) || size
< 0x1000 ||
397 (plb_addr
& (size
- 1)) != 0) {
398 printk(KERN_WARNING
"%s: Resource out of range\n",
399 hose
->dn
->full_name
);
403 /* Calculate register values */
404 lah
= RES_TO_U32_HIGH(plb_addr
);
405 lal
= RES_TO_U32_LOW(plb_addr
);
406 pciah
= RES_TO_U32_HIGH(pci_addr
);
407 pcial
= RES_TO_U32_LOW(pci_addr
);
408 sa
= (0xffffffffu
<< ilog2(size
)) | 0x1;
410 /* Program register values */
412 writel(lah
, reg
+ PCIX0_POM0LAH
);
413 writel(lal
, reg
+ PCIX0_POM0LAL
);
414 writel(pciah
, reg
+ PCIX0_POM0PCIAH
);
415 writel(pcial
, reg
+ PCIX0_POM0PCIAL
);
416 writel(sa
, reg
+ PCIX0_POM0SA
);
418 writel(lah
, reg
+ PCIX0_POM1LAH
);
419 writel(lal
, reg
+ PCIX0_POM1LAL
);
420 writel(pciah
, reg
+ PCIX0_POM1PCIAH
);
421 writel(pcial
, reg
+ PCIX0_POM1PCIAL
);
422 writel(sa
, reg
+ PCIX0_POM1SA
);
428 static void __init
ppc4xx_configure_pcix_POMs(struct pci_controller
*hose
,
431 int i
, j
, found_isa_hole
= 0;
433 /* Setup outbound memory windows */
434 for (i
= j
= 0; i
< 3; i
++) {
435 struct resource
*res
= &hose
->mem_resources
[i
];
437 /* we only care about memory windows */
438 if (!(res
->flags
& IORESOURCE_MEM
))
441 printk(KERN_WARNING
"%s: Too many ranges\n",
442 hose
->dn
->full_name
);
446 /* Configure the resource */
447 if (ppc4xx_setup_one_pcix_POM(hose
, reg
,
449 res
->start
- hose
->pci_mem_offset
,
450 res
->end
+ 1 - res
->start
,
455 /* If the resource PCI address is 0 then we have our
458 if (res
->start
== hose
->pci_mem_offset
)
463 /* Handle ISA memory hole if not already covered */
464 if (j
<= 1 && !found_isa_hole
&& hose
->isa_mem_size
)
465 if (ppc4xx_setup_one_pcix_POM(hose
, reg
, hose
->isa_mem_phys
, 0,
466 hose
->isa_mem_size
, 0, j
) == 0)
467 printk(KERN_INFO
"%s: Legacy ISA memory support enabled\n",
468 hose
->dn
->full_name
);
471 static void __init
ppc4xx_configure_pcix_PIMs(struct pci_controller
*hose
,
473 const struct resource
*res
,
477 resource_size_t size
= res
->end
- res
->start
+ 1;
480 /* RAM is always at 0 */
481 writel(0x00000000, reg
+ PCIX0_PIM0LAH
);
482 writel(0x00000000, reg
+ PCIX0_PIM0LAL
);
484 /* Calculate window size */
485 sa
= (0xffffffffu
<< ilog2(size
)) | 1;
487 if (res
->flags
& IORESOURCE_PREFETCH
)
491 writel(sa
, reg
+ PCIX0_PIM0SA
);
493 writel(0xffffffff, reg
+ PCIX0_PIM0SAH
);
495 /* Map on PCI side */
496 writel(0x00000000, reg
+ PCIX0_BAR0H
);
497 writel(res
->start
, reg
+ PCIX0_BAR0L
);
498 writew(0x0006, reg
+ PCIX0_COMMAND
);
501 static void __init
ppc4xx_probe_pcix_bridge(struct device_node
*np
)
503 struct resource rsrc_cfg
;
504 struct resource rsrc_reg
;
505 struct resource dma_window
;
506 struct pci_controller
*hose
= NULL
;
507 void __iomem
*reg
= NULL
;
508 const int *bus_range
;
509 int big_pim
= 0, msi
= 0, primary
= 0;
511 /* Fetch config space registers address */
512 if (of_address_to_resource(np
, 0, &rsrc_cfg
)) {
513 printk(KERN_ERR
"%s:Can't get PCI-X config register base !",
517 /* Fetch host bridge internal registers address */
518 if (of_address_to_resource(np
, 3, &rsrc_reg
)) {
519 printk(KERN_ERR
"%s: Can't get PCI-X internal register base !",
524 /* Check if it supports large PIMs (440GX) */
525 if (of_get_property(np
, "large-inbound-windows", NULL
))
528 /* Check if we should enable MSIs inbound hole */
529 if (of_get_property(np
, "enable-msi-hole", NULL
))
532 /* Check if primary bridge */
533 if (of_get_property(np
, "primary", NULL
))
536 /* Get bus range if any */
537 bus_range
= of_get_property(np
, "bus-range", NULL
);
540 reg
= ioremap(rsrc_reg
.start
, rsrc_reg
.end
+ 1 - rsrc_reg
.start
);
542 printk(KERN_ERR
"%s: Can't map registers !", np
->full_name
);
546 /* Allocate the host controller data structure */
547 hose
= pcibios_alloc_controller(np
);
551 hose
->first_busno
= bus_range
? bus_range
[0] : 0x0;
552 hose
->last_busno
= bus_range
? bus_range
[1] : 0xff;
554 /* Setup config space */
555 setup_indirect_pci(hose
, rsrc_cfg
.start
, rsrc_cfg
.start
+ 0x4, 0);
557 /* Disable all windows */
558 writel(0, reg
+ PCIX0_POM0SA
);
559 writel(0, reg
+ PCIX0_POM1SA
);
560 writel(0, reg
+ PCIX0_POM2SA
);
561 writel(0, reg
+ PCIX0_PIM0SA
);
562 writel(0, reg
+ PCIX0_PIM1SA
);
563 writel(0, reg
+ PCIX0_PIM2SA
);
565 writel(0, reg
+ PCIX0_PIM0SAH
);
566 writel(0, reg
+ PCIX0_PIM2SAH
);
569 /* Parse outbound mapping resources */
570 pci_process_bridge_OF_ranges(hose
, np
, primary
);
572 /* Parse inbound mapping resources */
573 if (ppc4xx_parse_dma_ranges(hose
, reg
, &dma_window
) != 0)
576 /* Configure outbound ranges POMs */
577 ppc4xx_configure_pcix_POMs(hose
, reg
);
579 /* Configure inbound ranges PIMs */
580 ppc4xx_configure_pcix_PIMs(hose
, reg
, &dma_window
, big_pim
, msi
);
582 /* We don't need the registers anymore */
588 pcibios_free_controller(hose
);
593 #ifdef CONFIG_PPC4xx_PCI_EXPRESS
596 * 4xx PCI-Express part
598 * We support 3 parts currently based on the compatible property:
600 * ibm,plb-pciex-440spe
601 * ibm,plb-pciex-405ex
602 * ibm,plb-pciex-460ex
604 * Anything else will be rejected for now as they are all subtly
605 * different unfortunately.
609 #define MAX_PCIE_BUS_MAPPED 0x40
611 struct ppc4xx_pciex_port
613 struct pci_controller
*hose
;
614 struct device_node
*node
;
619 unsigned int sdr_base
;
621 struct resource cfg_space
;
622 struct resource utl_regs
;
623 void __iomem
*utl_base
;
626 static struct ppc4xx_pciex_port
*ppc4xx_pciex_ports
;
627 static unsigned int ppc4xx_pciex_port_count
;
629 struct ppc4xx_pciex_hwops
631 int (*core_init
)(struct device_node
*np
);
632 int (*port_init_hw
)(struct ppc4xx_pciex_port
*port
);
633 int (*setup_utl
)(struct ppc4xx_pciex_port
*port
);
636 static struct ppc4xx_pciex_hwops
*ppc4xx_pciex_hwops
;
640 /* Check various reset bits of the 440SPe PCIe core */
641 static int __init
ppc440spe_pciex_check_reset(struct device_node
*np
)
643 u32 valPE0
, valPE1
, valPE2
;
646 /* SDR0_PEGPLLLCT1 reset */
647 if (!(mfdcri(SDR0
, PESDR0_PLLLCT1
) & 0x01000000)) {
649 * the PCIe core was probably already initialised
650 * by firmware - let's re-reset RCSSET regs
652 * -- Shouldn't we also re-reset the whole thing ? -- BenH
654 pr_debug("PCIE: SDR0_PLLLCT1 already reset.\n");
655 mtdcri(SDR0
, PESDR0_440SPE_RCSSET
, 0x01010000);
656 mtdcri(SDR0
, PESDR1_440SPE_RCSSET
, 0x01010000);
657 mtdcri(SDR0
, PESDR2_440SPE_RCSSET
, 0x01010000);
660 valPE0
= mfdcri(SDR0
, PESDR0_440SPE_RCSSET
);
661 valPE1
= mfdcri(SDR0
, PESDR1_440SPE_RCSSET
);
662 valPE2
= mfdcri(SDR0
, PESDR2_440SPE_RCSSET
);
664 /* SDR0_PExRCSSET rstgu */
665 if (!(valPE0
& 0x01000000) ||
666 !(valPE1
& 0x01000000) ||
667 !(valPE2
& 0x01000000)) {
668 printk(KERN_INFO
"PCIE: SDR0_PExRCSSET rstgu error\n");
672 /* SDR0_PExRCSSET rstdl */
673 if (!(valPE0
& 0x00010000) ||
674 !(valPE1
& 0x00010000) ||
675 !(valPE2
& 0x00010000)) {
676 printk(KERN_INFO
"PCIE: SDR0_PExRCSSET rstdl error\n");
680 /* SDR0_PExRCSSET rstpyn */
681 if ((valPE0
& 0x00001000) ||
682 (valPE1
& 0x00001000) ||
683 (valPE2
& 0x00001000)) {
684 printk(KERN_INFO
"PCIE: SDR0_PExRCSSET rstpyn error\n");
688 /* SDR0_PExRCSSET hldplb */
689 if ((valPE0
& 0x10000000) ||
690 (valPE1
& 0x10000000) ||
691 (valPE2
& 0x10000000)) {
692 printk(KERN_INFO
"PCIE: SDR0_PExRCSSET hldplb error\n");
696 /* SDR0_PExRCSSET rdy */
697 if ((valPE0
& 0x00100000) ||
698 (valPE1
& 0x00100000) ||
699 (valPE2
& 0x00100000)) {
700 printk(KERN_INFO
"PCIE: SDR0_PExRCSSET rdy error\n");
704 /* SDR0_PExRCSSET shutdown */
705 if ((valPE0
& 0x00000100) ||
706 (valPE1
& 0x00000100) ||
707 (valPE2
& 0x00000100)) {
708 printk(KERN_INFO
"PCIE: SDR0_PExRCSSET shutdown error\n");
715 /* Global PCIe core initializations for 440SPe core */
716 static int __init
ppc440spe_pciex_core_init(struct device_node
*np
)
720 /* Set PLL clock receiver to LVPECL */
721 dcri_clrset(SDR0
, PESDR0_PLLLCT1
, 0, 1 << 28);
723 /* Shouldn't we do all the calibration stuff etc... here ? */
724 if (ppc440spe_pciex_check_reset(np
))
727 if (!(mfdcri(SDR0
, PESDR0_PLLLCT2
) & 0x10000)) {
728 printk(KERN_INFO
"PCIE: PESDR_PLLCT2 resistance calibration "
730 mfdcri(SDR0
, PESDR0_PLLLCT2
));
734 /* De-assert reset of PCIe PLL, wait for lock */
735 dcri_clrset(SDR0
, PESDR0_PLLLCT1
, 1 << 24, 0);
739 if (!(mfdcri(SDR0
, PESDR0_PLLLCT3
) & 0x10000000)) {
746 printk(KERN_INFO
"PCIE: VCO output not locked\n");
750 pr_debug("PCIE initialization OK\n");
755 static int ppc440spe_pciex_init_port_hw(struct ppc4xx_pciex_port
*port
)
760 val
= PTYPE_LEGACY_ENDPOINT
<< 20;
762 val
= PTYPE_ROOT_PORT
<< 20;
764 if (port
->index
== 0)
765 val
|= LNKW_X8
<< 12;
767 val
|= LNKW_X4
<< 12;
769 mtdcri(SDR0
, port
->sdr_base
+ PESDRn_DLPSET
, val
);
770 mtdcri(SDR0
, port
->sdr_base
+ PESDRn_UTLSET1
, 0x20222222);
771 if (ppc440spe_revA())
772 mtdcri(SDR0
, port
->sdr_base
+ PESDRn_UTLSET2
, 0x11000000);
773 mtdcri(SDR0
, port
->sdr_base
+ PESDRn_440SPE_HSSL0SET1
, 0x35000000);
774 mtdcri(SDR0
, port
->sdr_base
+ PESDRn_440SPE_HSSL1SET1
, 0x35000000);
775 mtdcri(SDR0
, port
->sdr_base
+ PESDRn_440SPE_HSSL2SET1
, 0x35000000);
776 mtdcri(SDR0
, port
->sdr_base
+ PESDRn_440SPE_HSSL3SET1
, 0x35000000);
777 if (port
->index
== 0) {
778 mtdcri(SDR0
, port
->sdr_base
+ PESDRn_440SPE_HSSL4SET1
,
780 mtdcri(SDR0
, port
->sdr_base
+ PESDRn_440SPE_HSSL5SET1
,
782 mtdcri(SDR0
, port
->sdr_base
+ PESDRn_440SPE_HSSL6SET1
,
784 mtdcri(SDR0
, port
->sdr_base
+ PESDRn_440SPE_HSSL7SET1
,
787 dcri_clrset(SDR0
, port
->sdr_base
+ PESDRn_RCSSET
,
788 (1 << 24) | (1 << 16), 1 << 12);
793 static int ppc440speA_pciex_init_port_hw(struct ppc4xx_pciex_port
*port
)
795 return ppc440spe_pciex_init_port_hw(port
);
798 static int ppc440speB_pciex_init_port_hw(struct ppc4xx_pciex_port
*port
)
800 int rc
= ppc440spe_pciex_init_port_hw(port
);
807 static int ppc440speA_pciex_init_utl(struct ppc4xx_pciex_port
*port
)
809 /* XXX Check what that value means... I hate magic */
810 dcr_write(port
->dcrs
, DCRO_PEGPL_SPECIAL
, 0x68782800);
813 * Set buffer allocations and then assert VRB and TXE.
815 out_be32(port
->utl_base
+ PEUTL_OUTTR
, 0x08000000);
816 out_be32(port
->utl_base
+ PEUTL_INTR
, 0x02000000);
817 out_be32(port
->utl_base
+ PEUTL_OPDBSZ
, 0x10000000);
818 out_be32(port
->utl_base
+ PEUTL_PBBSZ
, 0x53000000);
819 out_be32(port
->utl_base
+ PEUTL_IPHBSZ
, 0x08000000);
820 out_be32(port
->utl_base
+ PEUTL_IPDBSZ
, 0x10000000);
821 out_be32(port
->utl_base
+ PEUTL_RCIRQEN
, 0x00f00000);
822 out_be32(port
->utl_base
+ PEUTL_PCTL
, 0x80800066);
827 static int ppc440speB_pciex_init_utl(struct ppc4xx_pciex_port
*port
)
829 /* Report CRS to the operating system */
830 out_be32(port
->utl_base
+ PEUTL_PBCTL
, 0x08000000);
835 static struct ppc4xx_pciex_hwops ppc440speA_pcie_hwops __initdata
=
837 .core_init
= ppc440spe_pciex_core_init
,
838 .port_init_hw
= ppc440speA_pciex_init_port_hw
,
839 .setup_utl
= ppc440speA_pciex_init_utl
,
842 static struct ppc4xx_pciex_hwops ppc440speB_pcie_hwops __initdata
=
844 .core_init
= ppc440spe_pciex_core_init
,
845 .port_init_hw
= ppc440speB_pciex_init_port_hw
,
846 .setup_utl
= ppc440speB_pciex_init_utl
,
849 static int __init
ppc460ex_pciex_core_init(struct device_node
*np
)
851 /* Nothing to do, return 2 ports */
855 static int ppc460ex_pciex_init_port_hw(struct ppc4xx_pciex_port
*port
)
861 val
= PTYPE_LEGACY_ENDPOINT
<< 20;
863 val
= PTYPE_ROOT_PORT
<< 20;
865 if (port
->index
== 0) {
866 val
|= LNKW_X1
<< 12;
867 utlset1
= 0x20000000;
869 val
|= LNKW_X4
<< 12;
870 utlset1
= 0x20101101;
873 mtdcri(SDR0
, port
->sdr_base
+ PESDRn_DLPSET
, val
);
874 mtdcri(SDR0
, port
->sdr_base
+ PESDRn_UTLSET1
, utlset1
);
875 mtdcri(SDR0
, port
->sdr_base
+ PESDRn_UTLSET2
, 0x01210000);
877 switch (port
->index
) {
879 mtdcri(SDR0
, PESDR0_460EX_L0CDRCTL
, 0x00003230);
880 mtdcri(SDR0
, PESDR0_460EX_L0DRV
, 0x00000130);
881 mtdcri(SDR0
, PESDR0_460EX_L0CLK
, 0x00000006);
883 mtdcri(SDR0
, PESDR0_460EX_PHY_CTL_RST
,0x10000000);
887 mtdcri(SDR0
, PESDR1_460EX_L0CDRCTL
, 0x00003230);
888 mtdcri(SDR0
, PESDR1_460EX_L1CDRCTL
, 0x00003230);
889 mtdcri(SDR0
, PESDR1_460EX_L2CDRCTL
, 0x00003230);
890 mtdcri(SDR0
, PESDR1_460EX_L3CDRCTL
, 0x00003230);
891 mtdcri(SDR0
, PESDR1_460EX_L0DRV
, 0x00000130);
892 mtdcri(SDR0
, PESDR1_460EX_L1DRV
, 0x00000130);
893 mtdcri(SDR0
, PESDR1_460EX_L2DRV
, 0x00000130);
894 mtdcri(SDR0
, PESDR1_460EX_L3DRV
, 0x00000130);
895 mtdcri(SDR0
, PESDR1_460EX_L0CLK
, 0x00000006);
896 mtdcri(SDR0
, PESDR1_460EX_L1CLK
, 0x00000006);
897 mtdcri(SDR0
, PESDR1_460EX_L2CLK
, 0x00000006);
898 mtdcri(SDR0
, PESDR1_460EX_L3CLK
, 0x00000006);
900 mtdcri(SDR0
, PESDR1_460EX_PHY_CTL_RST
,0x10000000);
904 mtdcri(SDR0
, port
->sdr_base
+ PESDRn_RCSSET
,
905 mfdcri(SDR0
, port
->sdr_base
+ PESDRn_RCSSET
) |
906 (PESDRx_RCSSET_RSTGU
| PESDRx_RCSSET_RSTPYN
));
908 /* Poll for PHY reset */
909 /* XXX FIXME add timeout */
910 switch (port
->index
) {
912 while (!(mfdcri(SDR0
, PESDR0_460EX_RSTSTA
) & 0x1))
916 while (!(mfdcri(SDR0
, PESDR1_460EX_RSTSTA
) & 0x1))
921 mtdcri(SDR0
, port
->sdr_base
+ PESDRn_RCSSET
,
922 (mfdcri(SDR0
, port
->sdr_base
+ PESDRn_RCSSET
) &
923 ~(PESDRx_RCSSET_RSTGU
| PESDRx_RCSSET_RSTDL
)) |
924 PESDRx_RCSSET_RSTPYN
);
931 static int ppc460ex_pciex_init_utl(struct ppc4xx_pciex_port
*port
)
933 dcr_write(port
->dcrs
, DCRO_PEGPL_SPECIAL
, 0x0);
936 * Set buffer allocations and then assert VRB and TXE.
938 out_be32(port
->utl_base
+ PEUTL_PBCTL
, 0x0800000c);
939 out_be32(port
->utl_base
+ PEUTL_OUTTR
, 0x08000000);
940 out_be32(port
->utl_base
+ PEUTL_INTR
, 0x02000000);
941 out_be32(port
->utl_base
+ PEUTL_OPDBSZ
, 0x04000000);
942 out_be32(port
->utl_base
+ PEUTL_PBBSZ
, 0x00000000);
943 out_be32(port
->utl_base
+ PEUTL_IPHBSZ
, 0x02000000);
944 out_be32(port
->utl_base
+ PEUTL_IPDBSZ
, 0x04000000);
945 out_be32(port
->utl_base
+ PEUTL_RCIRQEN
,0x00f00000);
946 out_be32(port
->utl_base
+ PEUTL_PCTL
, 0x80800066);
951 static struct ppc4xx_pciex_hwops ppc460ex_pcie_hwops __initdata
=
953 .core_init
= ppc460ex_pciex_core_init
,
954 .port_init_hw
= ppc460ex_pciex_init_port_hw
,
955 .setup_utl
= ppc460ex_pciex_init_utl
,
958 #endif /* CONFIG_44x */
962 static int __init
ppc405ex_pciex_core_init(struct device_node
*np
)
964 /* Nothing to do, return 2 ports */
968 static void ppc405ex_pcie_phy_reset(struct ppc4xx_pciex_port
*port
)
970 /* Assert the PE0_PHY reset */
971 mtdcri(SDR0
, port
->sdr_base
+ PESDRn_RCSSET
, 0x01010000);
974 /* deassert the PE0_hotreset */
976 mtdcri(SDR0
, port
->sdr_base
+ PESDRn_RCSSET
, 0x01111000);
978 mtdcri(SDR0
, port
->sdr_base
+ PESDRn_RCSSET
, 0x01101000);
980 /* poll for phy !reset */
981 /* XXX FIXME add timeout */
982 while (!(mfdcri(SDR0
, port
->sdr_base
+ PESDRn_405EX_PHYSTA
) & 0x00001000))
985 /* deassert the PE0_gpl_utl_reset */
986 mtdcri(SDR0
, port
->sdr_base
+ PESDRn_RCSSET
, 0x00101000);
989 static int ppc405ex_pciex_init_port_hw(struct ppc4xx_pciex_port
*port
)
994 val
= PTYPE_LEGACY_ENDPOINT
;
996 val
= PTYPE_ROOT_PORT
;
998 mtdcri(SDR0
, port
->sdr_base
+ PESDRn_DLPSET
,
999 1 << 24 | val
<< 20 | LNKW_X1
<< 12);
1001 mtdcri(SDR0
, port
->sdr_base
+ PESDRn_UTLSET1
, 0x00000000);
1002 mtdcri(SDR0
, port
->sdr_base
+ PESDRn_UTLSET2
, 0x01010000);
1003 mtdcri(SDR0
, port
->sdr_base
+ PESDRn_405EX_PHYSET1
, 0x720F0000);
1004 mtdcri(SDR0
, port
->sdr_base
+ PESDRn_405EX_PHYSET2
, 0x70600003);
1007 * Only reset the PHY when no link is currently established.
1008 * This is for the Atheros PCIe board which has problems to establish
1009 * the link (again) after this PHY reset. All other currently tested
1010 * PCIe boards don't show this problem.
1011 * This has to be re-tested and fixed in a later release!
1013 val
= mfdcri(SDR0
, port
->sdr_base
+ PESDRn_LOOP
);
1014 if (!(val
& 0x00001000))
1015 ppc405ex_pcie_phy_reset(port
);
1017 dcr_write(port
->dcrs
, DCRO_PEGPL_CFG
, 0x10000000); /* guarded on */
1019 port
->has_ibpre
= 1;
1024 static int ppc405ex_pciex_init_utl(struct ppc4xx_pciex_port
*port
)
1026 dcr_write(port
->dcrs
, DCRO_PEGPL_SPECIAL
, 0x0);
1029 * Set buffer allocations and then assert VRB and TXE.
1031 out_be32(port
->utl_base
+ PEUTL_OUTTR
, 0x02000000);
1032 out_be32(port
->utl_base
+ PEUTL_INTR
, 0x02000000);
1033 out_be32(port
->utl_base
+ PEUTL_OPDBSZ
, 0x04000000);
1034 out_be32(port
->utl_base
+ PEUTL_PBBSZ
, 0x21000000);
1035 out_be32(port
->utl_base
+ PEUTL_IPHBSZ
, 0x02000000);
1036 out_be32(port
->utl_base
+ PEUTL_IPDBSZ
, 0x04000000);
1037 out_be32(port
->utl_base
+ PEUTL_RCIRQEN
, 0x00f00000);
1038 out_be32(port
->utl_base
+ PEUTL_PCTL
, 0x80800066);
1040 out_be32(port
->utl_base
+ PEUTL_PBCTL
, 0x08000000);
1045 static struct ppc4xx_pciex_hwops ppc405ex_pcie_hwops __initdata
=
1047 .core_init
= ppc405ex_pciex_core_init
,
1048 .port_init_hw
= ppc405ex_pciex_init_port_hw
,
1049 .setup_utl
= ppc405ex_pciex_init_utl
,
1052 #endif /* CONFIG_40x */
1055 /* Check that the core has been initied and if not, do it */
1056 static int __init
ppc4xx_pciex_check_core_init(struct device_node
*np
)
1058 static int core_init
;
1059 int count
= -ENODEV
;
1065 if (of_device_is_compatible(np
, "ibm,plb-pciex-440spe")) {
1066 if (ppc440spe_revA())
1067 ppc4xx_pciex_hwops
= &ppc440speA_pcie_hwops
;
1069 ppc4xx_pciex_hwops
= &ppc440speB_pcie_hwops
;
1071 if (of_device_is_compatible(np
, "ibm,plb-pciex-460ex"))
1072 ppc4xx_pciex_hwops
= &ppc460ex_pcie_hwops
;
1073 #endif /* CONFIG_44x */
1075 if (of_device_is_compatible(np
, "ibm,plb-pciex-405ex"))
1076 ppc4xx_pciex_hwops
= &ppc405ex_pcie_hwops
;
1078 if (ppc4xx_pciex_hwops
== NULL
) {
1079 printk(KERN_WARNING
"PCIE: unknown host type %s\n",
1084 count
= ppc4xx_pciex_hwops
->core_init(np
);
1086 ppc4xx_pciex_ports
=
1087 kzalloc(count
* sizeof(struct ppc4xx_pciex_port
),
1089 if (ppc4xx_pciex_ports
) {
1090 ppc4xx_pciex_port_count
= count
;
1093 printk(KERN_WARNING
"PCIE: failed to allocate ports array\n");
1099 static void __init
ppc4xx_pciex_port_init_mapping(struct ppc4xx_pciex_port
*port
)
1101 /* We map PCI Express configuration based on the reg property */
1102 dcr_write(port
->dcrs
, DCRO_PEGPL_CFGBAH
,
1103 RES_TO_U32_HIGH(port
->cfg_space
.start
));
1104 dcr_write(port
->dcrs
, DCRO_PEGPL_CFGBAL
,
1105 RES_TO_U32_LOW(port
->cfg_space
.start
));
1107 /* XXX FIXME: Use size from reg property. For now, map 512M */
1108 dcr_write(port
->dcrs
, DCRO_PEGPL_CFGMSK
, 0xe0000001);
1110 /* We map UTL registers based on the reg property */
1111 dcr_write(port
->dcrs
, DCRO_PEGPL_REGBAH
,
1112 RES_TO_U32_HIGH(port
->utl_regs
.start
));
1113 dcr_write(port
->dcrs
, DCRO_PEGPL_REGBAL
,
1114 RES_TO_U32_LOW(port
->utl_regs
.start
));
1116 /* XXX FIXME: Use size from reg property */
1117 dcr_write(port
->dcrs
, DCRO_PEGPL_REGMSK
, 0x00007001);
1119 /* Disable all other outbound windows */
1120 dcr_write(port
->dcrs
, DCRO_PEGPL_OMR1MSKL
, 0);
1121 dcr_write(port
->dcrs
, DCRO_PEGPL_OMR2MSKL
, 0);
1122 dcr_write(port
->dcrs
, DCRO_PEGPL_OMR3MSKL
, 0);
1123 dcr_write(port
->dcrs
, DCRO_PEGPL_MSGMSK
, 0);
1126 static int __init
ppc4xx_pciex_wait_on_sdr(struct ppc4xx_pciex_port
*port
,
1127 unsigned int sdr_offset
,
1134 while(timeout_ms
--) {
1135 val
= mfdcri(SDR0
, port
->sdr_base
+ sdr_offset
);
1136 if ((val
& mask
) == value
) {
1137 pr_debug("PCIE%d: Wait on SDR %x success with tm %d (%08x)\n",
1138 port
->index
, sdr_offset
, timeout_ms
, val
);
1146 static int __init
ppc4xx_pciex_port_init(struct ppc4xx_pciex_port
*port
)
1151 if (ppc4xx_pciex_hwops
->port_init_hw
)
1152 rc
= ppc4xx_pciex_hwops
->port_init_hw(port
);
1156 printk(KERN_INFO
"PCIE%d: Checking link...\n",
1159 /* Wait for reset to complete */
1160 if (ppc4xx_pciex_wait_on_sdr(port
, PESDRn_RCSSTS
, 1 << 20, 0, 10)) {
1161 printk(KERN_WARNING
"PCIE%d: PGRST failed\n",
1166 /* Check for card presence detect if supported, if not, just wait for
1167 * link unconditionally.
1169 * note that we don't fail if there is no link, we just filter out
1170 * config space accesses. That way, it will be easier to implement
1173 if (!port
->has_ibpre
||
1174 !ppc4xx_pciex_wait_on_sdr(port
, PESDRn_LOOP
,
1175 1 << 28, 1 << 28, 100)) {
1177 "PCIE%d: Device detected, waiting for link...\n",
1179 if (ppc4xx_pciex_wait_on_sdr(port
, PESDRn_LOOP
,
1180 0x1000, 0x1000, 2000))
1182 "PCIE%d: Link up failed\n", port
->index
);
1185 "PCIE%d: link is up !\n", port
->index
);
1189 printk(KERN_INFO
"PCIE%d: No device detected.\n", port
->index
);
1192 * Initialize mapping: disable all regions and configure
1193 * CFG and REG regions based on resources in the device tree
1195 ppc4xx_pciex_port_init_mapping(port
);
1200 port
->utl_base
= ioremap(port
->utl_regs
.start
, 0x100);
1201 BUG_ON(port
->utl_base
== NULL
);
1204 * Setup UTL registers --BenH.
1206 if (ppc4xx_pciex_hwops
->setup_utl
)
1207 ppc4xx_pciex_hwops
->setup_utl(port
);
1210 * Check for VC0 active and assert RDY.
1213 ppc4xx_pciex_wait_on_sdr(port
, PESDRn_RCSSTS
,
1214 1 << 16, 1 << 16, 5000)) {
1215 printk(KERN_INFO
"PCIE%d: VC0 not active\n", port
->index
);
1219 dcri_clrset(SDR0
, port
->sdr_base
+ PESDRn_RCSSET
, 0, 1 << 20);
1225 static int ppc4xx_pciex_validate_bdf(struct ppc4xx_pciex_port
*port
,
1226 struct pci_bus
*bus
,
1231 /* Endpoint can not generate upstream(remote) config cycles */
1232 if (port
->endpoint
&& bus
->number
!= port
->hose
->first_busno
)
1233 return PCIBIOS_DEVICE_NOT_FOUND
;
1235 /* Check we are within the mapped range */
1236 if (bus
->number
> port
->hose
->last_busno
) {
1238 printk(KERN_WARNING
"Warning! Probing bus %u"
1239 " out of range !\n", bus
->number
);
1242 return PCIBIOS_DEVICE_NOT_FOUND
;
1245 /* The root complex has only one device / function */
1246 if (bus
->number
== port
->hose
->first_busno
&& devfn
!= 0)
1247 return PCIBIOS_DEVICE_NOT_FOUND
;
1249 /* The other side of the RC has only one device as well */
1250 if (bus
->number
== (port
->hose
->first_busno
+ 1) &&
1251 PCI_SLOT(devfn
) != 0)
1252 return PCIBIOS_DEVICE_NOT_FOUND
;
1254 /* Check if we have a link */
1255 if ((bus
->number
!= port
->hose
->first_busno
) && !port
->link
)
1256 return PCIBIOS_DEVICE_NOT_FOUND
;
1261 static void __iomem
*ppc4xx_pciex_get_config_base(struct ppc4xx_pciex_port
*port
,
1262 struct pci_bus
*bus
,
1267 /* Remove the casts when we finally remove the stupid volatile
1268 * in struct pci_controller
1270 if (bus
->number
== port
->hose
->first_busno
)
1271 return (void __iomem
*)port
->hose
->cfg_addr
;
1273 relbus
= bus
->number
- (port
->hose
->first_busno
+ 1);
1274 return (void __iomem
*)port
->hose
->cfg_data
+
1275 ((relbus
<< 20) | (devfn
<< 12));
1278 static int ppc4xx_pciex_read_config(struct pci_bus
*bus
, unsigned int devfn
,
1279 int offset
, int len
, u32
*val
)
1281 struct pci_controller
*hose
= (struct pci_controller
*) bus
->sysdata
;
1282 struct ppc4xx_pciex_port
*port
=
1283 &ppc4xx_pciex_ports
[hose
->indirect_type
];
1287 BUG_ON(hose
!= port
->hose
);
1289 if (ppc4xx_pciex_validate_bdf(port
, bus
, devfn
) != 0)
1290 return PCIBIOS_DEVICE_NOT_FOUND
;
1292 addr
= ppc4xx_pciex_get_config_base(port
, bus
, devfn
);
1295 * Reading from configuration space of non-existing device can
1296 * generate transaction errors. For the read duration we suppress
1297 * assertion of machine check exceptions to avoid those.
1299 gpl_cfg
= dcr_read(port
->dcrs
, DCRO_PEGPL_CFG
);
1300 dcr_write(port
->dcrs
, DCRO_PEGPL_CFG
, gpl_cfg
| GPL_DMER_MASK_DISA
);
1302 /* Make sure no CRS is recorded */
1303 out_be32(port
->utl_base
+ PEUTL_RCSTA
, 0x00040000);
1307 *val
= in_8((u8
*)(addr
+ offset
));
1310 *val
= in_le16((u16
*)(addr
+ offset
));
1313 *val
= in_le32((u32
*)(addr
+ offset
));
1317 pr_debug("pcie-config-read: bus=%3d [%3d..%3d] devfn=0x%04x"
1318 " offset=0x%04x len=%d, addr=0x%p val=0x%08x\n",
1319 bus
->number
, hose
->first_busno
, hose
->last_busno
,
1320 devfn
, offset
, len
, addr
+ offset
, *val
);
1322 /* Check for CRS (440SPe rev B does that for us but heh ..) */
1323 if (in_be32(port
->utl_base
+ PEUTL_RCSTA
) & 0x00040000) {
1324 pr_debug("Got CRS !\n");
1325 if (len
!= 4 || offset
!= 0)
1326 return PCIBIOS_DEVICE_NOT_FOUND
;
1330 dcr_write(port
->dcrs
, DCRO_PEGPL_CFG
, gpl_cfg
);
1332 return PCIBIOS_SUCCESSFUL
;
1335 static int ppc4xx_pciex_write_config(struct pci_bus
*bus
, unsigned int devfn
,
1336 int offset
, int len
, u32 val
)
1338 struct pci_controller
*hose
= (struct pci_controller
*) bus
->sysdata
;
1339 struct ppc4xx_pciex_port
*port
=
1340 &ppc4xx_pciex_ports
[hose
->indirect_type
];
1344 if (ppc4xx_pciex_validate_bdf(port
, bus
, devfn
) != 0)
1345 return PCIBIOS_DEVICE_NOT_FOUND
;
1347 addr
= ppc4xx_pciex_get_config_base(port
, bus
, devfn
);
1350 * Reading from configuration space of non-existing device can
1351 * generate transaction errors. For the read duration we suppress
1352 * assertion of machine check exceptions to avoid those.
1354 gpl_cfg
= dcr_read(port
->dcrs
, DCRO_PEGPL_CFG
);
1355 dcr_write(port
->dcrs
, DCRO_PEGPL_CFG
, gpl_cfg
| GPL_DMER_MASK_DISA
);
1357 pr_debug("pcie-config-write: bus=%3d [%3d..%3d] devfn=0x%04x"
1358 " offset=0x%04x len=%d, addr=0x%p val=0x%08x\n",
1359 bus
->number
, hose
->first_busno
, hose
->last_busno
,
1360 devfn
, offset
, len
, addr
+ offset
, val
);
1364 out_8((u8
*)(addr
+ offset
), val
);
1367 out_le16((u16
*)(addr
+ offset
), val
);
1370 out_le32((u32
*)(addr
+ offset
), val
);
1374 dcr_write(port
->dcrs
, DCRO_PEGPL_CFG
, gpl_cfg
);
1376 return PCIBIOS_SUCCESSFUL
;
1379 static struct pci_ops ppc4xx_pciex_pci_ops
=
1381 .read
= ppc4xx_pciex_read_config
,
1382 .write
= ppc4xx_pciex_write_config
,
1385 static int __init
ppc4xx_setup_one_pciex_POM(struct ppc4xx_pciex_port
*port
,
1386 struct pci_controller
*hose
,
1387 void __iomem
*mbase
,
1394 u32 lah
, lal
, pciah
, pcial
, sa
;
1396 if (!is_power_of_2(size
) ||
1397 (index
< 2 && size
< 0x100000) ||
1398 (index
== 2 && size
< 0x100) ||
1399 (plb_addr
& (size
- 1)) != 0) {
1400 printk(KERN_WARNING
"%s: Resource out of range\n",
1401 hose
->dn
->full_name
);
1405 /* Calculate register values */
1406 lah
= RES_TO_U32_HIGH(plb_addr
);
1407 lal
= RES_TO_U32_LOW(plb_addr
);
1408 pciah
= RES_TO_U32_HIGH(pci_addr
);
1409 pcial
= RES_TO_U32_LOW(pci_addr
);
1410 sa
= (0xffffffffu
<< ilog2(size
)) | 0x1;
1412 /* Program register values */
1415 out_le32(mbase
+ PECFG_POM0LAH
, pciah
);
1416 out_le32(mbase
+ PECFG_POM0LAL
, pcial
);
1417 dcr_write(port
->dcrs
, DCRO_PEGPL_OMR1BAH
, lah
);
1418 dcr_write(port
->dcrs
, DCRO_PEGPL_OMR1BAL
, lal
);
1419 dcr_write(port
->dcrs
, DCRO_PEGPL_OMR1MSKH
, 0x7fffffff);
1420 /* Note that 3 here means enabled | single region */
1421 dcr_write(port
->dcrs
, DCRO_PEGPL_OMR1MSKL
, sa
| 3);
1424 out_le32(mbase
+ PECFG_POM1LAH
, pciah
);
1425 out_le32(mbase
+ PECFG_POM1LAL
, pcial
);
1426 dcr_write(port
->dcrs
, DCRO_PEGPL_OMR2BAH
, lah
);
1427 dcr_write(port
->dcrs
, DCRO_PEGPL_OMR2BAL
, lal
);
1428 dcr_write(port
->dcrs
, DCRO_PEGPL_OMR2MSKH
, 0x7fffffff);
1429 /* Note that 3 here means enabled | single region */
1430 dcr_write(port
->dcrs
, DCRO_PEGPL_OMR2MSKL
, sa
| 3);
1433 out_le32(mbase
+ PECFG_POM2LAH
, pciah
);
1434 out_le32(mbase
+ PECFG_POM2LAL
, pcial
);
1435 dcr_write(port
->dcrs
, DCRO_PEGPL_OMR3BAH
, lah
);
1436 dcr_write(port
->dcrs
, DCRO_PEGPL_OMR3BAL
, lal
);
1437 dcr_write(port
->dcrs
, DCRO_PEGPL_OMR3MSKH
, 0x7fffffff);
1438 /* Note that 3 here means enabled | IO space !!! */
1439 dcr_write(port
->dcrs
, DCRO_PEGPL_OMR3MSKL
, sa
| 3);
1446 static void __init
ppc4xx_configure_pciex_POMs(struct ppc4xx_pciex_port
*port
,
1447 struct pci_controller
*hose
,
1448 void __iomem
*mbase
)
1450 int i
, j
, found_isa_hole
= 0;
1452 /* Setup outbound memory windows */
1453 for (i
= j
= 0; i
< 3; i
++) {
1454 struct resource
*res
= &hose
->mem_resources
[i
];
1456 /* we only care about memory windows */
1457 if (!(res
->flags
& IORESOURCE_MEM
))
1460 printk(KERN_WARNING
"%s: Too many ranges\n",
1461 port
->node
->full_name
);
1465 /* Configure the resource */
1466 if (ppc4xx_setup_one_pciex_POM(port
, hose
, mbase
,
1468 res
->start
- hose
->pci_mem_offset
,
1469 res
->end
+ 1 - res
->start
,
1474 /* If the resource PCI address is 0 then we have our
1477 if (res
->start
== hose
->pci_mem_offset
)
1482 /* Handle ISA memory hole if not already covered */
1483 if (j
<= 1 && !found_isa_hole
&& hose
->isa_mem_size
)
1484 if (ppc4xx_setup_one_pciex_POM(port
, hose
, mbase
,
1485 hose
->isa_mem_phys
, 0,
1486 hose
->isa_mem_size
, 0, j
) == 0)
1487 printk(KERN_INFO
"%s: Legacy ISA memory support enabled\n",
1488 hose
->dn
->full_name
);
1490 /* Configure IO, always 64K starting at 0. We hard wire it to 64K !
1491 * Note also that it -has- to be region index 2 on this HW
1493 if (hose
->io_resource
.flags
& IORESOURCE_IO
)
1494 ppc4xx_setup_one_pciex_POM(port
, hose
, mbase
,
1495 hose
->io_base_phys
, 0,
1496 0x10000, IORESOURCE_IO
, 2);
1499 static void __init
ppc4xx_configure_pciex_PIMs(struct ppc4xx_pciex_port
*port
,
1500 struct pci_controller
*hose
,
1501 void __iomem
*mbase
,
1502 struct resource
*res
)
1504 resource_size_t size
= res
->end
- res
->start
+ 1;
1507 if (port
->endpoint
) {
1508 resource_size_t ep_addr
= 0;
1509 resource_size_t ep_size
= 32 << 20;
1511 /* Currently we map a fixed 64MByte window to PLB address
1512 * 0 (SDRAM). This should probably be configurable via a dts
1516 /* Calculate window size */
1517 sa
= (0xffffffffffffffffull
<< ilog2(ep_size
));;
1520 out_le32(mbase
+ PECFG_BAR0HMPA
, RES_TO_U32_HIGH(sa
));
1521 out_le32(mbase
+ PECFG_BAR0LMPA
, RES_TO_U32_LOW(sa
) |
1522 PCI_BASE_ADDRESS_MEM_TYPE_64
);
1524 /* Disable BAR1 & BAR2 */
1525 out_le32(mbase
+ PECFG_BAR1MPA
, 0);
1526 out_le32(mbase
+ PECFG_BAR2HMPA
, 0);
1527 out_le32(mbase
+ PECFG_BAR2LMPA
, 0);
1529 out_le32(mbase
+ PECFG_PIM01SAH
, RES_TO_U32_HIGH(sa
));
1530 out_le32(mbase
+ PECFG_PIM01SAL
, RES_TO_U32_LOW(sa
));
1532 out_le32(mbase
+ PCI_BASE_ADDRESS_0
, RES_TO_U32_LOW(ep_addr
));
1533 out_le32(mbase
+ PCI_BASE_ADDRESS_1
, RES_TO_U32_HIGH(ep_addr
));
1535 /* Calculate window size */
1536 sa
= (0xffffffffffffffffull
<< ilog2(size
));;
1537 if (res
->flags
& IORESOURCE_PREFETCH
)
1540 out_le32(mbase
+ PECFG_BAR0HMPA
, RES_TO_U32_HIGH(sa
));
1541 out_le32(mbase
+ PECFG_BAR0LMPA
, RES_TO_U32_LOW(sa
));
1543 /* The setup of the split looks weird to me ... let's see
1546 out_le32(mbase
+ PECFG_PIM0LAL
, 0x00000000);
1547 out_le32(mbase
+ PECFG_PIM0LAH
, 0x00000000);
1548 out_le32(mbase
+ PECFG_PIM1LAL
, 0x00000000);
1549 out_le32(mbase
+ PECFG_PIM1LAH
, 0x00000000);
1550 out_le32(mbase
+ PECFG_PIM01SAH
, 0xffff0000);
1551 out_le32(mbase
+ PECFG_PIM01SAL
, 0x00000000);
1553 out_le32(mbase
+ PCI_BASE_ADDRESS_0
, RES_TO_U32_LOW(res
->start
));
1554 out_le32(mbase
+ PCI_BASE_ADDRESS_1
, RES_TO_U32_HIGH(res
->start
));
1557 /* Enable inbound mapping */
1558 out_le32(mbase
+ PECFG_PIMEN
, 0x1);
1560 /* Enable I/O, Mem, and Busmaster cycles */
1561 out_le16(mbase
+ PCI_COMMAND
,
1562 in_le16(mbase
+ PCI_COMMAND
) |
1563 PCI_COMMAND_IO
| PCI_COMMAND_MEMORY
| PCI_COMMAND_MASTER
);
1566 static void __init
ppc4xx_pciex_port_setup_hose(struct ppc4xx_pciex_port
*port
)
1568 struct resource dma_window
;
1569 struct pci_controller
*hose
= NULL
;
1570 const int *bus_range
;
1571 int primary
= 0, busses
;
1572 void __iomem
*mbase
= NULL
, *cfg_data
= NULL
;
1576 /* Check if primary bridge */
1577 if (of_get_property(port
->node
, "primary", NULL
))
1580 /* Get bus range if any */
1581 bus_range
= of_get_property(port
->node
, "bus-range", NULL
);
1583 /* Allocate the host controller data structure */
1584 hose
= pcibios_alloc_controller(port
->node
);
1588 /* We stick the port number in "indirect_type" so the config space
1589 * ops can retrieve the port data structure easily
1591 hose
->indirect_type
= port
->index
;
1594 hose
->first_busno
= bus_range
? bus_range
[0] : 0x0;
1595 hose
->last_busno
= bus_range
? bus_range
[1] : 0xff;
1597 /* Because of how big mapping the config space is (1M per bus), we
1598 * limit how many busses we support. In the long run, we could replace
1599 * that with something akin to kmap_atomic instead. We set aside 1 bus
1600 * for the host itself too.
1602 busses
= hose
->last_busno
- hose
->first_busno
; /* This is off by 1 */
1603 if (busses
> MAX_PCIE_BUS_MAPPED
) {
1604 busses
= MAX_PCIE_BUS_MAPPED
;
1605 hose
->last_busno
= hose
->first_busno
+ busses
;
1608 if (!port
->endpoint
) {
1609 /* Only map the external config space in cfg_data for
1610 * PCIe root-complexes. External space is 1M per bus
1612 cfg_data
= ioremap(port
->cfg_space
.start
+
1613 (hose
->first_busno
+ 1) * 0x100000,
1615 if (cfg_data
== NULL
) {
1616 printk(KERN_ERR
"%s: Can't map external config space !",
1617 port
->node
->full_name
);
1620 hose
->cfg_data
= cfg_data
;
1623 /* Always map the host config space in cfg_addr.
1624 * Internal space is 4K
1626 mbase
= ioremap(port
->cfg_space
.start
+ 0x10000000, 0x1000);
1627 if (mbase
== NULL
) {
1628 printk(KERN_ERR
"%s: Can't map internal config space !",
1629 port
->node
->full_name
);
1632 hose
->cfg_addr
= mbase
;
1634 pr_debug("PCIE %s, bus %d..%d\n", port
->node
->full_name
,
1635 hose
->first_busno
, hose
->last_busno
);
1636 pr_debug(" config space mapped at: root @0x%p, other @0x%p\n",
1637 hose
->cfg_addr
, hose
->cfg_data
);
1639 /* Setup config space */
1640 hose
->ops
= &ppc4xx_pciex_pci_ops
;
1642 mbase
= (void __iomem
*)hose
->cfg_addr
;
1644 if (!port
->endpoint
) {
1646 * Set bus numbers on our root port
1648 out_8(mbase
+ PCI_PRIMARY_BUS
, hose
->first_busno
);
1649 out_8(mbase
+ PCI_SECONDARY_BUS
, hose
->first_busno
+ 1);
1650 out_8(mbase
+ PCI_SUBORDINATE_BUS
, hose
->last_busno
);
1654 * OMRs are already reset, also disable PIMs
1656 out_le32(mbase
+ PECFG_PIMEN
, 0);
1658 /* Parse outbound mapping resources */
1659 pci_process_bridge_OF_ranges(hose
, port
->node
, primary
);
1661 /* Parse inbound mapping resources */
1662 if (ppc4xx_parse_dma_ranges(hose
, mbase
, &dma_window
) != 0)
1665 /* Configure outbound ranges POMs */
1666 ppc4xx_configure_pciex_POMs(port
, hose
, mbase
);
1668 /* Configure inbound ranges PIMs */
1669 ppc4xx_configure_pciex_PIMs(port
, hose
, mbase
, &dma_window
);
1671 /* The root complex doesn't show up if we don't set some vendor
1672 * and device IDs into it. The defaults below are the same bogus
1673 * one that the initial code in arch/ppc had. This can be
1674 * overwritten by setting the "vendor-id/device-id" properties
1675 * in the pciex node.
1678 /* Get the (optional) vendor-/device-id from the device-tree */
1679 pval
= of_get_property(port
->node
, "vendor-id", NULL
);
1683 if (!port
->endpoint
)
1684 val
= 0xaaa0 + port
->index
;
1686 val
= 0xeee0 + port
->index
;
1688 out_le16(mbase
+ 0x200, val
);
1690 pval
= of_get_property(port
->node
, "device-id", NULL
);
1694 if (!port
->endpoint
)
1695 val
= 0xbed0 + port
->index
;
1697 val
= 0xfed0 + port
->index
;
1699 out_le16(mbase
+ 0x202, val
);
1701 if (!port
->endpoint
) {
1702 /* Set Class Code to PCI-PCI bridge and Revision Id to 1 */
1703 out_le32(mbase
+ 0x208, 0x06040001);
1705 printk(KERN_INFO
"PCIE%d: successfully set as root-complex\n",
1708 /* Set Class Code to Processor/PPC */
1709 out_le32(mbase
+ 0x208, 0x0b200001);
1711 printk(KERN_INFO
"PCIE%d: successfully set as endpoint\n",
1718 pcibios_free_controller(hose
);
1725 static void __init
ppc4xx_probe_pciex_bridge(struct device_node
*np
)
1727 struct ppc4xx_pciex_port
*port
;
1733 /* First, proceed to core initialization as we assume there's
1734 * only one PCIe core in the system
1736 if (ppc4xx_pciex_check_core_init(np
))
1739 /* Get the port number from the device-tree */
1740 pval
= of_get_property(np
, "port", NULL
);
1742 printk(KERN_ERR
"PCIE: Can't find port number for %s\n",
1747 if (portno
>= ppc4xx_pciex_port_count
) {
1748 printk(KERN_ERR
"PCIE: port number out of range for %s\n",
1752 port
= &ppc4xx_pciex_ports
[portno
];
1753 port
->index
= portno
;
1756 * Check if device is enabled
1758 if (!of_device_is_available(np
)) {
1759 printk(KERN_INFO
"PCIE%d: Port disabled via device-tree\n", port
->index
);
1763 port
->node
= of_node_get(np
);
1764 pval
= of_get_property(np
, "sdr-base", NULL
);
1766 printk(KERN_ERR
"PCIE: missing sdr-base for %s\n",
1770 port
->sdr_base
= *pval
;
1772 /* Check if device_type property is set to "pci" or "pci-endpoint".
1773 * Resulting from this setup this PCIe port will be configured
1774 * as root-complex or as endpoint.
1776 val
= of_get_property(port
->node
, "device_type", NULL
);
1777 if (!strcmp(val
, "pci-endpoint")) {
1779 } else if (!strcmp(val
, "pci")) {
1782 printk(KERN_ERR
"PCIE: missing or incorrect device_type for %s\n",
1787 /* Fetch config space registers address */
1788 if (of_address_to_resource(np
, 0, &port
->cfg_space
)) {
1789 printk(KERN_ERR
"%s: Can't get PCI-E config space !",
1793 /* Fetch host bridge internal registers address */
1794 if (of_address_to_resource(np
, 1, &port
->utl_regs
)) {
1795 printk(KERN_ERR
"%s: Can't get UTL register base !",
1801 dcrs
= dcr_resource_start(np
, 0);
1803 printk(KERN_ERR
"%s: Can't get DCR register base !",
1807 port
->dcrs
= dcr_map(np
, dcrs
, dcr_resource_len(np
, 0));
1809 /* Initialize the port specific registers */
1810 if (ppc4xx_pciex_port_init(port
)) {
1811 printk(KERN_WARNING
"PCIE%d: Port init failed\n", port
->index
);
1815 /* Setup the linux hose data structure */
1816 ppc4xx_pciex_port_setup_hose(port
);
1819 #endif /* CONFIG_PPC4xx_PCI_EXPRESS */
1821 static int __init
ppc4xx_pci_find_bridges(void)
1823 struct device_node
*np
;
1825 #ifdef CONFIG_PPC4xx_PCI_EXPRESS
1826 for_each_compatible_node(np
, NULL
, "ibm,plb-pciex")
1827 ppc4xx_probe_pciex_bridge(np
);
1829 for_each_compatible_node(np
, NULL
, "ibm,plb-pcix")
1830 ppc4xx_probe_pcix_bridge(np
);
1831 for_each_compatible_node(np
, NULL
, "ibm,plb-pci")
1832 ppc4xx_probe_pci_bridge(np
);
1836 arch_initcall(ppc4xx_pci_find_bridges
);