2 * Interrupt controller driver for Xilinx Virtex FPGAs
4 * Copyright (C) 2007 Secret Lab Technologies Ltd.
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
13 * This is a driver for the interrupt controller typically found in
14 * Xilinx Virtex FPGA designs.
16 * The interrupt sense levels are hard coded into the FPGA design with
17 * typically a 1:1 relationship between irq lines and devices (no shared
18 * irq lines). Therefore, this driver does not attempt to handle edge
19 * and level interrupts differently.
23 #include <linux/kernel.h>
24 #include <linux/irq.h>
27 #include <asm/processor.h>
33 #define XINTC_ISR 0 /* Interrupt Status */
34 #define XINTC_IPR 4 /* Interrupt Pending */
35 #define XINTC_IER 8 /* Interrupt Enable */
36 #define XINTC_IAR 12 /* Interrupt Acknowledge */
37 #define XINTC_SIE 16 /* Set Interrupt Enable bits */
38 #define XINTC_CIE 20 /* Clear Interrupt Enable bits */
39 #define XINTC_IVR 24 /* Interrupt Vector */
40 #define XINTC_MER 28 /* Master Enable */
42 static struct irq_host
*master_irqhost
;
44 #define XILINX_INTC_MAXIRQS (32)
46 /* The following table allows the interrupt type, edge or level,
47 * to be cached after being read from the device tree until the interrupt
50 static int xilinx_intc_typetable
[XILINX_INTC_MAXIRQS
];
52 /* Map the interrupt type from the device tree to the interrupt types
53 * used by the interrupt subsystem
55 static unsigned char xilinx_intc_map_senses
[] = {
57 IRQ_TYPE_EDGE_FALLING
,
63 * The interrupt controller is setup such that it doesn't work well with
64 * the level interrupt handler in the kernel because the handler acks the
65 * interrupt before calling the application interrupt handler. To deal with
66 * that, we use 2 different irq chips so that different functions can be
67 * used for level and edge type interrupts.
69 * IRQ Chip common (across level and edge) operations
71 static void xilinx_intc_mask(unsigned int virq
)
73 int irq
= virq_to_hw(virq
);
74 void * regs
= get_irq_chip_data(virq
);
75 pr_debug("mask: %d\n", irq
);
76 out_be32(regs
+ XINTC_CIE
, 1 << irq
);
79 static int xilinx_intc_set_type(unsigned int virq
, unsigned int flow_type
)
81 struct irq_desc
*desc
= get_irq_desc(virq
);
83 desc
->status
&= ~(IRQ_TYPE_SENSE_MASK
| IRQ_LEVEL
);
84 desc
->status
|= flow_type
& IRQ_TYPE_SENSE_MASK
;
85 if (flow_type
& (IRQ_TYPE_LEVEL_HIGH
| IRQ_TYPE_LEVEL_LOW
))
86 desc
->status
|= IRQ_LEVEL
;
91 * IRQ Chip level operations
93 static void xilinx_intc_level_unmask(unsigned int virq
)
95 int irq
= virq_to_hw(virq
);
96 void * regs
= get_irq_chip_data(virq
);
97 pr_debug("unmask: %d\n", irq
);
98 out_be32(regs
+ XINTC_SIE
, 1 << irq
);
100 /* ack level irqs because they can't be acked during
101 * ack function since the handle_level_irq function
102 * acks the irq before calling the inerrupt handler
104 out_be32(regs
+ XINTC_IAR
, 1 << irq
);
107 static struct irq_chip xilinx_intc_level_irqchip
= {
108 .typename
= "Xilinx Level INTC",
109 .mask
= xilinx_intc_mask
,
110 .mask_ack
= xilinx_intc_mask
,
111 .unmask
= xilinx_intc_level_unmask
,
112 .set_type
= xilinx_intc_set_type
,
116 * IRQ Chip edge operations
118 static void xilinx_intc_edge_unmask(unsigned int virq
)
120 int irq
= virq_to_hw(virq
);
121 void *regs
= get_irq_chip_data(virq
);
122 pr_debug("unmask: %d\n", irq
);
123 out_be32(regs
+ XINTC_SIE
, 1 << irq
);
126 static void xilinx_intc_edge_ack(unsigned int virq
)
128 int irq
= virq_to_hw(virq
);
129 void * regs
= get_irq_chip_data(virq
);
130 pr_debug("ack: %d\n", irq
);
131 out_be32(regs
+ XINTC_IAR
, 1 << irq
);
134 static struct irq_chip xilinx_intc_edge_irqchip
= {
135 .typename
= "Xilinx Edge INTC",
136 .mask
= xilinx_intc_mask
,
137 .unmask
= xilinx_intc_edge_unmask
,
138 .ack
= xilinx_intc_edge_ack
,
139 .set_type
= xilinx_intc_set_type
,
143 * IRQ Host operations
147 * xilinx_intc_xlate - translate virq# from device tree interrupts property
149 static int xilinx_intc_xlate(struct irq_host
*h
, struct device_node
*ct
,
150 u32
*intspec
, unsigned int intsize
,
151 irq_hw_number_t
*out_hwirq
,
152 unsigned int *out_flags
)
154 if ((intsize
< 2) || (intspec
[0] >= XILINX_INTC_MAXIRQS
))
157 /* keep a copy of the interrupt type til the interrupt is mapped
159 xilinx_intc_typetable
[intspec
[0]] = xilinx_intc_map_senses
[intspec
[1]];
161 /* Xilinx uses 2 interrupt entries, the 1st being the h/w
162 * interrupt number, the 2nd being the interrupt type, edge or level
164 *out_hwirq
= intspec
[0];
165 *out_flags
= xilinx_intc_map_senses
[intspec
[1]];
169 static int xilinx_intc_map(struct irq_host
*h
, unsigned int virq
,
172 set_irq_chip_data(virq
, h
->host_data
);
174 if (xilinx_intc_typetable
[irq
] == IRQ_TYPE_LEVEL_HIGH
||
175 xilinx_intc_typetable
[irq
] == IRQ_TYPE_LEVEL_LOW
) {
176 set_irq_chip_and_handler(virq
, &xilinx_intc_level_irqchip
,
179 set_irq_chip_and_handler(virq
, &xilinx_intc_edge_irqchip
,
185 static struct irq_host_ops xilinx_intc_ops
= {
186 .map
= xilinx_intc_map
,
187 .xlate
= xilinx_intc_xlate
,
190 struct irq_host
* __init
191 xilinx_intc_init(struct device_node
*np
)
193 struct irq_host
* irq
;
198 /* Find and map the intc registers */
199 rc
= of_address_to_resource(np
, 0, &res
);
201 printk(KERN_ERR __FILE__
": of_address_to_resource() failed\n");
204 regs
= ioremap(res
.start
, 32);
206 printk(KERN_INFO
"Xilinx intc at 0x%08llx mapped to 0x%p\n",
207 (unsigned long long) res
.start
, regs
);
209 /* Setup interrupt controller */
210 out_be32(regs
+ XINTC_IER
, 0); /* disable all irqs */
211 out_be32(regs
+ XINTC_IAR
, ~(u32
) 0); /* Acknowledge pending irqs */
212 out_be32(regs
+ XINTC_MER
, 0x3UL
); /* Turn on the Master Enable. */
214 /* Allocate and initialize an irq_host structure. */
215 irq
= irq_alloc_host(np
, IRQ_HOST_MAP_LINEAR
, XILINX_INTC_MAXIRQS
,
216 &xilinx_intc_ops
, -1);
218 panic(__FILE__
": Cannot allocate IRQ host\n");
219 irq
->host_data
= regs
;
223 int xilinx_intc_get_irq(void)
225 void * regs
= master_irqhost
->host_data
;
226 pr_debug("get_irq:\n");
227 return irq_linear_revmap(master_irqhost
, in_be32(regs
+ XINTC_IVR
));
230 void __init
xilinx_intc_init_tree(void)
232 struct device_node
*np
;
234 /* find top level interrupt controller */
235 for_each_compatible_node(np
, NULL
, "xlnx,opb-intc-1.00.c") {
236 if (!of_get_property(np
, "interrupts", NULL
))
240 for_each_compatible_node(np
, NULL
, "xlnx,xps-intc-1.00.a") {
241 if (!of_get_property(np
, "interrupts", NULL
))
246 /* xilinx interrupt controller needs to be top level */
249 master_irqhost
= xilinx_intc_init(np
);
250 BUG_ON(!master_irqhost
);
252 irq_set_default_host(master_irqhost
);