arch/ppc/kernel/cpu_setup_6xx.S

   1 /*
   2  * This file contains low level CPU setup functions.
   3  *    Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org)
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License
   7  * as published by the Free Software Foundation; either version
   8  * 2 of the License, or (at your option) any later version.
   9  *
  10  */
  11
  12 #include <linux/config.h>
  13 #include <asm/processor.h>
  14 #include <asm/page.h>
  15 #include <asm/ppc_asm.h>
  16 #include <asm/cputable.h>
  17 #include <asm/ppc_asm.h>
  18 #include <asm/asm-offsets.h>
  19 #include <asm/cache.h>
  20
  21 _GLOBAL(__setup_cpu_601)
  22         blr
  23 _GLOBAL(__setup_cpu_603)
  24         b       setup_common_caches
  25 _GLOBAL(__setup_cpu_604)
  26         mflr    r4
  27         bl      setup_common_caches
  28         bl      setup_604_hid0
  29         mtlr    r4
  30         blr
  31 _GLOBAL(__setup_cpu_750)
  32         mflr    r4
  33         bl      __init_fpu_registers
  34         bl      setup_common_caches
  35         bl      setup_750_7400_hid0
  36         mtlr    r4
  37         blr
  38 _GLOBAL(__setup_cpu_750cx)
  39         mflr    r4
  40         bl      __init_fpu_registers
  41         bl      setup_common_caches
  42         bl      setup_750_7400_hid0
  43         bl      setup_750cx
  44         mtlr    r4
  45         blr
  46 _GLOBAL(__setup_cpu_750fx)
  47         mflr    r4
  48         bl      __init_fpu_registers
  49         bl      setup_common_caches
  50         bl      setup_750_7400_hid0
  51         bl      setup_750fx
  52         mtlr    r4
  53         blr
  54 _GLOBAL(__setup_cpu_7400)
  55         mflr    r4
  56         bl      __init_fpu_registers
  57         bl      setup_7400_workarounds
  58         bl      setup_common_caches
  59         bl      setup_750_7400_hid0
  60         mtlr    r4
  61         blr
  62 _GLOBAL(__setup_cpu_7410)
  63         mflr    r4
  64         bl      __init_fpu_registers
  65         bl      setup_7410_workarounds
  66         bl      setup_common_caches
  67         bl      setup_750_7400_hid0
  68         li      r3,0
  69         mtspr   SPRN_L2CR2,r3
  70         mtlr    r4
  71         blr
  72 _GLOBAL(__setup_cpu_745x)
  73         mflr    r4
  74         bl      setup_common_caches
  75         bl      setup_745x_specifics
  76         mtlr    r4
  77         blr
  78
  79 /* Enable caches for 603's, 604, 750 & 7400 */
  80 setup_common_caches:
  81         mfspr   r11,SPRN_HID0
  82         andi.   r0,r11,HID0_DCE
  83         ori     r11,r11,HID0_ICE|HID0_DCE
  84         ori     r8,r11,HID0_ICFI
  85         bne     1f                      /* don't invalidate the D-cache */
  86         ori     r8,r8,HID0_DCI          /* unless it wasn't enabled */
  87 1:      sync
  88         mtspr   SPRN_HID0,r8            /* enable and invalidate caches */
  89         sync
  90         mtspr   SPRN_HID0,r11           /* enable caches */
  91         sync
  92         isync
  93         blr
  94
  95 /* 604, 604e, 604ev, ...
  96  * Enable superscalar execution & branch history table
  97  */
  98 setup_604_hid0:
  99         mfspr   r11,SPRN_HID0
 100         ori     r11,r11,HID0_SIED|HID0_BHTE
 101         ori     r8,r11,HID0_BTCD
 102         sync
 103         mtspr   SPRN_HID0,r8    /* flush branch target address cache */
 104         sync                    /* on 604e/604r */
 105         mtspr   SPRN_HID0,r11
 106         sync
 107         isync
 108         blr
 109
 110 /* 7400 <= rev 2.7 and 7410 rev = 1.0 suffer from some
 111  * erratas we work around here.
 112  * Moto MPC710CE.pdf describes them, those are errata
 113  * #3, #4 and #5
 114  * Note that we assume the firmware didn't choose to
 115  * apply other workarounds (there are other ones documented
 116  * in the .pdf). It appear that Apple firmware only works
 117  * around #3 and with the same fix we use. We may want to
 118  * check if the CPU is using 60x bus mode in which case
 119  * the workaround for errata #4 is useless. Also, we may
 120  * want to explicitely clear HID0_NOPDST as this is not
 121  * needed once we have applied workaround #5 (though it's
 122  * not set by Apple's firmware at least).
 123  */
 124 setup_7400_workarounds:
 125         mfpvr   r3
 126         rlwinm  r3,r3,0,20,31
 127         cmpwi   0,r3,0x0207
 128         ble     1f
 129         blr
 130 setup_7410_workarounds:
 131         mfpvr   r3
 132         rlwinm  r3,r3,0,20,31
 133         cmpwi   0,r3,0x0100
 134         bnelr
 135 1:
 136         mfspr   r11,SPRN_MSSSR0
 137         /* Errata #3: Set L1OPQ_SIZE to 0x10 */
 138         rlwinm  r11,r11,0,9,6
 139         oris    r11,r11,0x0100
 140         /* Errata #4: Set L2MQ_SIZE to 1 (check for MPX mode first ?) */
 141         oris    r11,r11,0x0002
 142         /* Errata #5: Set DRLT_SIZE to 0x01 */
 143         rlwinm  r11,r11,0,5,2
 144         oris    r11,r11,0x0800
 145         sync
 146         mtspr   SPRN_MSSSR0,r11
 147         sync
 148         isync
 149         blr
 150
 151 /* 740/750/7400/7410
 152  * Enable Store Gathering (SGE), Address Brodcast (ABE),
 153  * Branch History Table (BHTE), Branch Target ICache (BTIC)
 154  * Dynamic Power Management (DPM), Speculative (SPD)
 155  * Clear Instruction cache throttling (ICTC)
 156  */
 157 setup_750_7400_hid0:
 158         mfspr   r11,SPRN_HID0
 159         ori     r11,r11,HID0_SGE | HID0_ABE | HID0_BHTE | HID0_BTIC
 160         oris    r11,r11,HID0_DPM@h
 161 BEGIN_FTR_SECTION
 162         xori    r11,r11,HID0_BTIC
 163 END_FTR_SECTION_IFSET(CPU_FTR_NO_BTIC)
 164 BEGIN_FTR_SECTION
 165         xoris   r11,r11,HID0_DPM@h      /* disable dynamic power mgmt */
 166 END_FTR_SECTION_IFSET(CPU_FTR_NO_DPM)
 167         li      r3,HID0_SPD
 168         andc    r11,r11,r3              /* clear SPD: enable speculative */
 169         li      r3,0
 170         mtspr   SPRN_ICTC,r3            /* Instruction Cache Throttling off */
 171         isync
 172         mtspr   SPRN_HID0,r11
 173         sync
 174         isync
 175         blr
 176
 177 /* 750cx specific
 178  * Looks like we have to disable NAP feature for some PLL settings...
 179  * (waiting for confirmation)
 180  */
 181 setup_750cx:
 182         mfspr   r10, SPRN_HID1
 183         rlwinm  r10,r10,4,28,31
 184         cmpwi   cr0,r10,7
 185         cmpwi   cr1,r10,9
 186         cmpwi   cr2,r10,11
 187         cror    4*cr0+eq,4*cr0+eq,4*cr1+eq
 188         cror    4*cr0+eq,4*cr0+eq,4*cr2+eq
 189         bnelr
 190         lwz     r6,CPU_SPEC_FEATURES(r5)
 191         li      r7,CPU_FTR_CAN_NAP
 192         andc    r6,r6,r7
 193         stw     r6,CPU_SPEC_FEATURES(r5)
 194         blr
 195
 196 /* 750fx specific
 197  */
 198 setup_750fx:
 199         blr
 200
 201 /* MPC 745x
 202  * Enable Store Gathering (SGE), Branch Folding (FOLD)
 203  * Branch History Table (BHTE), Branch Target ICache (BTIC)
 204  * Dynamic Power Management (DPM), Speculative (SPD)
 205  * Ensure our data cache instructions really operate.
 206  * Timebase has to be running or we wouldn't have made it here,
 207  * just ensure we don't disable it.
 208  * Clear Instruction cache throttling (ICTC)
 209  * Enable L2 HW prefetch
 210  */
 211 setup_745x_specifics:
 212         /* We check for the presence of an L3 cache setup by
 213          * the firmware. If any, we disable NAP capability as
 214          * it's known to be bogus on rev 2.1 and earlier
 215          */
 216         mfspr   r11,SPRN_L3CR
 217         andis.  r11,r11,L3CR_L3E@h
 218         beq     1f
 219         lwz     r6,CPU_SPEC_FEATURES(r5)
 220         andi.   r0,r6,CPU_FTR_L3_DISABLE_NAP
 221         beq     1f
 222         li      r7,CPU_FTR_CAN_NAP
 223         andc    r6,r6,r7
 224         stw     r6,CPU_SPEC_FEATURES(r5)
 225 1:
 226         mfspr   r11,SPRN_HID0
 227
 228         /* All of the bits we have to set.....
 229          */
 230         ori     r11,r11,HID0_SGE | HID0_FOLD | HID0_BHTE
 231         ori     r11,r11,HID0_LRSTK | HID0_BTIC
 232         oris    r11,r11,HID0_DPM@h
 233 BEGIN_FTR_SECTION
 234         xori    r11,r11,HID0_BTIC
 235 END_FTR_SECTION_IFSET(CPU_FTR_NO_BTIC)
 236 BEGIN_FTR_SECTION
 237         xoris   r11,r11,HID0_DPM@h      /* disable dynamic power mgmt */
 238 END_FTR_SECTION_IFSET(CPU_FTR_NO_DPM)
 239
 240         /* All of the bits we have to clear....
 241          */
 242         li      r3,HID0_SPD | HID0_NOPDST | HID0_NOPTI
 243         andc    r11,r11,r3              /* clear SPD: enable speculative */
 244         li      r3,0
 245
 246         mtspr   SPRN_ICTC,r3            /* Instruction Cache Throttling off */
 247         isync
 248         mtspr   SPRN_HID0,r11
 249         sync
 250         isync
 251
 252         /* Enable L2 HW prefetch, if L2 is enabled
 253          */
 254         mfspr   r3,SPRN_L2CR
 255         andis.  r3,r3,L2CR_L2E@h
 256         beqlr
 257         mfspr   r3,SPRN_MSSCR0
 258         ori     r3,r3,3
 259         sync
 260         mtspr   SPRN_MSSCR0,r3
 261         sync
 262         isync
 263         blr
 264
 265 /*
 266  * Initialize the FPU registers. This is needed to work around an errata
 267  * in some 750 cpus where using a not yet initialized FPU register after
 268  * power on reset may hang the CPU
 269  */
 270 _GLOBAL(__init_fpu_registers)
 271         mfmsr   r10
 272         ori     r11,r10,MSR_FP
 273         mtmsr   r11
 274         isync
 275         addis   r9,r3,empty_zero_page@ha
 276         addi    r9,r9,empty_zero_page@l
 277         REST_32FPRS(0,r9)
 278         sync
 279         mtmsr   r10
 280         isync
 281         blr
 282
 283
 284 /* Definitions for the table use to save CPU states */
 285 #define CS_HID0         0
 286 #define CS_HID1         4
 287 #define CS_HID2         8
 288 #define CS_MSSCR0       12
 289 #define CS_MSSSR0       16
 290 #define CS_ICTRL        20
 291 #define CS_LDSTCR       24
 292 #define CS_LDSTDB       28
 293 #define CS_SIZE         32
 294
 295         .data
 296         .balign L1_CACHE_LINE_SIZE
 297 cpu_state_storage:
 298         .space  CS_SIZE
 299         .balign L1_CACHE_LINE_SIZE,0
 300         .text
 301
 302 /* Called in normal context to backup CPU 0 state. This
 303  * does not include cache settings. This function is also
 304  * called for machine sleep. This does not include the MMU
 305  * setup, BATs, etc... but rather the "special" registers
 306  * like HID0, HID1, MSSCR0, etc...
 307  */
 308 _GLOBAL(__save_cpu_setup)
 309         /* Some CR fields are volatile, we back it up all */
 310         mfcr    r7
 311
 312         /* Get storage ptr */
 313         lis     r5,cpu_state_storage@h
 314         ori     r5,r5,cpu_state_storage@l
 315
 316         /* Save HID0 (common to all CONFIG_6xx cpus) */
 317         mfspr   r3,SPRN_HID0
 318         stw     r3,CS_HID0(r5)
 319
 320         /* Now deal with CPU type dependent registers */
 321         mfspr   r3,SPRN_PVR
 322         srwi    r3,r3,16
 323         cmplwi  cr0,r3,0x8000   /* 7450 */
 324         cmplwi  cr1,r3,0x000c   /* 7400 */
 325         cmplwi  cr2,r3,0x800c   /* 7410 */
 326         cmplwi  cr3,r3,0x8001   /* 7455 */
 327         cmplwi  cr4,r3,0x8002   /* 7457 */
 328         cmplwi  cr5,r3,0x8003   /* 7447A */
 329         cmplwi  cr6,r3,0x7000   /* 750FX */
 330         cmplwi  cr7,r3,0x8004   /* 7448 */
 331         /* cr1 is 7400 || 7410 */
 332         cror    4*cr1+eq,4*cr1+eq,4*cr2+eq
 333         /* cr0 is 74xx */
 334         cror    4*cr0+eq,4*cr0+eq,4*cr3+eq
 335         cror    4*cr0+eq,4*cr0+eq,4*cr4+eq
 336         cror    4*cr0+eq,4*cr0+eq,4*cr1+eq
 337         cror    4*cr0+eq,4*cr0+eq,4*cr5+eq
 338         cror    4*cr0+eq,4*cr0+eq,4*cr7+eq
 339         bne     1f
 340         /* Backup 74xx specific regs */
 341         mfspr   r4,SPRN_MSSCR0
 342         stw     r4,CS_MSSCR0(r5)
 343         mfspr   r4,SPRN_MSSSR0
 344         stw     r4,CS_MSSSR0(r5)
 345         beq     cr1,1f
 346         /* Backup 745x specific registers */
 347         mfspr   r4,SPRN_HID1
 348         stw     r4,CS_HID1(r5)
 349         mfspr   r4,SPRN_ICTRL
 350         stw     r4,CS_ICTRL(r5)
 351         mfspr   r4,SPRN_LDSTCR
 352         stw     r4,CS_LDSTCR(r5)
 353         mfspr   r4,SPRN_LDSTDB
 354         stw     r4,CS_LDSTDB(r5)
 355 1:
 356         bne     cr6,1f
 357         /* Backup 750FX specific registers */
 358         mfspr   r4,SPRN_HID1
 359         stw     r4,CS_HID1(r5)
 360         /* If rev 2.x, backup HID2 */
 361         mfspr   r3,SPRN_PVR
 362         andi.   r3,r3,0xff00
 363         cmpwi   cr0,r3,0x0200
 364         bne     1f
 365         mfspr   r4,SPRN_HID2
 366         stw     r4,CS_HID2(r5)
 367 1:
 368         mtcr    r7
 369         blr
 370
 371 /* Called with no MMU context (typically MSR:IR/DR off) to
 372  * restore CPU state as backed up by the previous
 373  * function. This does not include cache setting
 374  */
 375 _GLOBAL(__restore_cpu_setup)
 376         /* Some CR fields are volatile, we back it up all */
 377         mfcr    r7
 378
 379         /* Get storage ptr */
 380         lis     r5,(cpu_state_storage-KERNELBASE)@h
 381         ori     r5,r5,cpu_state_storage@l
 382
 383         /* Restore HID0 */
 384         lwz     r3,CS_HID0(r5)
 385         sync
 386         isync
 387         mtspr   SPRN_HID0,r3
 388         sync
 389         isync
 390
 391         /* Now deal with CPU type dependent registers */
 392         mfspr   r3,SPRN_PVR
 393         srwi    r3,r3,16
 394         cmplwi  cr0,r3,0x8000   /* 7450 */
 395         cmplwi  cr1,r3,0x000c   /* 7400 */
 396         cmplwi  cr2,r3,0x800c   /* 7410 */
 397         cmplwi  cr3,r3,0x8001   /* 7455 */
 398         cmplwi  cr4,r3,0x8002   /* 7457 */
 399         cmplwi  cr5,r3,0x8003   /* 7447A */
 400         cmplwi  cr6,r3,0x7000   /* 750FX */
 401         cmplwi  cr7,r3,0x8004   /* 7448 */
 402         /* cr1 is 7400 || 7410 */
 403         cror    4*cr1+eq,4*cr1+eq,4*cr2+eq
 404         /* cr0 is 74xx */
 405         cror    4*cr0+eq,4*cr0+eq,4*cr3+eq
 406         cror    4*cr0+eq,4*cr0+eq,4*cr4+eq
 407         cror    4*cr0+eq,4*cr0+eq,4*cr1+eq
 408         cror    4*cr0+eq,4*cr0+eq,4*cr5+eq
 409         cror    4*cr0+eq,4*cr0+eq,4*cr7+eq
 410         bne     2f
 411         /* Restore 74xx specific regs */
 412         lwz     r4,CS_MSSCR0(r5)
 413         sync
 414         mtspr   SPRN_MSSCR0,r4
 415         sync
 416         isync
 417         lwz     r4,CS_MSSSR0(r5)
 418         sync
 419         mtspr   SPRN_MSSSR0,r4
 420         sync
 421         isync
 422         bne     cr2,1f
 423         /* Clear 7410 L2CR2 */
 424         li      r4,0
 425         mtspr   SPRN_L2CR2,r4
 426 1:      beq     cr1,2f
 427         /* Restore 745x specific registers */
 428         lwz     r4,CS_HID1(r5)
 429         sync
 430         mtspr   SPRN_HID1,r4
 431         isync
 432         sync
 433         lwz     r4,CS_ICTRL(r5)
 434         sync
 435         mtspr   SPRN_ICTRL,r4
 436         isync
 437         sync
 438         lwz     r4,CS_LDSTCR(r5)
 439         sync
 440         mtspr   SPRN_LDSTCR,r4
 441         isync
 442         sync
 443         lwz     r4,CS_LDSTDB(r5)
 444         sync
 445         mtspr   SPRN_LDSTDB,r4
 446         isync
 447         sync
 448 2:      bne     cr6,1f
 449         /* Restore 750FX specific registers
 450          * that is restore HID2 on rev 2.x and PLL config & switch
 451          * to PLL 0 on all
 452          */
 453         /* If rev 2.x, restore HID2 with low voltage bit cleared */
 454         mfspr   r3,SPRN_PVR
 455         andi.   r3,r3,0xff00
 456         cmpwi   cr0,r3,0x0200
 457         bne     4f
 458         lwz     r4,CS_HID2(r5)
 459         rlwinm  r4,r4,0,19,17
 460         mtspr   SPRN_HID2,r4
 461         sync
 462 4:
 463         lwz     r4,CS_HID1(r5)
 464         rlwinm  r5,r4,0,16,14
 465         mtspr   SPRN_HID1,r5
 466                 /* Wait for PLL to stabilize */
 467         mftbl   r5
 468 3:      mftbl   r6
 469         sub     r6,r6,r5
 470         cmplwi  cr0,r6,10000
 471         ble     3b
 472         /* Setup final PLL */
 473         mtspr   SPRN_HID1,r4
 474 1:
 475         mtcr    r7
 476         blr
 477