arch/ppc/mm/hashtable.S

   1 /*
   2  *  $Id: hashtable.S,v 1.6 1999/10/08 01:56:15 paulus Exp $
   3  *
   4  *  PowerPC version
   5  *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
   6  *  Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
   7  *    Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
   8  *  Adapted for Power Macintosh by Paul Mackerras.
   9  *  Low-level exception handlers and MMU support
  10  *  rewritten by Paul Mackerras.
  11  *    Copyright (C) 1996 Paul Mackerras.
  12  *
  13  *  This file contains low-level assembler routines for managing
  14  *  the PowerPC MMU hash table.  (PPC 8xx processors don't use a
  15  *  hash table, so this file is not used on them.)
  16  *
  17  *  This program is free software; you can redistribute it and/or
  18  *  modify it under the terms of the GNU General Public License
  19  *  as published by the Free Software Foundation; either version
  20  *  2 of the License, or (at your option) any later version.
  21  *
  22  */
  23
  24 #include <linux/config.h>
  25 #include <asm/processor.h>
  26 #include <asm/page.h>
  27 #include <asm/pgtable.h>
  28 #include <asm/cputable.h>
  29 #include <asm/ppc_asm.h>
  30 #include <asm/thread_info.h>
  31 #include <asm/asm-offsets.h>
  32
  33 #ifdef CONFIG_SMP
  34         .comm   mmu_hash_lock,4
  35 #endif /* CONFIG_SMP */
  36
  37 /*
  38  * Sync CPUs with hash_page taking & releasing the hash
  39  * table lock
  40  */
  41 #ifdef CONFIG_SMP
  42         .text
  43 _GLOBAL(hash_page_sync)
  44         lis     r8,mmu_hash_lock@h
  45         ori     r8,r8,mmu_hash_lock@l
  46         lis     r0,0x0fff
  47         b       10f
  48 11:     lwz     r6,0(r8)
  49         cmpwi   0,r6,0
  50         bne     11b
  51 10:     lwarx   r6,0,r8
  52         cmpwi   0,r6,0
  53         bne-    11b
  54         stwcx.  r0,0,r8
  55         bne-    10b
  56         isync
  57         eieio
  58         li      r0,0
  59         stw     r0,0(r8)
  60         blr
  61 #endif
  62
  63 /*
  64  * Load a PTE into the hash table, if possible.
  65  * The address is in r4, and r3 contains an access flag:
  66  * _PAGE_RW (0x400) if a write.
  67  * r9 contains the SRR1 value, from which we use the MSR_PR bit.
  68  * SPRG3 contains the physical address of the current task's thread.
  69  *
  70  * Returns to the caller if the access is illegal or there is no
  71  * mapping for the address.  Otherwise it places an appropriate PTE
  72  * in the hash table and returns from the exception.
  73  * Uses r0, r3 - r8, ctr, lr.
  74  */
  75         .text
  76 _GLOBAL(hash_page)
  77 #ifdef CONFIG_PPC64BRIDGE
  78         mfmsr   r0
  79         clrldi  r0,r0,1         /* make sure it's in 32-bit mode */
  80         MTMSRD(r0)
  81         isync
  82 #endif
  83         tophys(r7,0)                    /* gets -KERNELBASE into r7 */
  84 #ifdef CONFIG_SMP
  85         addis   r8,r7,mmu_hash_lock@h
  86         ori     r8,r8,mmu_hash_lock@l
  87         lis     r0,0x0fff
  88         b       10f
  89 11:     lwz     r6,0(r8)
  90         cmpwi   0,r6,0
  91         bne     11b
  92 10:     lwarx   r6,0,r8
  93         cmpwi   0,r6,0
  94         bne-    11b
  95         stwcx.  r0,0,r8
  96         bne-    10b
  97         isync
  98 #endif
  99         /* Get PTE (linux-style) and check access */
 100         lis     r0,KERNELBASE@h         /* check if kernel address */
 101         cmplw   0,r4,r0
 102         mfspr   r8,SPRN_SPRG3           /* current task's THREAD (phys) */
 103         ori     r3,r3,_PAGE_USER|_PAGE_PRESENT /* test low addresses as user */
 104         lwz     r5,PGDIR(r8)            /* virt page-table root */
 105         blt+    112f                    /* assume user more likely */
 106         lis     r5,swapper_pg_dir@ha    /* if kernel address, use */
 107         addi    r5,r5,swapper_pg_dir@l  /* kernel page table */
 108         rlwimi  r3,r9,32-12,29,29       /* MSR_PR -> _PAGE_USER */
 109 112:    add     r5,r5,r7                /* convert to phys addr */
 110         rlwimi  r5,r4,12,20,29          /* insert top 10 bits of address */
 111         lwz     r8,0(r5)                /* get pmd entry */
 112         rlwinm. r8,r8,0,0,19            /* extract address of pte page */
 113 #ifdef CONFIG_SMP
 114         beq-    hash_page_out           /* return if no mapping */
 115 #else
 116         /* XXX it seems like the 601 will give a machine fault on the
 117            rfi if its alignment is wrong (bottom 4 bits of address are
 118            8 or 0xc) and we have had a not-taken conditional branch
 119            to the address following the rfi. */
 120         beqlr-
 121 #endif
 122         rlwimi  r8,r4,22,20,29          /* insert next 10 bits of address */
 123         rlwinm  r0,r3,32-3,24,24        /* _PAGE_RW access -> _PAGE_DIRTY */
 124         ori     r0,r0,_PAGE_ACCESSED|_PAGE_HASHPTE
 125
 126         /*
 127          * Update the linux PTE atomically.  We do the lwarx up-front
 128          * because almost always, there won't be a permission violation
 129          * and there won't already be an HPTE, and thus we will have
 130          * to update the PTE to set _PAGE_HASHPTE.  -- paulus.
 131          */
 132 retry:
 133         lwarx   r6,0,r8                 /* get linux-style pte */
 134         andc.   r5,r3,r6                /* check access & ~permission */
 135 #ifdef CONFIG_SMP
 136         bne-    hash_page_out           /* return if access not permitted */
 137 #else
 138         bnelr-
 139 #endif
 140         or      r5,r0,r6                /* set accessed/dirty bits */
 141         stwcx.  r5,0,r8                 /* attempt to update PTE */
 142         bne-    retry                   /* retry if someone got there first */
 143
 144         mfsrin  r3,r4                   /* get segment reg for segment */
 145         mfctr   r0
 146         stw     r0,_CTR(r11)
 147         bl      create_hpte             /* add the hash table entry */
 148
 149 /*
 150  * htab_reloads counts the number of times we have to fault an
 151  * HPTE into the hash table.  This should only happen after a
 152  * fork (because fork does a flush_tlb_mm) or a vmalloc or ioremap.
 153  * Where a page is faulted into a process's address space,
 154  * update_mmu_cache gets called to put the HPTE into the hash table
 155  * and those are counted as preloads rather than reloads.
 156  */
 157         addis   r8,r7,htab_reloads@ha
 158         lwz     r3,htab_reloads@l(r8)
 159         addi    r3,r3,1
 160         stw     r3,htab_reloads@l(r8)
 161
 162 #ifdef CONFIG_SMP
 163         eieio
 164         addis   r8,r7,mmu_hash_lock@ha
 165         li      r0,0
 166         stw     r0,mmu_hash_lock@l(r8)
 167 #endif
 168
 169         /* Return from the exception */
 170         lwz     r5,_CTR(r11)
 171         mtctr   r5
 172         lwz     r0,GPR0(r11)
 173         lwz     r7,GPR7(r11)
 174         lwz     r8,GPR8(r11)
 175         b       fast_exception_return
 176
 177 #ifdef CONFIG_SMP
 178 hash_page_out:
 179         eieio
 180         addis   r8,r7,mmu_hash_lock@ha
 181         li      r0,0
 182         stw     r0,mmu_hash_lock@l(r8)
 183         blr
 184 #endif /* CONFIG_SMP */
 185
 186 /*
 187  * Add an entry for a particular page to the hash table.
 188  *
 189  * add_hash_page(unsigned context, unsigned long va, unsigned long pmdval)
 190  *
 191  * We assume any necessary modifications to the pte (e.g. setting
 192  * the accessed bit) have already been done and that there is actually
 193  * a hash table in use (i.e. we're not on a 603).
 194  */
 195 _GLOBAL(add_hash_page)
 196         mflr    r0
 197         stw     r0,4(r1)
 198
 199         /* Convert context and va to VSID */
 200         mulli   r3,r3,897*16            /* multiply context by context skew */
 201         rlwinm  r0,r4,4,28,31           /* get ESID (top 4 bits of va) */
 202         mulli   r0,r0,0x111             /* multiply by ESID skew */
 203         add     r3,r3,r0                /* note create_hpte trims to 24 bits */
 204
 205 #ifdef CONFIG_SMP
 206         rlwinm  r8,r1,0,0,18            /* use cpu number to make tag */
 207         lwz     r8,TI_CPU(r8)           /* to go in mmu_hash_lock */
 208         oris    r8,r8,12
 209 #endif /* CONFIG_SMP */
 210
 211         /*
 212          * We disable interrupts here, even on UP, because we don't
 213          * want to race with hash_page, and because we want the
 214          * _PAGE_HASHPTE bit to be a reliable indication of whether
 215          * the HPTE exists (or at least whether one did once).
 216          * We also turn off the MMU for data accesses so that we
 217          * we can't take a hash table miss (assuming the code is
 218          * covered by a BAT).  -- paulus
 219          */
 220         mfmsr   r10
 221         SYNC
 222         rlwinm  r0,r10,0,17,15          /* clear bit 16 (MSR_EE) */
 223         rlwinm  r0,r0,0,28,26           /* clear MSR_DR */
 224         mtmsr   r0
 225         SYNC_601
 226         isync
 227
 228         tophys(r7,0)
 229
 230 #ifdef CONFIG_SMP
 231         addis   r9,r7,mmu_hash_lock@ha
 232         addi    r9,r9,mmu_hash_lock@l
 233 10:     lwarx   r0,0,r9                 /* take the mmu_hash_lock */
 234         cmpi    0,r0,0
 235         bne-    11f
 236         stwcx.  r8,0,r9
 237         beq+    12f
 238 11:     lwz     r0,0(r9)
 239         cmpi    0,r0,0
 240         beq     10b
 241         b       11b
 242 12:     isync
 243 #endif
 244
 245         /*
 246          * Fetch the linux pte and test and set _PAGE_HASHPTE atomically.
 247          * If _PAGE_HASHPTE was already set, we don't replace the existing
 248          * HPTE, so we just unlock and return.
 249          */
 250         mr      r8,r5
 251         rlwimi  r8,r4,22,20,29
 252 1:      lwarx   r6,0,r8
 253         andi.   r0,r6,_PAGE_HASHPTE
 254         bne     9f                      /* if HASHPTE already set, done */
 255         ori     r5,r6,_PAGE_HASHPTE
 256         stwcx.  r5,0,r8
 257         bne-    1b
 258
 259         bl      create_hpte
 260
 261         addis   r8,r7,htab_preloads@ha
 262         lwz     r3,htab_preloads@l(r8)
 263         addi    r3,r3,1
 264         stw     r3,htab_preloads@l(r8)
 265
 266 9:
 267 #ifdef CONFIG_SMP
 268         eieio
 269         li      r0,0
 270         stw     r0,0(r9)                /* clear mmu_hash_lock */
 271 #endif
 272
 273         /* reenable interrupts and DR */
 274         mtmsr   r10
 275         SYNC_601
 276         isync
 277
 278         lwz     r0,4(r1)
 279         mtlr    r0
 280         blr
 281
 282 /*
 283  * This routine adds a hardware PTE to the hash table.
 284  * It is designed to be called with the MMU either on or off.
 285  * r3 contains the VSID, r4 contains the virtual address,
 286  * r5 contains the linux PTE, r6 contains the old value of the
 287  * linux PTE (before setting _PAGE_HASHPTE) and r7 contains the
 288  * offset to be added to addresses (0 if the MMU is on,
 289  * -KERNELBASE if it is off).
 290  * On SMP, the caller should have the mmu_hash_lock held.
 291  * We assume that the caller has (or will) set the _PAGE_HASHPTE
 292  * bit in the linux PTE in memory.  The value passed in r6 should
 293  * be the old linux PTE value; if it doesn't have _PAGE_HASHPTE set
 294  * this routine will skip the search for an existing HPTE.
 295  * This procedure modifies r0, r3 - r6, r8, cr0.
 296  *  -- paulus.
 297  *
 298  * For speed, 4 of the instructions get patched once the size and
 299  * physical address of the hash table are known.  These definitions
 300  * of Hash_base and Hash_bits below are just an example.
 301  */
 302 Hash_base = 0xc0180000
 303 Hash_bits = 12                          /* e.g. 256kB hash table */
 304 Hash_msk = (((1 << Hash_bits) - 1) * 64)
 305
 306 #ifndef CONFIG_PPC64BRIDGE
 307 /* defines for the PTE format for 32-bit PPCs */
 308 #define PTE_SIZE        8
 309 #define PTEG_SIZE       64
 310 #define LG_PTEG_SIZE    6
 311 #define LDPTEu          lwzu
 312 #define STPTE           stw
 313 #define CMPPTE          cmpw
 314 #define PTE_H           0x40
 315 #define PTE_V           0x80000000
 316 #define TST_V(r)        rlwinm. r,r,0,0,0
 317 #define SET_V(r)        oris r,r,PTE_V@h
 318 #define CLR_V(r,t)      rlwinm r,r,0,1,31
 319
 320 #else
 321 /* defines for the PTE format for 64-bit PPCs */
 322 #define PTE_SIZE        16
 323 #define PTEG_SIZE       128
 324 #define LG_PTEG_SIZE    7
 325 #define LDPTEu          ldu
 326 #define STPTE           std
 327 #define CMPPTE          cmpd
 328 #define PTE_H           2
 329 #define PTE_V           1
 330 #define TST_V(r)        andi. r,r,PTE_V
 331 #define SET_V(r)        ori r,r,PTE_V
 332 #define CLR_V(r,t)      li t,PTE_V; andc r,r,t
 333 #endif /* CONFIG_PPC64BRIDGE */
 334
 335 #define HASH_LEFT       31-(LG_PTEG_SIZE+Hash_bits-1)
 336 #define HASH_RIGHT      31-LG_PTEG_SIZE
 337
 338 _GLOBAL(create_hpte)
 339         /* Convert linux-style PTE (r5) to low word of PPC-style PTE (r8) */
 340         rlwinm  r8,r5,32-10,31,31       /* _PAGE_RW -> PP lsb */
 341         rlwinm  r0,r5,32-7,31,31        /* _PAGE_DIRTY -> PP lsb */
 342         and     r8,r8,r0                /* writable if _RW & _DIRTY */
 343         rlwimi  r5,r5,32-1,30,30        /* _PAGE_USER -> PP msb */
 344         rlwimi  r5,r5,32-2,31,31        /* _PAGE_USER -> PP lsb */
 345         ori     r8,r8,0xe14             /* clear out reserved bits and M */
 346         andc    r8,r5,r8                /* PP = user? (rw&dirty? 2: 3): 0 */
 347 BEGIN_FTR_SECTION
 348         ori     r8,r8,_PAGE_COHERENT    /* set M (coherence required) */
 349 END_FTR_SECTION_IFSET(CPU_FTR_NEED_COHERENT)
 350
 351         /* Construct the high word of the PPC-style PTE (r5) */
 352 #ifndef CONFIG_PPC64BRIDGE
 353         rlwinm  r5,r3,7,1,24            /* put VSID in 0x7fffff80 bits */
 354         rlwimi  r5,r4,10,26,31          /* put in API (abbrev page index) */
 355 #else /* CONFIG_PPC64BRIDGE */
 356         clrlwi  r3,r3,8                 /* reduce vsid to 24 bits */
 357         sldi    r5,r3,12                /* shift vsid into position */
 358         rlwimi  r5,r4,16,20,24          /* put in API (abbrev page index) */
 359 #endif /* CONFIG_PPC64BRIDGE */
 360         SET_V(r5)                       /* set V (valid) bit */
 361
 362         /* Get the address of the primary PTE group in the hash table (r3) */
 363 _GLOBAL(hash_page_patch_A)
 364         addis   r0,r7,Hash_base@h       /* base address of hash table */
 365         rlwimi  r0,r3,LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT    /* VSID -> hash */
 366         rlwinm  r3,r4,20+LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* PI -> hash */
 367         xor     r3,r3,r0                /* make primary hash */
 368         li      r0,8                    /* PTEs/group */
 369
 370         /*
 371          * Test the _PAGE_HASHPTE bit in the old linux PTE, and skip the search
 372          * if it is clear, meaning that the HPTE isn't there already...
 373          */
 374         andi.   r6,r6,_PAGE_HASHPTE
 375         beq+    10f                     /* no PTE: go look for an empty slot */
 376         tlbie   r4
 377
 378         addis   r4,r7,htab_hash_searches@ha
 379         lwz     r6,htab_hash_searches@l(r4)
 380         addi    r6,r6,1                 /* count how many searches we do */
 381         stw     r6,htab_hash_searches@l(r4)
 382
 383         /* Search the primary PTEG for a PTE whose 1st (d)word matches r5 */
 384         mtctr   r0
 385         addi    r4,r3,-PTE_SIZE
 386 1:      LDPTEu  r6,PTE_SIZE(r4)         /* get next PTE */
 387         CMPPTE  0,r6,r5
 388         bdnzf   2,1b                    /* loop while ctr != 0 && !cr0.eq */
 389         beq+    found_slot
 390
 391         /* Search the secondary PTEG for a matching PTE */
 392         ori     r5,r5,PTE_H             /* set H (secondary hash) bit */
 393 _GLOBAL(hash_page_patch_B)
 394         xoris   r4,r3,Hash_msk>>16      /* compute secondary hash */
 395         xori    r4,r4,(-PTEG_SIZE & 0xffff)
 396         addi    r4,r4,-PTE_SIZE
 397         mtctr   r0
 398 2:      LDPTEu  r6,PTE_SIZE(r4)
 399         CMPPTE  0,r6,r5
 400         bdnzf   2,2b
 401         beq+    found_slot
 402         xori    r5,r5,PTE_H             /* clear H bit again */
 403
 404         /* Search the primary PTEG for an empty slot */
 405 10:     mtctr   r0
 406         addi    r4,r3,-PTE_SIZE         /* search primary PTEG */
 407 1:      LDPTEu  r6,PTE_SIZE(r4)         /* get next PTE */
 408         TST_V(r6)                       /* test valid bit */
 409         bdnzf   2,1b                    /* loop while ctr != 0 && !cr0.eq */
 410         beq+    found_empty
 411
 412         /* update counter of times that the primary PTEG is full */
 413         addis   r4,r7,primary_pteg_full@ha
 414         lwz     r6,primary_pteg_full@l(r4)
 415         addi    r6,r6,1
 416         stw     r6,primary_pteg_full@l(r4)
 417
 418         /* Search the secondary PTEG for an empty slot */
 419         ori     r5,r5,PTE_H             /* set H (secondary hash) bit */
 420 _GLOBAL(hash_page_patch_C)
 421         xoris   r4,r3,Hash_msk>>16      /* compute secondary hash */
 422         xori    r4,r4,(-PTEG_SIZE & 0xffff)
 423         addi    r4,r4,-PTE_SIZE
 424         mtctr   r0
 425 2:      LDPTEu  r6,PTE_SIZE(r4)
 426         TST_V(r6)
 427         bdnzf   2,2b
 428         beq+    found_empty
 429         xori    r5,r5,PTE_H             /* clear H bit again */
 430
 431         /*
 432          * Choose an arbitrary slot in the primary PTEG to overwrite.
 433          * Since both the primary and secondary PTEGs are full, and we
 434          * have no information that the PTEs in the primary PTEG are
 435          * more important or useful than those in the secondary PTEG,
 436          * and we know there is a definite (although small) speed
 437          * advantage to putting the PTE in the primary PTEG, we always
 438          * put the PTE in the primary PTEG.
 439          */
 440         addis   r4,r7,next_slot@ha
 441         lwz     r6,next_slot@l(r4)
 442         addi    r6,r6,PTE_SIZE
 443         andi.   r6,r6,7*PTE_SIZE
 444         stw     r6,next_slot@l(r4)
 445         add     r4,r3,r6
 446
 447         /* update counter of evicted pages */
 448         addis   r6,r7,htab_evicts@ha
 449         lwz     r3,htab_evicts@l(r6)
 450         addi    r3,r3,1
 451         stw     r3,htab_evicts@l(r6)
 452
 453 #ifndef CONFIG_SMP
 454         /* Store PTE in PTEG */
 455 found_empty:
 456         STPTE   r5,0(r4)
 457 found_slot:
 458         STPTE   r8,PTE_SIZE/2(r4)
 459
 460 #else /* CONFIG_SMP */
 461 /*
 462  * Between the tlbie above and updating the hash table entry below,
 463  * another CPU could read the hash table entry and put it in its TLB.
 464  * There are 3 cases:
 465  * 1. using an empty slot
 466  * 2. updating an earlier entry to change permissions (i.e. enable write)
 467  * 3. taking over the PTE for an unrelated address
 468  *
 469  * In each case it doesn't really matter if the other CPUs have the old
 470  * PTE in their TLB.  So we don't need to bother with another tlbie here,
 471  * which is convenient as we've overwritten the register that had the
 472  * address. :-)  The tlbie above is mainly to make sure that this CPU comes
 473  * and gets the new PTE from the hash table.
 474  *
 475  * We do however have to make sure that the PTE is never in an invalid
 476  * state with the V bit set.
 477  */
 478 found_empty:
 479 found_slot:
 480         CLR_V(r5,r0)            /* clear V (valid) bit in PTE */
 481         STPTE   r5,0(r4)
 482         sync
 483         TLBSYNC
 484         STPTE   r8,PTE_SIZE/2(r4) /* put in correct RPN, WIMG, PP bits */
 485         sync
 486         SET_V(r5)
 487         STPTE   r5,0(r4)        /* finally set V bit in PTE */
 488 #endif /* CONFIG_SMP */
 489
 490         sync            /* make sure pte updates get to memory */
 491         blr
 492
 493         .comm   next_slot,4
 494         .comm   primary_pteg_full,4
 495         .comm   htab_hash_searches,4
 496
 497 /*
 498  * Flush the entry for a particular page from the hash table.
 499  *
 500  * flush_hash_pages(unsigned context, unsigned long va, unsigned long pmdval,
 501  *                  int count)
 502  *
 503  * We assume that there is a hash table in use (Hash != 0).
 504  */
 505 _GLOBAL(flush_hash_pages)
 506         tophys(r7,0)
 507
 508         /*
 509          * We disable interrupts here, even on UP, because we want
 510          * the _PAGE_HASHPTE bit to be a reliable indication of
 511          * whether the HPTE exists (or at least whether one did once).
 512          * We also turn off the MMU for data accesses so that we
 513          * we can't take a hash table miss (assuming the code is
 514          * covered by a BAT).  -- paulus
 515          */
 516         mfmsr   r10
 517         SYNC
 518         rlwinm  r0,r10,0,17,15          /* clear bit 16 (MSR_EE) */
 519         rlwinm  r0,r0,0,28,26           /* clear MSR_DR */
 520         mtmsr   r0
 521         SYNC_601
 522         isync
 523
 524         /* First find a PTE in the range that has _PAGE_HASHPTE set */
 525         rlwimi  r5,r4,22,20,29
 526 1:      lwz     r0,0(r5)
 527         cmpwi   cr1,r6,1
 528         andi.   r0,r0,_PAGE_HASHPTE
 529         bne     2f
 530         ble     cr1,19f
 531         addi    r4,r4,0x1000
 532         addi    r5,r5,4
 533         addi    r6,r6,-1
 534         b       1b
 535
 536         /* Convert context and va to VSID */
 537 2:      mulli   r3,r3,897*16            /* multiply context by context skew */
 538         rlwinm  r0,r4,4,28,31           /* get ESID (top 4 bits of va) */
 539         mulli   r0,r0,0x111             /* multiply by ESID skew */
 540         add     r3,r3,r0                /* note code below trims to 24 bits */
 541
 542         /* Construct the high word of the PPC-style PTE (r11) */
 543 #ifndef CONFIG_PPC64BRIDGE
 544         rlwinm  r11,r3,7,1,24           /* put VSID in 0x7fffff80 bits */
 545         rlwimi  r11,r4,10,26,31         /* put in API (abbrev page index) */
 546 #else /* CONFIG_PPC64BRIDGE */
 547         clrlwi  r3,r3,8                 /* reduce vsid to 24 bits */
 548         sldi    r11,r3,12               /* shift vsid into position */
 549         rlwimi  r11,r4,16,20,24         /* put in API (abbrev page index) */
 550 #endif /* CONFIG_PPC64BRIDGE */
 551         SET_V(r11)                      /* set V (valid) bit */
 552
 553 #ifdef CONFIG_SMP
 554         addis   r9,r7,mmu_hash_lock@ha
 555         addi    r9,r9,mmu_hash_lock@l
 556         rlwinm  r8,r1,0,0,18
 557         add     r8,r8,r7
 558         lwz     r8,TI_CPU(r8)
 559         oris    r8,r8,9
 560 10:     lwarx   r0,0,r9
 561         cmpi    0,r0,0
 562         bne-    11f
 563         stwcx.  r8,0,r9
 564         beq+    12f
 565 11:     lwz     r0,0(r9)
 566         cmpi    0,r0,0
 567         beq     10b
 568         b       11b
 569 12:     isync
 570 #endif
 571
 572         /*
 573          * Check the _PAGE_HASHPTE bit in the linux PTE.  If it is
 574          * already clear, we're done (for this pte).  If not,
 575          * clear it (atomically) and proceed.  -- paulus.
 576          */
 577 33:     lwarx   r8,0,r5                 /* fetch the pte */
 578         andi.   r0,r8,_PAGE_HASHPTE
 579         beq     8f                      /* done if HASHPTE is already clear */
 580         rlwinm  r8,r8,0,31,29           /* clear HASHPTE bit */
 581         stwcx.  r8,0,r5                 /* update the pte */
 582         bne-    33b
 583
 584         /* Get the address of the primary PTE group in the hash table (r3) */
 585 _GLOBAL(flush_hash_patch_A)
 586         addis   r8,r7,Hash_base@h       /* base address of hash table */
 587         rlwimi  r8,r3,LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT    /* VSID -> hash */
 588         rlwinm  r0,r4,20+LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* PI -> hash */
 589         xor     r8,r0,r8                /* make primary hash */
 590
 591         /* Search the primary PTEG for a PTE whose 1st (d)word matches r5 */
 592         li      r0,8                    /* PTEs/group */
 593         mtctr   r0
 594         addi    r12,r8,-PTE_SIZE
 595 1:      LDPTEu  r0,PTE_SIZE(r12)        /* get next PTE */
 596         CMPPTE  0,r0,r11
 597         bdnzf   2,1b                    /* loop while ctr != 0 && !cr0.eq */
 598         beq+    3f
 599
 600         /* Search the secondary PTEG for a matching PTE */
 601         ori     r11,r11,PTE_H           /* set H (secondary hash) bit */
 602         li      r0,8                    /* PTEs/group */
 603 _GLOBAL(flush_hash_patch_B)
 604         xoris   r12,r8,Hash_msk>>16     /* compute secondary hash */
 605         xori    r12,r12,(-PTEG_SIZE & 0xffff)
 606         addi    r12,r12,-PTE_SIZE
 607         mtctr   r0
 608 2:      LDPTEu  r0,PTE_SIZE(r12)
 609         CMPPTE  0,r0,r11
 610         bdnzf   2,2b
 611         xori    r11,r11,PTE_H           /* clear H again */
 612         bne-    4f                      /* should rarely fail to find it */
 613
 614 3:      li      r0,0
 615         STPTE   r0,0(r12)               /* invalidate entry */
 616 4:      sync
 617         tlbie   r4                      /* in hw tlb too */
 618         sync
 619
 620 8:      ble     cr1,9f                  /* if all ptes checked */
 621 81:     addi    r6,r6,-1
 622         addi    r5,r5,4                 /* advance to next pte */
 623         addi    r4,r4,0x1000
 624         lwz     r0,0(r5)                /* check next pte */
 625         cmpwi   cr1,r6,1
 626         andi.   r0,r0,_PAGE_HASHPTE
 627         bne     33b
 628         bgt     cr1,81b
 629
 630 9:
 631 #ifdef CONFIG_SMP
 632         TLBSYNC
 633         li      r0,0
 634         stw     r0,0(r9)                /* clear mmu_hash_lock */
 635 #endif
 636
 637 19:     mtmsr   r10
 638         SYNC_601
 639         isync
 640         blr