arch/ppc/platforms/4xx/ibm405gpr.c

   1 /*
   2  * Author: Armin Kuster <akuster@mvista.com>
   3  *
   4  * 2002 (c) MontaVista, Software, Inc.  This file is licensed under
   5  * the terms of the GNU General Public License version 2.  This program
   6  * is licensed "as is" without any warranty of any kind, whether express
   7  * or implied.
   8  */
   9
  10 #include <linux/config.h>
  11 #include <linux/init.h>
  12 #include <linux/smp.h>
  13 #include <linux/threads.h>
  14 #include <linux/param.h>
  15 #include <linux/string.h>
  16 #include <platforms/4xx/ibm405gpr.h>
  17 #include <asm/ibm4xx.h>
  18 #include <asm/ocp.h>
  19 #include <asm/ppc4xx_pic.h>
  20
  21 static struct ocp_func_emac_data ibm405gpr_emac0_def = {
  22         .rgmii_idx      = -1,           /* No RGMII */
  23         .rgmii_mux      = -1,           /* No RGMII */
  24         .zmii_idx       = -1,           /* ZMII device index */
  25         .zmii_mux       = 0,            /* ZMII input of this EMAC */
  26         .mal_idx        = 0,            /* MAL device index */
  27         .mal_rx_chan    = 0,            /* MAL rx channel number */
  28         .mal_tx_chan    = 0,            /* MAL tx channel number */
  29         .wol_irq        = 9,            /* WOL interrupt number */
  30         .mdio_idx       = -1,           /* No shared MDIO */
  31         .tah_idx        = -1,           /* No TAH */
  32 };
  33 OCP_SYSFS_EMAC_DATA()
  34
  35 static struct ocp_func_mal_data ibm405gpr_mal0_def = {
  36         .num_tx_chans   = 1,            /* Number of TX channels */
  37         .num_rx_chans   = 1,            /* Number of RX channels */
  38         .txeob_irq      = 11,           /* TX End Of Buffer IRQ  */
  39         .rxeob_irq      = 12,           /* RX End Of Buffer IRQ  */
  40         .txde_irq       = 13,           /* TX Descriptor Error IRQ */
  41         .rxde_irq       = 14,           /* RX Descriptor Error IRQ */
  42         .serr_irq       = 10,           /* MAL System Error IRQ    */
  43         .dcr_base       = DCRN_MAL_BASE /* MAL0_CFG DCR number */
  44 };
  45 OCP_SYSFS_MAL_DATA()
  46
  47 static struct ocp_func_iic_data ibm405gpr_iic0_def = {
  48         .fast_mode      = 0,            /* Use standad mode (100Khz) */
  49 };
  50
  51 OCP_SYSFS_IIC_DATA()
  52
  53 struct ocp_def core_ocp[] = {
  54         { .vendor       = OCP_VENDOR_IBM,
  55           .function     = OCP_FUNC_OPB,
  56           .index        = 0,
  57           .paddr        = 0xEF600000,
  58           .irq          = OCP_IRQ_NA,
  59           .pm           = OCP_CPM_NA,
  60         },
  61         { .vendor       = OCP_VENDOR_IBM,
  62           .function     = OCP_FUNC_16550,
  63           .index        = 0,
  64           .paddr        = UART0_IO_BASE,
  65           .irq          = UART0_INT,
  66           .pm           = IBM_CPM_UART0
  67         },
  68         { .vendor       = OCP_VENDOR_IBM,
  69           .function     = OCP_FUNC_16550,
  70           .index        = 1,
  71           .paddr        = UART1_IO_BASE,
  72           .irq          = UART1_INT,
  73           .pm           = IBM_CPM_UART1
  74         },
  75         { .vendor       = OCP_VENDOR_IBM,
  76           .function     = OCP_FUNC_IIC,
  77           .paddr        = 0xEF600500,
  78           .irq          = 2,
  79           .pm           = IBM_CPM_IIC0,
  80           .additions    = &ibm405gpr_iic0_def,
  81           .show         = &ocp_show_iic_data,
  82         },
  83         { .vendor       = OCP_VENDOR_IBM,
  84           .function     = OCP_FUNC_GPIO,
  85           .paddr        = 0xEF600700,
  86           .irq          = OCP_IRQ_NA,
  87           .pm           = IBM_CPM_GPIO0
  88         },
  89         { .vendor       = OCP_VENDOR_IBM,
  90           .function     = OCP_FUNC_MAL,
  91           .paddr        = OCP_PADDR_NA,
  92           .irq          = OCP_IRQ_NA,
  93           .pm           = OCP_CPM_NA,
  94           .additions    = &ibm405gpr_mal0_def,
  95           .show         = &ocp_show_mal_data,
  96         },
  97         { .vendor       = OCP_VENDOR_IBM,
  98           .function     = OCP_FUNC_EMAC,
  99           .index        = 0,
 100           .paddr        = EMAC0_BASE,
 101           .irq          = 15,
 102           .pm           = IBM_CPM_EMAC0,
 103           .additions    = &ibm405gpr_emac0_def,
 104           .show         = &ocp_show_emac_data,
 105         },
 106         { .vendor       = OCP_VENDOR_INVALID
 107         }
 108 };
 109
 110 /* Polarity and triggering settings for internal interrupt sources */
 111 struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = {
 112         { .polarity     = 0xffffe000,
 113           .triggering   = 0x10000000,
 114           .ext_irq_mask = 0x00001fff,   /* IRQ7 - IRQ12, IRQ0 - IRQ6 */
 115         }
 116 };