arch/ppc/platforms/4xx/yucca.c

   1 /*
   2  * Yucca board specific routines
   3  *
   4  * Roland Dreier <rolandd@cisco.com> (based on luan.c by Matt Porter)
   5  *
   6  * Copyright 2004-2005 MontaVista Software Inc.
   7  * Copyright (c) 2005 Cisco Systems.  All rights reserved.
   8  *
   9  * This program is free software; you can redistribute  it and/or modify it
  10  * under  the terms of  the GNU General  Public License as published by the
  11  * Free Software Foundation;  either version 2 of the  License, or (at your
  12  * option) any later version.
  13  */
  14
  15 #include <linux/config.h>
  16 #include <linux/stddef.h>
  17 #include <linux/kernel.h>
  18 #include <linux/init.h>
  19 #include <linux/errno.h>
  20 #include <linux/reboot.h>
  21 #include <linux/pci.h>
  22 #include <linux/kdev_t.h>
  23 #include <linux/types.h>
  24 #include <linux/major.h>
  25 #include <linux/blkdev.h>
  26 #include <linux/console.h>
  27 #include <linux/delay.h>
  28 #include <linux/ide.h>
  29 #include <linux/initrd.h>
  30 #include <linux/seq_file.h>
  31 #include <linux/root_dev.h>
  32 #include <linux/tty.h>
  33 #include <linux/serial.h>
  34 #include <linux/serial_core.h>
  35
  36 #include <asm/system.h>
  37 #include <asm/pgtable.h>
  38 #include <asm/page.h>
  39 #include <asm/dma.h>
  40 #include <asm/io.h>
  41 #include <asm/machdep.h>
  42 #include <asm/ocp.h>
  43 #include <asm/pci-bridge.h>
  44 #include <asm/time.h>
  45 #include <asm/todc.h>
  46 #include <asm/bootinfo.h>
  47 #include <asm/ppc4xx_pic.h>
  48 #include <asm/ppcboot.h>
  49
  50 #include <syslib/ibm44x_common.h>
  51 #include <syslib/ibm440gx_common.h>
  52 #include <syslib/ibm440sp_common.h>
  53 #include <syslib/ppc440spe_pcie.h>
  54
  55 extern bd_t __res;
  56
  57 static struct ibm44x_clocks clocks __initdata;
  58
  59 static void __init
  60 yucca_calibrate_decr(void)
  61 {
  62         unsigned int freq;
  63
  64         if (mfspr(SPRN_CCR1) & CCR1_TCS)
  65                 freq = YUCCA_TMR_CLK;
  66         else
  67                 freq = clocks.cpu;
  68
  69         ibm44x_calibrate_decr(freq);
  70 }
  71
  72 static int
  73 yucca_show_cpuinfo(struct seq_file *m)
  74 {
  75         seq_printf(m, "vendor\t\t: AMCC\n");
  76         seq_printf(m, "machine\t\t: PPC440SPe EVB (Yucca)\n");
  77
  78         return 0;
  79 }
  80
  81 static enum {
  82         HOSE_UNKNOWN,
  83         HOSE_PCIX,
  84         HOSE_PCIE0,
  85         HOSE_PCIE1,
  86         HOSE_PCIE2
  87 } hose_type[4];
  88
  89 static inline int
  90 yucca_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
  91 {
  92         struct pci_controller *hose = pci_bus_to_hose(dev->bus->number);
  93
  94         if (hose_type[hose->index] == HOSE_PCIX) {
  95                 static char pci_irq_table[][4] =
  96                 /*
  97                  *      PCI IDSEL/INTPIN->INTLINE
  98                  *        A   B   C   D
  99                  */
 100                 {
 101                         { 81, -1, -1, -1 },     /* IDSEL 1 - PCIX0 Slot 0 */
 102                 };
 103                 const long min_idsel = 1, max_idsel = 1, irqs_per_slot = 4;
 104                 return PCI_IRQ_TABLE_LOOKUP;
 105         } else if (hose_type[hose->index] == HOSE_PCIE0) {
 106                 static char pci_irq_table[][4] =
 107                 /*
 108                  *      PCI IDSEL/INTPIN->INTLINE
 109                  *        A   B   C   D
 110                  */
 111                 {
 112                         { 96, 97, 98, 99 },
 113                 };
 114                 const long min_idsel = 1, max_idsel = 1, irqs_per_slot = 4;
 115                 return PCI_IRQ_TABLE_LOOKUP;
 116         } else if (hose_type[hose->index] == HOSE_PCIE1) {
 117                 static char pci_irq_table[][4] =
 118                 /*
 119                  *      PCI IDSEL/INTPIN->INTLINE
 120                  *        A   B   C   D
 121                  */
 122                 {
 123                         { 100, 101, 102, 103 },
 124                 };
 125                 const long min_idsel = 1, max_idsel = 1, irqs_per_slot = 4;
 126                 return PCI_IRQ_TABLE_LOOKUP;
 127         } else if (hose_type[hose->index] == HOSE_PCIE2) {
 128                 static char pci_irq_table[][4] =
 129                 /*
 130                  *      PCI IDSEL/INTPIN->INTLINE
 131                  *        A   B   C   D
 132                  */
 133                 {
 134                         { 104, 105, 106, 107 },
 135                 };
 136                 const long min_idsel = 1, max_idsel = 1, irqs_per_slot = 4;
 137                 return PCI_IRQ_TABLE_LOOKUP;
 138         }
 139         return -1;
 140 }
 141
 142 static void __init yucca_set_emacdata(void)
 143 {
 144         struct ocp_def *def;
 145         struct ocp_func_emac_data *emacdata;
 146
 147         /* Set phy_map, phy_mode, and mac_addr for the EMAC */
 148         def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 0);
 149         emacdata = def->additions;
 150         emacdata->phy_map = 0x00000001; /* Skip 0x00 */
 151         emacdata->phy_mode = PHY_MODE_GMII;
 152         memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6);
 153 }
 154
 155 static int __init yucca_pcie_card_present(int port)
 156 {
 157    void __iomem *pcie_fpga_base;
 158    u16 reg;
 159
 160    pcie_fpga_base = ioremap64(YUCCA_FPGA_REG_BASE, YUCCA_FPGA_REG_SIZE);
 161    reg = in_be16(pcie_fpga_base + FPGA_REG1C);
 162    iounmap(pcie_fpga_base);
 163
 164    switch(port) {
 165    case 0: return !(reg & FPGA_REG1C_PE0_PRSNT);
 166    case 1: return !(reg & FPGA_REG1C_PE1_PRSNT);
 167    case 2: return !(reg & FPGA_REG1C_PE2_PRSNT);
 168    default: return 0;
 169    }
 170 }
 171
 172 /*
 173  * For the given slot, set rootpoint mode, send power to the slot,
 174  * turn on the green LED and turn off the yellow LED, enable the clock
 175  * and turn off reset.
 176  */
 177 static void __init yucca_setup_pcie_fpga_rootpoint(int port)
 178 {
 179         void __iomem *pcie_reg_fpga_base;
 180         u16 power, clock, green_led, yellow_led, reset_off, rootpoint, endpoint;
 181
 182         pcie_reg_fpga_base = ioremap64(YUCCA_FPGA_REG_BASE, YUCCA_FPGA_REG_SIZE);
 183
 184         switch(port) {
 185         case 0:
 186                 rootpoint   = FPGA_REG1C_PE0_ROOTPOINT;
 187                 endpoint    = 0;
 188                 power       = FPGA_REG1A_PE0_PWRON;
 189                 green_led   = FPGA_REG1A_PE0_GLED;
 190                 clock       = FPGA_REG1A_PE0_REFCLK_ENABLE;
 191                 yellow_led  = FPGA_REG1A_PE0_YLED;
 192                 reset_off   = FPGA_REG1C_PE0_PERST;
 193                 break;
 194         case 1:
 195                 rootpoint   = 0;
 196                 endpoint    = FPGA_REG1C_PE1_ENDPOINT;
 197                 power       = FPGA_REG1A_PE1_PWRON;
 198                 green_led   = FPGA_REG1A_PE1_GLED;
 199                 clock       = FPGA_REG1A_PE1_REFCLK_ENABLE;
 200                 yellow_led  = FPGA_REG1A_PE1_YLED;
 201                 reset_off   = FPGA_REG1C_PE1_PERST;
 202                 break;
 203         case 2:
 204                 rootpoint   = 0;
 205                 endpoint    = FPGA_REG1C_PE2_ENDPOINT;
 206                 power       = FPGA_REG1A_PE2_PWRON;
 207                 green_led   = FPGA_REG1A_PE2_GLED;
 208                 clock       = FPGA_REG1A_PE2_REFCLK_ENABLE;
 209                 yellow_led  = FPGA_REG1A_PE2_YLED;
 210                 reset_off   = FPGA_REG1C_PE2_PERST;
 211                 break;
 212
 213         default:
 214                 return;
 215         }
 216
 217         out_be16(pcie_reg_fpga_base + FPGA_REG1A,
 218                  ~(power | clock | green_led) &
 219                  (yellow_led | in_be16(pcie_reg_fpga_base + FPGA_REG1A)));
 220         out_be16(pcie_reg_fpga_base + FPGA_REG1C,
 221                  ~(endpoint | reset_off) &
 222                  (rootpoint | in_be16(pcie_reg_fpga_base + FPGA_REG1C)));
 223
 224         /*
 225          * Leave device in reset for a while after powering on the
 226          * slot to give it a chance to initialize.
 227          */
 228         mdelay(250);
 229
 230         out_be16(pcie_reg_fpga_base + FPGA_REG1C,
 231                  reset_off | in_be16(pcie_reg_fpga_base + FPGA_REG1C));
 232
 233         iounmap(pcie_reg_fpga_base);
 234 }
 235
 236 static void __init
 237 yucca_setup_hoses(void)
 238 {
 239         struct pci_controller *hose;
 240         char name[20];
 241         int i;
 242
 243         if (0 && ppc440spe_init_pcie()) {
 244                 printk(KERN_WARNING "PPC440SPe PCI Express initialization failed\n");
 245                 return;
 246         }
 247
 248         for (i = 0; i <= 2; ++i) {
 249                 if (!yucca_pcie_card_present(i))
 250                         continue;
 251
 252                 printk(KERN_INFO "PCIE%d: card present\n", i);
 253                 yucca_setup_pcie_fpga_rootpoint(i);
 254                 if (ppc440spe_init_pcie_rootport(i)) {
 255                         printk(KERN_WARNING "PCIE%d: initialization failed\n", i);
 256                         continue;
 257                 }
 258
 259                 hose = pcibios_alloc_controller();
 260                 if (!hose)
 261                         return;
 262
 263                 sprintf(name, "PCIE%d host bridge", i);
 264                 pci_init_resource(&hose->io_resource,
 265                                   YUCCA_PCIX_LOWER_IO,
 266                                   YUCCA_PCIX_UPPER_IO,
 267                                   IORESOURCE_IO,
 268                                   name);
 269
 270                 hose->mem_space.start = YUCCA_PCIE_LOWER_MEM +
 271                         i * YUCCA_PCIE_MEM_SIZE;
 272                 hose->mem_space.end   = hose->mem_space.start +
 273                         YUCCA_PCIE_MEM_SIZE - 1;
 274
 275                 pci_init_resource(&hose->mem_resources[0],
 276                                   hose->mem_space.start,
 277                                   hose->mem_space.end,
 278                                   IORESOURCE_MEM,
 279                                   name);
 280
 281                 hose->first_busno = 0;
 282                 hose->last_busno  = 15;
 283                 hose_type[hose->index] = HOSE_PCIE0 + i;
 284
 285                 ppc440spe_setup_pcie(hose, i);
 286                 hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
 287         }
 288
 289         ppc_md.pci_swizzle = common_swizzle;
 290         ppc_md.pci_map_irq = yucca_map_irq;
 291 }
 292
 293 TODC_ALLOC();
 294
 295 static void __init
 296 yucca_early_serial_map(void)
 297 {
 298         struct uart_port port;
 299
 300         /* Setup ioremapped serial port access */
 301         memset(&port, 0, sizeof(port));
 302         port.membase = ioremap64(PPC440SPE_UART0_ADDR, 8);
 303         port.irq = UART0_INT;
 304         port.uartclk = clocks.uart0;
 305         port.regshift = 0;
 306         port.iotype = UPIO_MEM;
 307         port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
 308         port.line = 0;
 309
 310         if (early_serial_setup(&port) != 0) {
 311                 printk("Early serial init of port 0 failed\n");
 312         }
 313
 314         port.membase = ioremap64(PPC440SPE_UART1_ADDR, 8);
 315         port.irq = UART1_INT;
 316         port.uartclk = clocks.uart1;
 317         port.line = 1;
 318
 319         if (early_serial_setup(&port) != 0) {
 320                 printk("Early serial init of port 1 failed\n");
 321         }
 322
 323         port.membase = ioremap64(PPC440SPE_UART2_ADDR, 8);
 324         port.irq = UART2_INT;
 325         port.uartclk = BASE_BAUD;
 326         port.line = 2;
 327
 328         if (early_serial_setup(&port) != 0) {
 329                 printk("Early serial init of port 2 failed\n");
 330         }
 331 }
 332
 333 static void __init
 334 yucca_setup_arch(void)
 335 {
 336         yucca_set_emacdata();
 337
 338 #if !defined(CONFIG_BDI_SWITCH)
 339         /*
 340          * The Abatron BDI JTAG debugger does not tolerate others
 341          * mucking with the debug registers.
 342          */
 343         mtspr(SPRN_DBCR0, (DBCR0_TDE | DBCR0_IDM));
 344 #endif
 345
 346         /*
 347          * Determine various clocks.
 348          * To be completely correct we should get SysClk
 349          * from FPGA, because it can be changed by on-board switches
 350          * --ebs
 351          */
 352         /* 440GX and 440SPe clocking is the same - rd */
 353         ibm440gx_get_clocks(&clocks, 33333333, 6 * 1843200);
 354         ocp_sys_info.opb_bus_freq = clocks.opb;
 355
 356         /* init to some ~sane value until calibrate_delay() runs */
 357         loops_per_jiffy = 50000000/HZ;
 358
 359         /* Setup PCIXn host bridges */
 360         yucca_setup_hoses();
 361
 362 #ifdef CONFIG_BLK_DEV_INITRD
 363         if (initrd_start)
 364                 ROOT_DEV = Root_RAM0;
 365         else
 366 #endif
 367 #ifdef CONFIG_ROOT_NFS
 368                 ROOT_DEV = Root_NFS;
 369 #else
 370                 ROOT_DEV = Root_HDA1;
 371 #endif
 372
 373         yucca_early_serial_map();
 374
 375         /* Identify the system */
 376         printk("Yucca port (Roland Dreier <rolandd@cisco.com>)\n");
 377 }
 378
 379 void __init platform_init(unsigned long r3, unsigned long r4,
 380                 unsigned long r5, unsigned long r6, unsigned long r7)
 381 {
 382         ibm44x_platform_init(r3, r4, r5, r6, r7);
 383
 384         ppc_md.setup_arch = yucca_setup_arch;
 385         ppc_md.show_cpuinfo = yucca_show_cpuinfo;
 386         ppc_md.find_end_of_memory = ibm440sp_find_end_of_memory;
 387         ppc_md.get_irq = NULL;          /* Set in ppc4xx_pic_init() */
 388
 389         ppc_md.calibrate_decr = yucca_calibrate_decr;
 390 #ifdef CONFIG_KGDB
 391         ppc_md.early_serial_map = yucca_early_serial_map;
 392 #endif
 393 }