2 * TQM85xx (40/41/55/60) board specific routines
4 * Copyright (c) 2005 DENX Software Engineering
5 * Stefan Roese <sr@denx.de>
7 * Based on original work by
8 * Kumar Gala <galak@kernel.crashing.org>
9 * Copyright 2004 Freescale Semiconductor Inc.
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
17 #include <linux/config.h>
18 #include <linux/stddef.h>
19 #include <linux/kernel.h>
20 #include <linux/init.h>
21 #include <linux/errno.h>
22 #include <linux/reboot.h>
23 #include <linux/pci.h>
24 #include <linux/kdev_t.h>
25 #include <linux/major.h>
26 #include <linux/console.h>
27 #include <linux/delay.h>
28 #include <linux/seq_file.h>
29 #include <linux/root_dev.h>
30 #include <linux/serial.h>
31 #include <linux/tty.h> /* for linux/serial_core.h */
32 #include <linux/serial_core.h>
33 #include <linux/initrd.h>
34 #include <linux/module.h>
35 #include <linux/fsl_devices.h>
37 #include <asm/system.h>
38 #include <asm/pgtable.h>
40 #include <asm/atomic.h>
43 #include <asm/machdep.h>
44 #include <asm/open_pic.h>
45 #include <asm/bootinfo.h>
46 #include <asm/pci-bridge.h>
47 #include <asm/mpc85xx.h>
49 #include <asm/immap_85xx.h>
51 #include <asm/ppc_sys.h>
53 #include <mm/mmu_decl.h>
55 #include <syslib/ppc85xx_setup.h>
56 #include <syslib/cpm2_pic.h>
57 #include <syslib/ppc85xx_common.h>
58 #include <syslib/ppc85xx_rio.h>
61 unsigned long isa_io_base
= 0;
62 unsigned long isa_mem_base
= 0;
66 extern unsigned long total_memory
; /* in mm/init */
68 unsigned char __res
[sizeof (bd_t
)];
70 /* Internal interrupts are all Level Sensitive, and Positive Polarity */
71 static u_char tqm85xx_openpic_initsenses
[] __initdata
= {
72 MPC85XX_INTERNAL_IRQ_SENSES
,
73 0x0, /* External 0: */
74 0x0, /* External 1: */
75 #if defined(CONFIG_PCI)
76 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_NEGATIVE
), /* External 2: PCI INTA */
77 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_NEGATIVE
), /* External 3: PCI INTB */
79 0x0, /* External 2: */
80 0x0, /* External 3: */
82 0x0, /* External 4: */
83 0x0, /* External 5: */
84 0x0, /* External 6: */
85 0x0, /* External 7: */
86 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_NEGATIVE
), /* External 8: PHY */
87 0x0, /* External 9: */
88 0x0, /* External 10: */
89 0x0, /* External 11: */
92 /* ************************************************************************
94 * Setup the architecture
98 tqm85xx_setup_arch(void)
100 bd_t
*binfo
= (bd_t
*) __res
;
102 struct gianfar_platform_data
*pdata
;
103 struct gianfar_mdio_data
*mdata
;
105 #ifdef CONFIG_MPC8560
109 /* get the core frequency */
110 freq
= binfo
->bi_intfreq
;
113 ppc_md
.progress("tqm85xx_setup_arch()", 0);
115 /* Set loops_per_jiffy to a half-way reasonable value,
116 for use until calibrate_delay gets called. */
117 loops_per_jiffy
= freq
/ HZ
;
120 /* setup PCI host bridges */
121 mpc85xx_setup_hose();
124 #ifndef CONFIG_MPC8560
125 #if defined(CONFIG_SERIAL_8250)
126 mpc85xx_early_serial_map();
129 #ifdef CONFIG_SERIAL_TEXT_DEBUG
130 /* Invalidate the entry we stole earlier the serial ports
131 * should be properly mapped */
132 invalidate_tlbcam_entry(num_tlbcam_entries
- 1);
134 #endif /* CONFIG_MPC8560 */
136 /* setup the board related info for the MDIO bus */
137 mdata
= (struct gianfar_mdio_data
*) ppc_sys_get_pdata(MPC85xx_MDIO
);
139 mdata
->irq
[0] = MPC85xx_IRQ_EXT8
;
140 mdata
->irq
[1] = MPC85xx_IRQ_EXT8
;
142 mdata
->irq
[3] = MPC85xx_IRQ_EXT8
;
145 /* setup the board related information for the enet controllers */
146 pdata
= (struct gianfar_platform_data
*) ppc_sys_get_pdata(MPC85xx_TSEC1
);
148 pdata
->board_flags
= FSL_GIANFAR_BRD_HAS_PHY_INTR
;
151 memcpy(pdata
->mac_addr
, binfo
->bi_enetaddr
, 6);
154 pdata
= (struct gianfar_platform_data
*) ppc_sys_get_pdata(MPC85xx_TSEC2
);
156 pdata
->board_flags
= FSL_GIANFAR_BRD_HAS_PHY_INTR
;
159 memcpy(pdata
->mac_addr
, binfo
->bi_enet1addr
, 6);
162 #ifdef CONFIG_MPC8540
163 pdata
= (struct gianfar_platform_data
*) ppc_sys_get_pdata(MPC85xx_FEC
);
165 pdata
->board_flags
= 0;
168 memcpy(pdata
->mac_addr
, binfo
->bi_enet2addr
, 6);
172 #ifdef CONFIG_BLK_DEV_INITRD
174 ROOT_DEV
= Root_RAM0
;
177 #ifdef CONFIG_ROOT_NFS
180 ROOT_DEV
= Root_HDA1
;
184 #ifdef CONFIG_MPC8560
185 static irqreturn_t
cpm2_cascade(int irq
, void *dev_id
, struct pt_regs
*regs
)
187 while ((irq
= cpm2_get_irq(regs
)) >= 0)
192 static struct irqaction cpm2_irqaction
= {
193 .handler
= cpm2_cascade
,
194 .flags
= SA_INTERRUPT
,
195 .mask
= CPU_MASK_NONE
,
196 .name
= "cpm2_cascade",
198 #endif /* CONFIG_MPC8560 */
201 tqm85xx_init_IRQ(void)
203 bd_t
*binfo
= (bd_t
*) __res
;
205 /* Determine the Physical Address of the OpenPIC regs */
206 phys_addr_t OpenPIC_PAddr
=
207 binfo
->bi_immr_base
+ MPC85xx_OPENPIC_OFFSET
;
208 OpenPIC_Addr
= ioremap(OpenPIC_PAddr
, MPC85xx_OPENPIC_SIZE
);
209 OpenPIC_InitSenses
= tqm85xx_openpic_initsenses
;
210 OpenPIC_NumInitSenses
= sizeof (tqm85xx_openpic_initsenses
);
212 /* Skip reserved space and internal sources */
213 openpic_set_sources(0, 32, OpenPIC_Addr
+ 0x10200);
215 /* Map PIC IRQs 0-11 */
216 openpic_set_sources(48, 12, OpenPIC_Addr
+ 0x10000);
218 /* we let openpic interrupts starting from an offset, to
219 * leave space for cascading interrupts underneath.
221 openpic_init(MPC85xx_OPENPIC_IRQ_OFFSET
);
223 #ifdef CONFIG_MPC8560
227 setup_irq(MPC85xx_IRQ_CPM
, &cpm2_irqaction
);
228 #endif /* CONFIG_MPC8560 */
233 int tqm85xx_show_cpuinfo(struct seq_file
*m
)
235 uint pvid
, svid
, phid1
;
236 uint memsize
= total_memory
;
237 bd_t
*binfo
= (bd_t
*) __res
;
240 /* get the core frequency */
241 freq
= binfo
->bi_intfreq
;
243 pvid
= mfspr(SPRN_PVR
);
244 svid
= mfspr(SPRN_SVR
);
246 seq_printf(m
, "Vendor\t\t: TQ Components\n");
247 seq_printf(m
, "Machine\t\t: TQM%s\n", cur_ppc_sys_spec
->ppc_sys_name
);
248 seq_printf(m
, "clock\t\t: %dMHz\n", freq
/ 1000000);
249 seq_printf(m
, "PVR\t\t: 0x%x\n", pvid
);
250 seq_printf(m
, "SVR\t\t: 0x%x\n", svid
);
252 /* Display cpu Pll setting */
253 phid1
= mfspr(SPRN_HID1
);
254 seq_printf(m
, "PLL setting\t: 0x%x\n", ((phid1
>> 24) & 0x3f));
256 /* Display the amount of memory */
257 seq_printf(m
, "Memory\t\t: %d MB\n", memsize
/ (1024 * 1024));
262 #if defined(CONFIG_I2C) && defined(CONFIG_SENSORS_DS1337)
263 extern ulong
ds1337_get_rtc_time(void);
264 extern int ds1337_set_rtc_time(unsigned long nowtime
);
267 tqm85xx_rtc_hookup(void)
271 ppc_md
.set_rtc_time
= ds1337_set_rtc_time
;
272 ppc_md
.get_rtc_time
= ds1337_get_rtc_time
;
275 tv
.tv_sec
= (ppc_md
.get_rtc_time
)();
276 do_settimeofday(&tv
);
280 late_initcall(tqm85xx_rtc_hookup
);
287 int mpc85xx_map_irq(struct pci_dev
*dev
, unsigned char idsel
, unsigned char pin
)
289 static char pci_irq_table
[][4] =
291 * PCI IDSEL/INTPIN->INTLINE
295 {PIRQA
, PIRQB
, 0, 0},
298 const long min_idsel
= 0x1c, max_idsel
= 0x1c, irqs_per_slot
= 4;
299 return PCI_IRQ_TABLE_LOOKUP
;
302 int mpc85xx_exclude_device(u_char bus
, u_char devfn
)
304 if (bus
== 0 && PCI_SLOT(devfn
) == 0)
305 return PCIBIOS_DEVICE_NOT_FOUND
;
307 return PCIBIOS_SUCCESSFUL
;
310 #endif /* CONFIG_PCI */
312 #ifdef CONFIG_RAPIDIO
313 void platform_rio_init(void)
315 /* 512MB RIO LAW at 0xc0000000 */
316 mpc85xx_rio_setup(0xc0000000, 0x20000000);
318 #endif /* CONFIG_RAPIDIO */
320 /* ************************************************************************ */
322 platform_init(unsigned long r3
, unsigned long r4
, unsigned long r5
,
323 unsigned long r6
, unsigned long r7
)
325 /* parse_bootinfo must always be called first */
326 parse_bootinfo(find_bootinfo());
329 * If we were passed in a board information, copy it into the
330 * residual data area.
333 memcpy((void *) __res
, (void *) (r3
+ KERNELBASE
),
337 #if defined(CONFIG_SERIAL_TEXT_DEBUG) && !defined(CONFIG_MPC8560)
339 bd_t
*binfo
= (bd_t
*) __res
;
342 /* Use the last TLB entry to map CCSRBAR to allow access to DUART regs */
343 settlbcam(num_tlbcam_entries
- 1, binfo
->bi_immr_base
,
344 binfo
->bi_immr_base
, MPC85xx_CCSRBAR_SIZE
, _PAGE_IO
, 0);
346 memset(&p
, 0, sizeof (p
));
348 p
.membase
= (void *) binfo
->bi_immr_base
+ MPC85xx_UART0_OFFSET
;
349 p
.uartclk
= binfo
->bi_busfreq
;
353 memset(&p
, 0, sizeof (p
));
355 p
.membase
= (void *) binfo
->bi_immr_base
+ MPC85xx_UART1_OFFSET
;
356 p
.uartclk
= binfo
->bi_busfreq
;
362 #if defined(CONFIG_BLK_DEV_INITRD)
364 * If the init RAM disk has been configured in, and there's a valid
365 * starting address for it, set it up.
368 initrd_start
= r4
+ KERNELBASE
;
369 initrd_end
= r5
+ KERNELBASE
;
371 #endif /* CONFIG_BLK_DEV_INITRD */
373 /* Copy the kernel command line arguments to a safe place. */
376 *(char *) (r7
+ KERNELBASE
) = 0;
377 strcpy(cmd_line
, (char *) (r6
+ KERNELBASE
));
380 identify_ppc_sys_by_id(mfspr(SPRN_SVR
));
382 /* setup the PowerPC module struct */
383 ppc_md
.setup_arch
= tqm85xx_setup_arch
;
384 ppc_md
.show_cpuinfo
= tqm85xx_show_cpuinfo
;
386 ppc_md
.init_IRQ
= tqm85xx_init_IRQ
;
387 ppc_md
.get_irq
= openpic_get_irq
;
389 ppc_md
.restart
= mpc85xx_restart
;
390 ppc_md
.power_off
= mpc85xx_power_off
;
391 ppc_md
.halt
= mpc85xx_halt
;
393 ppc_md
.find_end_of_memory
= mpc85xx_find_end_of_memory
;
395 ppc_md
.time_init
= NULL
;
396 ppc_md
.set_rtc_time
= NULL
;
397 ppc_md
.get_rtc_time
= NULL
;
398 ppc_md
.calibrate_decr
= mpc85xx_calibrate_decr
;
400 #ifndef CONFIG_MPC8560
401 #if defined(CONFIG_SERIAL_8250) && defined(CONFIG_SERIAL_TEXT_DEBUG)
402 ppc_md
.progress
= gen550_progress
;
403 #endif /* CONFIG_SERIAL_8250 && CONFIG_SERIAL_TEXT_DEBUG */
404 #if defined(CONFIG_SERIAL_8250) && defined(CONFIG_KGDB)
405 ppc_md
.early_serial_map
= mpc85xx_early_serial_map
;
406 #endif /* CONFIG_SERIAL_8250 && CONFIG_KGDB */
407 #endif /* CONFIG_MPC8560 */
410 ppc_md
.progress("tqm85xx_init(): exit", 0);