arch/ppc/platforms/chestnut.c

   1 /*
   2  * Board setup routines for IBM Chestnut
   3  *
   4  * Author: <source@mvista.com>
   5  *
   6  * <2004> (c) MontaVista Software, Inc. This file is licensed under
   7  * the terms of the GNU General Public License version 2. This program
   8  * is licensed "as is" without any warranty of any kind, whether express
   9  * or implied.
  10  */
  11
  12 #include <linux/stddef.h>
  13 #include <linux/kernel.h>
  14 #include <linux/init.h>
  15 #include <linux/errno.h>
  16 #include <linux/reboot.h>
  17 #include <linux/kdev_t.h>
  18 #include <linux/major.h>
  19 #include <linux/blkdev.h>
  20 #include <linux/console.h>
  21 #include <linux/root_dev.h>
  22 #include <linux/initrd.h>
  23 #include <linux/delay.h>
  24 #include <linux/seq_file.h>
  25 #include <linux/ide.h>
  26 #include <linux/serial.h>
  27 #include <linux/serial_core.h>
  28 #include <linux/serial_8250.h>
  29 #include <linux/mtd/physmap.h>
  30 #include <asm/system.h>
  31 #include <asm/pgtable.h>
  32 #include <asm/page.h>
  33 #include <asm/time.h>
  34 #include <asm/dma.h>
  35 #include <asm/io.h>
  36 #include <asm/hw_irq.h>
  37 #include <asm/machdep.h>
  38 #include <asm/kgdb.h>
  39 #include <asm/bootinfo.h>
  40 #include <asm/mv64x60.h>
  41 #include <platforms/chestnut.h>
  42
  43 static void __iomem *sram_base; /* Virtual addr of Internal SRAM */
  44 static void __iomem *cpld_base; /* Virtual addr of CPLD Regs */
  45
  46 static mv64x60_handle_t bh;
  47
  48 extern void gen550_progress(char *, unsigned short);
  49 extern void gen550_init(int, struct uart_port *);
  50 extern void mv64360_pcibios_fixup(mv64x60_handle_t *bh);
  51
  52 #define BIT(x) (1<<x)
  53 #define CHESTNUT_PRESERVE_MASK (BIT(MV64x60_CPU2DEV_0_WIN) | \
  54                                 BIT(MV64x60_CPU2DEV_1_WIN) | \
  55                                 BIT(MV64x60_CPU2DEV_2_WIN) | \
  56                                 BIT(MV64x60_CPU2DEV_3_WIN) | \
  57                                 BIT(MV64x60_CPU2BOOT_WIN))
  58 /**************************************************************************
  59  * FUNCTION: chestnut_calibrate_decr
  60  *
  61  * DESCRIPTION: initialize decrementer interrupt frequency (used as system
  62  *              timer)
  63  *
  64  ****/
  65 static void __init
  66 chestnut_calibrate_decr(void)
  67 {
  68         ulong freq;
  69
  70         freq = CHESTNUT_BUS_SPEED / 4;
  71
  72         printk("time_init: decrementer frequency = %lu.%.6lu MHz\n",
  73                 freq/1000000, freq%1000000);
  74
  75         tb_ticks_per_jiffy = freq / HZ;
  76         tb_to_us = mulhwu_scale_factor(freq, 1000000);
  77 }
  78
  79 static int
  80 chestnut_show_cpuinfo(struct seq_file *m)
  81 {
  82         seq_printf(m, "vendor\t\t: IBM\n");
  83         seq_printf(m, "machine\t\t: 750FX/GX Eval Board (Chestnut/Buckeye)\n");
  84
  85         return 0;
  86 }
  87
  88 /**************************************************************************
  89  * FUNCTION: chestnut_find_end_of_memory
  90  *
  91  * DESCRIPTION: ppc_md memory size callback
  92  *
  93  ****/
  94 unsigned long __init
  95 chestnut_find_end_of_memory(void)
  96 {
  97         static int  mem_size = 0;
  98
  99         if (mem_size == 0) {
 100                 mem_size = mv64x60_get_mem_size(CONFIG_MV64X60_NEW_BASE,
 101                                 MV64x60_TYPE_MV64460);
 102         }
 103         return mem_size;
 104 }
 105
 106 #if defined(CONFIG_SERIAL_8250)
 107 static void __init
 108 chestnut_early_serial_map(void)
 109 {
 110         struct uart_port port;
 111
 112         /* Setup serial port access */
 113         memset(&port, 0, sizeof(port));
 114         port.uartclk = BASE_BAUD * 16;
 115         port.irq = UART0_INT;
 116         port.flags = STD_COM_FLAGS | UPF_IOREMAP;
 117         port.iotype = UPIO_MEM;
 118         port.mapbase = CHESTNUT_UART0_IO_BASE;
 119         port.regshift = 0;
 120
 121         if (early_serial_setup(&port) != 0)
 122                 printk("Early serial init of port 0 failed\n");
 123
 124         /* Assume early_serial_setup() doesn't modify serial_req */
 125         port.line = 1;
 126         port.irq = UART1_INT;
 127         port.mapbase = CHESTNUT_UART1_IO_BASE;
 128
 129         if (early_serial_setup(&port) != 0)
 130                 printk("Early serial init of port 1 failed\n");
 131 }
 132 #endif
 133
 134 /**************************************************************************
 135  * FUNCTION: chestnut_map_irq
 136  *
 137  * DESCRIPTION: 0 return since PCI IRQs not needed
 138  *
 139  ****/
 140 static int __init
 141 chestnut_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
 142 {
 143         static char pci_irq_table[][4] = {
 144                 {CHESTNUT_PCI_SLOT0_IRQ, CHESTNUT_PCI_SLOT0_IRQ,
 145                  CHESTNUT_PCI_SLOT0_IRQ, CHESTNUT_PCI_SLOT0_IRQ},
 146                 {CHESTNUT_PCI_SLOT1_IRQ, CHESTNUT_PCI_SLOT1_IRQ,
 147                  CHESTNUT_PCI_SLOT1_IRQ, CHESTNUT_PCI_SLOT1_IRQ},
 148                 {CHESTNUT_PCI_SLOT2_IRQ, CHESTNUT_PCI_SLOT2_IRQ,
 149                  CHESTNUT_PCI_SLOT2_IRQ, CHESTNUT_PCI_SLOT2_IRQ},
 150                 {CHESTNUT_PCI_SLOT3_IRQ, CHESTNUT_PCI_SLOT3_IRQ,
 151                  CHESTNUT_PCI_SLOT3_IRQ, CHESTNUT_PCI_SLOT3_IRQ},
 152         };
 153         const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
 154
 155         return PCI_IRQ_TABLE_LOOKUP;
 156 }
 157
 158
 159 /**************************************************************************
 160  * FUNCTION: chestnut_setup_bridge
 161  *
 162  * DESCRIPTION: initalize board-specific settings on the MV64360
 163  *
 164  ****/
 165 static void __init
 166 chestnut_setup_bridge(void)
 167 {
 168         struct mv64x60_setup_info       si;
 169         int i;
 170
 171         if ( ppc_md.progress )
 172                 ppc_md.progress("chestnut_setup_bridge: enter", 0);
 173
 174         memset(&si, 0, sizeof(si));
 175
 176         si.phys_reg_base = CONFIG_MV64X60_NEW_BASE;
 177
 178         /* setup only PCI bus 0 (bus 1 not used) */
 179         si.pci_0.enable_bus = 1;
 180         si.pci_0.pci_io.cpu_base = CHESTNUT_PCI0_IO_PROC_ADDR;
 181         si.pci_0.pci_io.pci_base_hi = 0;
 182         si.pci_0.pci_io.pci_base_lo = CHESTNUT_PCI0_IO_PCI_ADDR;
 183         si.pci_0.pci_io.size = CHESTNUT_PCI0_IO_SIZE;
 184         si.pci_0.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE; /* no swapping */
 185         si.pci_0.pci_mem[0].cpu_base = CHESTNUT_PCI0_MEM_PROC_ADDR;
 186         si.pci_0.pci_mem[0].pci_base_hi = CHESTNUT_PCI0_MEM_PCI_HI_ADDR;
 187         si.pci_0.pci_mem[0].pci_base_lo = CHESTNUT_PCI0_MEM_PCI_LO_ADDR;
 188         si.pci_0.pci_mem[0].size = CHESTNUT_PCI0_MEM_SIZE;
 189         si.pci_0.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE; /* no swapping */
 190         si.pci_0.pci_cmd_bits = 0;
 191         si.pci_0.latency_timer = 0x80;
 192
 193         for (i=0; i<MV64x60_CPU2MEM_WINDOWS; i++) {
 194 #if defined(CONFIG_NOT_COHERENT_CACHE)
 195                 si.cpu_prot_options[i] = 0;
 196                 si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE;
 197                 si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE;
 198                 si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE;
 199
 200                 si.pci_1.acc_cntl_options[i] =
 201                     MV64360_PCI_ACC_CNTL_SNOOP_NONE |
 202                     MV64360_PCI_ACC_CNTL_SWAP_NONE |
 203                     MV64360_PCI_ACC_CNTL_MBURST_128_BYTES |
 204                     MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;
 205 #else
 206                 si.cpu_prot_options[i] = 0;
 207                 si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE; /* errata */
 208                 si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE; /* errata */
 209                 si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE; /* errata */
 210
 211                 si.pci_1.acc_cntl_options[i] =
 212                     MV64360_PCI_ACC_CNTL_SNOOP_WB |
 213                     MV64360_PCI_ACC_CNTL_SWAP_NONE |
 214                     MV64360_PCI_ACC_CNTL_MBURST_32_BYTES |
 215                     MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES;
 216 #endif
 217         }
 218
 219         /* Lookup host bridge - on CPU 0 - no SMP support */
 220         if (mv64x60_init(&bh, &si)) {
 221                 printk("\n\nPCI Bridge initialization failed!\n");
 222         }
 223
 224         pci_dram_offset = 0;
 225         ppc_md.pci_swizzle = common_swizzle;
 226         ppc_md.pci_map_irq = chestnut_map_irq;
 227         ppc_md.pci_exclude_device = mv64x60_pci_exclude_device;
 228
 229         mv64x60_set_bus(&bh, 0, 0);
 230         bh.hose_a->first_busno = 0;
 231         bh.hose_a->last_busno = 0xff;
 232         bh.hose_a->last_busno = pciauto_bus_scan(bh.hose_a, 0);
 233 }
 234
 235 void __init
 236 chestnut_setup_peripherals(void)
 237 {
 238         mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN,
 239                         CHESTNUT_BOOT_8BIT_BASE, CHESTNUT_BOOT_8BIT_SIZE, 0);
 240         bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);
 241
 242         mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN,
 243                         CHESTNUT_32BIT_BASE, CHESTNUT_32BIT_SIZE, 0);
 244         bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_0_WIN);
 245
 246         mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN,
 247                         CHESTNUT_CPLD_BASE, CHESTNUT_CPLD_SIZE, 0);
 248         bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN);
 249         cpld_base = ioremap(CHESTNUT_CPLD_BASE, CHESTNUT_CPLD_SIZE);
 250
 251         mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_2_WIN,
 252                         CHESTNUT_UART_BASE, CHESTNUT_UART_SIZE, 0);
 253         bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_2_WIN);
 254
 255         mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_3_WIN,
 256                         CHESTNUT_FRAM_BASE, CHESTNUT_FRAM_SIZE, 0);
 257         bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_3_WIN);
 258
 259         mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN,
 260                         CHESTNUT_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, 0);
 261         bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN);
 262
 263 #ifdef CONFIG_NOT_COHERENT_CACHE
 264         mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b0);
 265 #else
 266         mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b2);
 267 #endif
 268         sram_base = ioremap(CHESTNUT_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE);
 269         memset(sram_base, 0, MV64360_SRAM_SIZE);
 270
 271         /*
 272          * Configure MPP pins for PCI DMA
 273          *
 274          * PCI Slot     GNT pin         REQ pin
 275          *      0       MPP16           MPP17
 276          *      1       MPP18           MPP19
 277          *      2       MPP20           MPP21
 278          *      3       MPP22           MPP23
 279          */
 280         mv64x60_write(&bh, MV64x60_MPP_CNTL_2,
 281                         (0x1 << 0)  |   /* MPPSel16 PCI0_GNT[0] */
 282                         (0x1 << 4)  |   /* MPPSel17 PCI0_REQ[0] */
 283                         (0x1 << 8)  |   /* MPPSel18 PCI0_GNT[1] */
 284                         (0x1 << 12) |   /* MPPSel19 PCI0_REQ[1] */
 285                         (0x1 << 16) |   /* MPPSel20 PCI0_GNT[2] */
 286                         (0x1 << 20) |   /* MPPSel21 PCI0_REQ[2] */
 287                         (0x1 << 24) |   /* MPPSel22 PCI0_GNT[3] */
 288                         (0x1 << 28));   /* MPPSel23 PCI0_REQ[3] */
 289         /*
 290          * Set unused MPP pins for output, as per schematic note
 291          *
 292          * Unused Pins: MPP01, MPP02, MPP04, MPP05, MPP06
 293          *              MPP09, MPP10, MPP13, MPP14, MPP15
 294          */
 295         mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_0,
 296                         (0xf << 4)  |   /* MPPSel01 GPIO[1] */
 297                         (0xf << 8)  |   /* MPPSel02 GPIO[2] */
 298                         (0xf << 16) |   /* MPPSel04 GPIO[4] */
 299                         (0xf << 20) |   /* MPPSel05 GPIO[5] */
 300                         (0xf << 24));   /* MPPSel06 GPIO[6] */
 301         mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_1,
 302                         (0xf << 4)  |   /* MPPSel09 GPIO[9] */
 303                         (0xf << 8)  |   /* MPPSel10 GPIO[10] */
 304                         (0xf << 20) |   /* MPPSel13 GPIO[13] */
 305                         (0xf << 24) |   /* MPPSel14 GPIO[14] */
 306                         (0xf << 28));   /* MPPSel15 GPIO[15] */
 307         mv64x60_set_bits(&bh, MV64x60_GPP_IO_CNTL, /* Output */
 308                         BIT(1)  | BIT(2)  | BIT(4)  | BIT(5)  | BIT(6)  |
 309                         BIT(9)  | BIT(10) | BIT(13) | BIT(14) | BIT(15));
 310
 311         /*
 312          * Configure the following MPP pins to indicate a level
 313          * triggered interrupt
 314          *
 315          * MPP24 - Board Reset (just map the MPP & GPP for chestnut_reset)
 316          * MPP25 - UART A  (high)
 317          * MPP26 - UART B  (high)
 318          * MPP28 - PCI Slot 3 (low)
 319          * MPP29 - PCI Slot 2 (low)
 320          * MPP30 - PCI Slot 1 (low)
 321          * MPP31 - PCI Slot 0 (low)
 322          */
 323         mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_3,
 324                         BIT(3) | BIT(2) | BIT(1) | BIT(0)        | /* MPP 24 */
 325                         BIT(7) | BIT(6) | BIT(5) | BIT(4)        | /* MPP 25 */
 326                         BIT(11) | BIT(10) | BIT(9) | BIT(8)      | /* MPP 26 */
 327                         BIT(19) | BIT(18) | BIT(17) | BIT(16)    | /* MPP 28 */
 328                         BIT(23) | BIT(22) | BIT(21) | BIT(20)    | /* MPP 29 */
 329                         BIT(27) | BIT(26) | BIT(25) | BIT(24)    | /* MPP 30 */
 330                         BIT(31) | BIT(30) | BIT(29) | BIT(28));    /* MPP 31 */
 331
 332         /*
 333          * Define GPP 25 (high), 26 (high), 28 (low), 29 (low), 30 (low),
 334          * 31 (low) interrupt polarity input signal and level triggered
 335          */
 336         mv64x60_clr_bits(&bh, MV64x60_GPP_LEVEL_CNTL, BIT(25) | BIT(26));
 337         mv64x60_set_bits(&bh, MV64x60_GPP_LEVEL_CNTL,
 338                         BIT(28) | BIT(29) | BIT(30) | BIT(31));
 339         mv64x60_clr_bits(&bh, MV64x60_GPP_IO_CNTL,
 340                         BIT(25) | BIT(26) | BIT(28) | BIT(29) | BIT(30) |
 341                         BIT(31));
 342
 343         /* Config GPP interrupt controller to respond to level trigger */
 344         mv64x60_set_bits(&bh, MV64360_COMM_ARBITER_CNTL, BIT(10));
 345
 346         /*
 347          * Dismiss and then enable interrupt on GPP interrupt cause for CPU #0
 348          */
 349         mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE,
 350                         ~(BIT(25) | BIT(26) | BIT(28) | BIT(29) | BIT(30) |
 351                           BIT(31)));
 352         mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK,
 353                         BIT(25) | BIT(26) | BIT(28) | BIT(29) | BIT(30) |
 354                         BIT(31));
 355
 356         /*
 357          * Dismiss and then enable interrupt on CPU #0 high cause register
 358          * BIT27 summarizes GPP interrupts 24-31
 359          */
 360         mv64x60_set_bits(&bh, MV64360_IC_CPU0_INTR_MASK_HI, BIT(27));
 361
 362         if (ppc_md.progress)
 363                 ppc_md.progress("chestnut_setup_bridge: exit", 0);
 364 }
 365
 366 /**************************************************************************
 367  * FUNCTION: chestnut_setup_arch
 368  *
 369  * DESCRIPTION: ppc_md machine configuration callback
 370  *
 371  ****/
 372 static void __init
 373 chestnut_setup_arch(void)
 374 {
 375         if (ppc_md.progress)
 376                 ppc_md.progress("chestnut_setup_arch: enter", 0);
 377
 378         /* init to some ~sane value until calibrate_delay() runs */
 379         loops_per_jiffy = 50000000 / HZ;
 380
 381         /* if the time base value is greater than bus freq/4 (the TB and
 382         * decrementer tick rate) + signed integer rollover value, we
 383         * can spend a fair amount of time waiting for the rollover to
 384         * happen.  To get around this, initialize the time base register
 385         * to a "safe" value.
 386         */
 387         set_tb(0, 0);
 388
 389 #ifdef CONFIG_BLK_DEV_INITRD
 390         if (initrd_start)
 391                 ROOT_DEV = Root_RAM0;
 392         else
 393 #endif
 394 #ifdef CONFIG_ROOT_NFS
 395                 ROOT_DEV = Root_NFS;
 396 #else
 397                 ROOT_DEV = Root_SDA2;
 398 #endif
 399
 400         /*
 401         * Set up the L2CR register.
 402         */
 403         _set_L2CR(_get_L2CR() | L2CR_L2E);
 404
 405         chestnut_setup_bridge();
 406         chestnut_setup_peripherals();
 407
 408 #ifdef CONFIG_DUMMY_CONSOLE
 409         conswitchp = &dummy_con;
 410 #endif
 411
 412 #if defined(CONFIG_SERIAL_8250)
 413         chestnut_early_serial_map();
 414 #endif
 415
 416         /* Identify the system */
 417         printk(KERN_INFO "System Identification: IBM 750FX/GX Eval Board\n");
 418         printk(KERN_INFO "IBM 750FX/GX port (C) 2004 MontaVista Software, Inc."
 419                 " (source@mvista.com)\n");
 420
 421         if (ppc_md.progress)
 422                 ppc_md.progress("chestnut_setup_arch: exit", 0);
 423 }
 424
 425 #ifdef CONFIG_MTD_PHYSMAP
 426 static struct mtd_partition ptbl;
 427
 428 static int __init
 429 chestnut_setup_mtd(void)
 430 {
 431         memset(&ptbl, 0, sizeof(ptbl));
 432
 433         ptbl.name = "User FS";
 434         ptbl.size = CHESTNUT_32BIT_SIZE;
 435
 436         physmap_map.size = CHESTNUT_32BIT_SIZE;
 437         physmap_set_partitions(&ptbl, 1);
 438         return 0;
 439 }
 440
 441 arch_initcall(chestnut_setup_mtd);
 442 #endif
 443
 444 /**************************************************************************
 445  * FUNCTION: chestnut_restart
 446  *
 447  * DESCRIPTION: ppc_md machine reset callback
 448  *              reset the board via the CPLD command register
 449  *
 450  ****/
 451 static void
 452 chestnut_restart(char *cmd)
 453 {
 454         volatile ulong i = 10000000;
 455
 456         local_irq_disable();
 457
 458         /*
 459          * Set CPLD Reg 3 bit 0 to 1 to allow MPP signals on reset to work
 460          *
 461          * MPP24 - board reset
 462          */
 463         writeb(0x1, cpld_base + 3);
 464
 465         /* GPP pin tied to MPP earlier */
 466         mv64x60_set_bits(&bh, MV64x60_GPP_VALUE_SET, BIT(24));
 467
 468         while (i-- > 0);
 469         panic("restart failed\n");
 470 }
 471
 472 static void
 473 chestnut_halt(void)
 474 {
 475         local_irq_disable();
 476         for (;;);
 477         /* NOTREACHED */
 478 }
 479
 480 static void
 481 chestnut_power_off(void)
 482 {
 483         chestnut_halt();
 484         /* NOTREACHED */
 485 }
 486
 487 /**************************************************************************
 488  * FUNCTION: chestnut_map_io
 489  *
 490  * DESCRIPTION: configure fixed memory-mapped IO
 491  *
 492  ****/
 493 static void __init
 494 chestnut_map_io(void)
 495 {
 496 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
 497         io_block_mapping(CHESTNUT_UART_BASE, CHESTNUT_UART_BASE, 0x100000,
 498                 _PAGE_IO);
 499 #endif
 500 }
 501
 502 /**************************************************************************
 503  * FUNCTION: chestnut_set_bat
 504  *
 505  * DESCRIPTION: configures a (temporary) bat mapping for early access to
 506  *              device I/O
 507  *
 508  ****/
 509 static __inline__ void
 510 chestnut_set_bat(void)
 511 {
 512         mb();
 513         mtspr(SPRN_DBAT3U, 0xf0001ffe);
 514         mtspr(SPRN_DBAT3L, 0xf000002a);
 515         mb();
 516 }
 517
 518 /**************************************************************************
 519  * FUNCTION: platform_init
 520  *
 521  * DESCRIPTION: main entry point for configuring board-specific machine
 522  *              callbacks
 523  *
 524  ****/
 525 void __init
 526 platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
 527               unsigned long r6, unsigned long r7)
 528 {
 529         parse_bootinfo(find_bootinfo());
 530
 531         /* Copy the kernel command line arguments to a safe place. */
 532
 533         if (r6) {
 534                 *(char *) (r7 + KERNELBASE) = 0;
 535                 strcpy(cmd_line, (char *) (r6 + KERNELBASE));
 536         }
 537
 538         isa_mem_base = 0;
 539
 540         ppc_md.setup_arch = chestnut_setup_arch;
 541         ppc_md.show_cpuinfo = chestnut_show_cpuinfo;
 542         ppc_md.init_IRQ = mv64360_init_irq;
 543         ppc_md.get_irq = mv64360_get_irq;
 544         ppc_md.init = NULL;
 545
 546         ppc_md.find_end_of_memory = chestnut_find_end_of_memory;
 547         ppc_md.setup_io_mappings  = chestnut_map_io;
 548
 549         ppc_md.restart = chestnut_restart;
 550         ppc_md.power_off = chestnut_power_off;
 551         ppc_md.halt = chestnut_halt;
 552
 553         ppc_md.time_init = NULL;
 554         ppc_md.set_rtc_time = NULL;
 555         ppc_md.get_rtc_time = NULL;
 556         ppc_md.calibrate_decr = chestnut_calibrate_decr;
 557
 558         ppc_md.nvram_read_val = NULL;
 559         ppc_md.nvram_write_val = NULL;
 560
 561         ppc_md.heartbeat = NULL;
 562
 563         bh.p_base = CONFIG_MV64X60_NEW_BASE;
 564
 565         chestnut_set_bat();
 566
 567 #if defined(CONFIG_SERIAL_TEXT_DEBUG)
 568         ppc_md.progress = gen550_progress;
 569 #endif
 570 #if defined(CONFIG_KGDB)
 571         ppc_md.kgdb_map_scc = gen550_kgdb_map_scc;
 572 #endif
 573
 574         if (ppc_md.progress)
 575                 ppc_md.progress("chestnut_init(): exit", 0);
 576 }