2 * arch/ppc/platforms/ev64260.c
4 * Board setup routines for the Marvell/Galileo EV-64260-BP Evaluation Board.
6 * Author: Mark A. Greer <mgreer@mvista.com>
8 * 2001-2003 (c) MontaVista, Software, Inc. This file is licensed under
9 * the terms of the GNU General Public License version 2. This program
10 * is licensed "as is" without any warranty of any kind, whether express
15 * The EV-64260-BP port is the result of hard work from many people from
16 * many companies. In particular, employees of Marvell/Galileo, Mission
17 * Critical Linux, Xyterra, and MontaVista Software were heavily involved.
19 * Note: I have not been able to get *all* PCI slots to work reliably
20 * at 66 MHz. I recommend setting jumpers J15 & J16 to short pins 1&2
21 * so that 33 MHz is used. --MAG
22 * Note: The 750CXe and 7450 are not stable with a 125MHz or 133MHz TCLK/SYSCLK.
23 * At 100MHz, they are solid.
25 #include <linux/config.h>
27 #include <linux/delay.h>
28 #include <linux/pci.h>
29 #include <linux/ide.h>
30 #include <linux/irq.h>
32 #include <linux/seq_file.h>
33 #include <linux/console.h>
34 #include <linux/initrd.h>
35 #include <linux/root_dev.h>
36 #include <linux/platform_device.h>
37 #if !defined(CONFIG_SERIAL_MPSC_CONSOLE)
38 #include <linux/serial.h>
39 #include <linux/tty.h>
40 #include <linux/serial_core.h>
42 #include <linux/mv643xx.h>
44 #include <asm/bootinfo.h>
45 #include <asm/machdep.h>
46 #include <asm/mv64x60.h>
50 #include <platforms/ev64260.h>
52 #define BOARD_VENDOR "Marvell/Galileo"
53 #define BOARD_MACHINE "EV-64260-BP"
55 static struct mv64x60_handle bh
;
57 #if !defined(CONFIG_SERIAL_MPSC_CONSOLE)
58 extern void gen550_progress(char *, unsigned short);
59 extern void gen550_init(int, struct uart_port
*);
62 static const unsigned int cpu_7xx
[16] = { /* 7xx & 74xx (but not 745x) */
63 18, 15, 14, 2, 4, 13, 5, 9, 6, 11, 8, 10, 16, 12, 7, 0
65 static const unsigned int cpu_745x
[2][16] = { /* PLL_EXT 0 & 1 */
66 { 1, 15, 14, 2, 4, 13, 5, 9, 6, 11, 8, 10, 16, 12, 7, 0 },
67 { 0, 30, 0, 2, 0, 26, 0, 18, 0, 22, 20, 24, 28, 32, 0, 0 }
74 ev64260_get_bus_speed(void)
80 ev64260_get_cpu_speed(void)
82 unsigned long pvr
, hid1
, pll_ext
;
84 pvr
= PVR_VER(mfspr(SPRN_PVR
));
86 if (pvr
!= PVR_VER(PVR_7450
)) {
87 hid1
= mfspr(SPRN_HID1
) >> 28;
88 return ev64260_get_bus_speed() * cpu_7xx
[hid1
]/2;
91 hid1
= (mfspr(SPRN_HID1
) & 0x0001e000) >> 13;
92 pll_ext
= 0; /* No way to read; must get from schematic */
93 return ev64260_get_bus_speed() * cpu_745x
[pll_ext
][hid1
]/2;
98 ev64260_find_end_of_memory(void)
100 return mv64x60_get_mem_size(CONFIG_MV64X60_NEW_BASE
,
101 MV64x60_TYPE_GT64260A
);
105 * Marvell/Galileo EV-64260-BP Evaluation Board PCI interrupt routing.
106 * Note: By playing with J8 and JP1-4, you can get 2 IRQ's from the first
107 * PCI bus (in which cast, INTPIN B would be EV64260_PCI_1_IRQ).
108 * This is the most IRQs you can get from one bus with this board, though.
111 ev64260_map_irq(struct pci_dev
*dev
, unsigned char idsel
, unsigned char pin
)
113 struct pci_controller
*hose
= pci_bus_to_hose(dev
->bus
->number
);
115 if (hose
->index
== 0) {
116 static char pci_irq_table
[][4] =
118 * PCI IDSEL/INTPIN->INTLINE
122 {EV64260_PCI_0_IRQ
,0,0,0}, /* IDSEL 7 - PCI bus 0 */
123 {EV64260_PCI_0_IRQ
,0,0,0}, /* IDSEL 8 - PCI bus 0 */
126 const long min_idsel
= 7, max_idsel
= 8, irqs_per_slot
= 4;
127 return PCI_IRQ_TABLE_LOOKUP
;
130 static char pci_irq_table
[][4] =
132 * PCI IDSEL/INTPIN->INTLINE
136 { EV64260_PCI_1_IRQ
,0,0,0}, /* IDSEL 7 - PCI bus 1 */
137 { EV64260_PCI_1_IRQ
,0,0,0}, /* IDSEL 8 - PCI bus 1 */
140 const long min_idsel
= 7, max_idsel
= 8, irqs_per_slot
= 4;
141 return PCI_IRQ_TABLE_LOOKUP
;
146 ev64260_setup_peripherals(void)
148 mv64x60_set_32bit_window(&bh
, MV64x60_CPU2BOOT_WIN
,
149 EV64260_EMB_FLASH_BASE
, EV64260_EMB_FLASH_SIZE
, 0);
150 bh
.ci
->enable_window_32bit(&bh
, MV64x60_CPU2BOOT_WIN
);
151 mv64x60_set_32bit_window(&bh
, MV64x60_CPU2DEV_0_WIN
,
152 EV64260_EXT_SRAM_BASE
, EV64260_EXT_SRAM_SIZE
, 0);
153 bh
.ci
->enable_window_32bit(&bh
, MV64x60_CPU2DEV_0_WIN
);
154 mv64x60_set_32bit_window(&bh
, MV64x60_CPU2DEV_1_WIN
,
155 EV64260_TODC_BASE
, EV64260_TODC_SIZE
, 0);
156 bh
.ci
->enable_window_32bit(&bh
, MV64x60_CPU2DEV_1_WIN
);
157 mv64x60_set_32bit_window(&bh
, MV64x60_CPU2DEV_2_WIN
,
158 EV64260_UART_BASE
, EV64260_UART_SIZE
, 0);
159 bh
.ci
->enable_window_32bit(&bh
, MV64x60_CPU2DEV_2_WIN
);
160 mv64x60_set_32bit_window(&bh
, MV64x60_CPU2DEV_3_WIN
,
161 EV64260_EXT_FLASH_BASE
, EV64260_EXT_FLASH_SIZE
, 0);
162 bh
.ci
->enable_window_32bit(&bh
, MV64x60_CPU2DEV_3_WIN
);
164 TODC_INIT(TODC_TYPE_DS1501
, 0, 0,
165 ioremap(EV64260_TODC_BASE
, EV64260_TODC_SIZE
), 8);
167 mv64x60_clr_bits(&bh
, MV64x60_CPU_CONFIG
,((1<<12) | (1<<28) | (1<<29)));
168 mv64x60_set_bits(&bh
, MV64x60_CPU_CONFIG
, (1<<27));
170 if (ev64260_get_bus_speed() > 100000000)
171 mv64x60_set_bits(&bh
, MV64x60_CPU_CONFIG
, (1<<23));
173 mv64x60_set_bits(&bh
, MV64x60_PCI0_PCI_DECODE_CNTL
, ((1<<0) | (1<<3)));
174 mv64x60_set_bits(&bh
, MV64x60_PCI1_PCI_DECODE_CNTL
, ((1<<0) | (1<<3)));
177 * Enabling of PCI internal-vs-external arbitration
178 * is a platform- and errata-dependent decision.
180 if (bh
.type
== MV64x60_TYPE_GT64260A
) {
181 mv64x60_set_bits(&bh
, MV64x60_PCI0_ARBITER_CNTL
, (1<<31));
182 mv64x60_set_bits(&bh
, MV64x60_PCI1_ARBITER_CNTL
, (1<<31));
185 mv64x60_set_bits(&bh
, MV64x60_CPU_MASTER_CNTL
, (1<<9)); /* Only 1 cpu */
188 * Turn off timer/counters. Not turning off watchdog timer because
189 * can't read its reg on the 64260A so don't know if we'll be enabling
192 mv64x60_clr_bits(&bh
, MV64x60_TIMR_CNTR_0_3_CNTL
,
193 ((1<<0) | (1<<8) | (1<<16) | (1<<24)));
194 mv64x60_clr_bits(&bh
, GT64260_TIMR_CNTR_4_7_CNTL
,
195 ((1<<0) | (1<<8) | (1<<16) | (1<<24)));
198 * Set MPSC Multiplex RMII
199 * NOTE: ethernet driver modifies bit 0 and 1
201 mv64x60_write(&bh
, GT64260_MPP_SERIAL_PORTS_MULTIPLEX
, 0x00001102);
204 * The EV-64260-BP uses several Multi-Purpose Pins (MPP) on the 64260
205 * bridge as interrupt inputs (via the General Purpose Ports (GPP)
206 * register). Need to route the MPP inputs to the GPP and set the
207 * polarity correctly.
209 * In MPP Control 2 Register
210 * MPP 21 -> GPP 21 (DUART channel A intr) bits 20-23 -> 0
211 * MPP 22 -> GPP 22 (DUART channel B intr) bits 24-27 -> 0
213 mv64x60_clr_bits(&bh
, MV64x60_MPP_CNTL_2
, (0xf<<20) | (0xf<<24) );
216 * In MPP Control 3 Register
217 * MPP 26 -> GPP 26 (RTC INT) bits 8-11 -> 0
218 * MPP 27 -> GPP 27 (PCI 0 INTA) bits 12-15 -> 0
219 * MPP 29 -> GPP 29 (PCI 1 INTA) bits 20-23 -> 0
221 mv64x60_clr_bits(&bh
, MV64x60_MPP_CNTL_3
, (0xf<<8)|(0xf<<12)|(0xf<<20));
223 #define GPP_EXTERNAL_INTERRUPTS \
224 ((1<<21) | (1<<22) | (1<<26) | (1<<27) | (1<<29))
225 /* DUART & PCI interrupts are inputs */
226 mv64x60_clr_bits(&bh
, MV64x60_GPP_IO_CNTL
, GPP_EXTERNAL_INTERRUPTS
);
227 /* DUART & PCI interrupts are active low */
228 mv64x60_set_bits(&bh
, MV64x60_GPP_LEVEL_CNTL
, GPP_EXTERNAL_INTERRUPTS
);
230 /* Clear any pending interrupts for these inputs and enable them. */
231 mv64x60_write(&bh
, MV64x60_GPP_INTR_CAUSE
, ~GPP_EXTERNAL_INTERRUPTS
);
232 mv64x60_set_bits(&bh
, MV64x60_GPP_INTR_MASK
, GPP_EXTERNAL_INTERRUPTS
);
238 ev64260_setup_bridge(void)
240 struct mv64x60_setup_info si
;
243 memset(&si
, 0, sizeof(si
));
245 si
.phys_reg_base
= CONFIG_MV64X60_NEW_BASE
;
247 si
.pci_0
.enable_bus
= 1;
248 si
.pci_0
.pci_io
.cpu_base
= EV64260_PCI0_IO_CPU_BASE
;
249 si
.pci_0
.pci_io
.pci_base_hi
= 0;
250 si
.pci_0
.pci_io
.pci_base_lo
= EV64260_PCI0_IO_PCI_BASE
;
251 si
.pci_0
.pci_io
.size
= EV64260_PCI0_IO_SIZE
;
252 si
.pci_0
.pci_io
.swap
= MV64x60_CPU2PCI_SWAP_NONE
;
253 si
.pci_0
.pci_mem
[0].cpu_base
= EV64260_PCI0_MEM_CPU_BASE
;
254 si
.pci_0
.pci_mem
[0].pci_base_hi
= 0;
255 si
.pci_0
.pci_mem
[0].pci_base_lo
= EV64260_PCI0_MEM_PCI_BASE
;
256 si
.pci_0
.pci_mem
[0].size
= EV64260_PCI0_MEM_SIZE
;
257 si
.pci_0
.pci_mem
[0].swap
= MV64x60_CPU2PCI_SWAP_NONE
;
258 si
.pci_0
.pci_cmd_bits
= 0;
259 si
.pci_0
.latency_timer
= 0x8;
261 si
.pci_1
.enable_bus
= 1;
262 si
.pci_1
.pci_io
.cpu_base
= EV64260_PCI1_IO_CPU_BASE
;
263 si
.pci_1
.pci_io
.pci_base_hi
= 0;
264 si
.pci_1
.pci_io
.pci_base_lo
= EV64260_PCI1_IO_PCI_BASE
;
265 si
.pci_1
.pci_io
.size
= EV64260_PCI1_IO_SIZE
;
266 si
.pci_1
.pci_io
.swap
= MV64x60_CPU2PCI_SWAP_NONE
;
267 si
.pci_1
.pci_mem
[0].cpu_base
= EV64260_PCI1_MEM_CPU_BASE
;
268 si
.pci_1
.pci_mem
[0].pci_base_hi
= 0;
269 si
.pci_1
.pci_mem
[0].pci_base_lo
= EV64260_PCI1_MEM_PCI_BASE
;
270 si
.pci_1
.pci_mem
[0].size
= EV64260_PCI1_MEM_SIZE
;
271 si
.pci_1
.pci_mem
[0].swap
= MV64x60_CPU2PCI_SWAP_NONE
;
272 si
.pci_1
.pci_cmd_bits
= 0;
273 si
.pci_1
.latency_timer
= 0x8;
275 for (i
=0; i
<MV64x60_CPU2MEM_WINDOWS
; i
++) {
276 si
.cpu_prot_options
[i
] = 0;
277 si
.cpu_snoop_options
[i
] = GT64260_CPU_SNOOP_WB
;
278 si
.pci_0
.acc_cntl_options
[i
] =
279 GT64260_PCI_ACC_CNTL_DREADEN
|
280 GT64260_PCI_ACC_CNTL_RDPREFETCH
|
281 GT64260_PCI_ACC_CNTL_RDLINEPREFETCH
|
282 GT64260_PCI_ACC_CNTL_RDMULPREFETCH
|
283 GT64260_PCI_ACC_CNTL_SWAP_NONE
|
284 GT64260_PCI_ACC_CNTL_MBURST_32_BTYES
;
285 si
.pci_0
.snoop_options
[i
] = GT64260_PCI_SNOOP_WB
;
286 si
.pci_1
.acc_cntl_options
[i
] =
287 GT64260_PCI_ACC_CNTL_DREADEN
|
288 GT64260_PCI_ACC_CNTL_RDPREFETCH
|
289 GT64260_PCI_ACC_CNTL_RDLINEPREFETCH
|
290 GT64260_PCI_ACC_CNTL_RDMULPREFETCH
|
291 GT64260_PCI_ACC_CNTL_SWAP_NONE
|
292 GT64260_PCI_ACC_CNTL_MBURST_32_BTYES
;
293 si
.pci_1
.snoop_options
[i
] = GT64260_PCI_SNOOP_WB
;
296 /* Lookup PCI host bridges */
297 if (mv64x60_init(&bh
, &si
))
298 printk(KERN_ERR
"Bridge initialization failed.\n");
300 pci_dram_offset
= 0; /* System mem at same addr on PCI & cpu bus */
301 ppc_md
.pci_swizzle
= common_swizzle
;
302 ppc_md
.pci_map_irq
= ev64260_map_irq
;
303 ppc_md
.pci_exclude_device
= mv64x60_pci_exclude_device
;
305 mv64x60_set_bus(&bh
, 0, 0);
306 bh
.hose_a
->first_busno
= 0;
307 bh
.hose_a
->last_busno
= 0xff;
308 bh
.hose_a
->last_busno
= pciauto_bus_scan(bh
.hose_a
, 0);
310 bh
.hose_b
->first_busno
= bh
.hose_a
->last_busno
+ 1;
311 mv64x60_set_bus(&bh
, 1, bh
.hose_b
->first_busno
);
312 bh
.hose_b
->last_busno
= 0xff;
313 bh
.hose_b
->last_busno
= pciauto_bus_scan(bh
.hose_b
,
314 bh
.hose_b
->first_busno
);
319 #if defined(CONFIG_SERIAL_8250) && !defined(CONFIG_SERIAL_MPSC_CONSOLE)
321 ev64260_early_serial_map(void)
323 struct uart_port port
;
324 static char first_time
= 1;
327 memset(&port
, 0, sizeof(port
));
329 port
.membase
= ioremap(EV64260_SERIAL_0
, EV64260_UART_SIZE
);
330 port
.irq
= EV64260_UART_0_IRQ
;
331 port
.uartclk
= BASE_BAUD
* 16;
333 port
.iotype
= UPIO_MEM
;
334 port
.flags
= STD_COM_FLAGS
;
336 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
337 gen550_init(0, &port
);
340 if (early_serial_setup(&port
) != 0)
341 printk(KERN_WARNING
"Early serial init of port 0"
349 #elif defined(CONFIG_SERIAL_MPSC_CONSOLE)
351 ev64260_early_serial_map(void)
357 ev64260_setup_arch(void)
360 ppc_md
.progress("ev64260_setup_arch: enter", 0);
362 #ifdef CONFIG_BLK_DEV_INITRD
364 ROOT_DEV
= Root_RAM0
;
367 #ifdef CONFIG_ROOT_NFS
370 ROOT_DEV
= Root_SDA2
;
374 ppc_md
.progress("ev64260_setup_arch: Enabling L2 cache", 0);
376 /* Enable L2 and L3 caches (if 745x) */
377 _set_L2CR(_get_L2CR() | L2CR_L2E
);
378 _set_L3CR(_get_L3CR() | L3CR_L3E
);
381 ppc_md
.progress("ev64260_setup_arch: Initializing bridge", 0);
383 ev64260_setup_bridge(); /* set up PCI bridge(s) */
384 ev64260_setup_peripherals(); /* set up chip selects/GPP/MPP etc */
387 ppc_md
.progress("ev64260_setup_arch: bridge init complete", 0);
389 #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_MPSC_CONSOLE)
390 ev64260_early_serial_map();
393 printk(KERN_INFO
"%s %s port (C) 2001 MontaVista Software, Inc."
394 "(source@mvista.com)\n", BOARD_VENDOR
, BOARD_MACHINE
);
397 ppc_md
.progress("ev64260_setup_arch: exit", 0);
402 /* Platform device data fixup routines. */
403 #if defined(CONFIG_SERIAL_MPSC)
405 ev64260_fixup_mpsc_pdata(struct platform_device
*pdev
)
407 struct mpsc_pdata
*pdata
;
409 pdata
= (struct mpsc_pdata
*)pdev
->dev
.platform_data
;
411 pdata
->max_idle
= 40;
412 pdata
->default_baud
= EV64260_DEFAULT_BAUD
;
413 pdata
->brg_clk_src
= EV64260_MPSC_CLK_SRC
;
414 pdata
->brg_clk_freq
= EV64260_MPSC_CLK_FREQ
;
420 ev64260_platform_notify(struct device
*dev
)
424 void ((*rtn
)(struct platform_device
*pdev
));
426 { MPSC_CTLR_NAME
".0", ev64260_fixup_mpsc_pdata
},
427 { MPSC_CTLR_NAME
".1", ev64260_fixup_mpsc_pdata
},
429 struct platform_device
*pdev
;
432 if (dev
&& dev
->bus_id
)
433 for (i
=0; i
<ARRAY_SIZE(dev_map
); i
++)
434 if (!strncmp(dev
->bus_id
, dev_map
[i
].bus_id
,
437 pdev
= container_of(dev
,
438 struct platform_device
, dev
);
439 dev_map
[i
].rtn(pdev
);
447 ev64260_reset_board(void *addr
)
451 /* disable and invalidate the L2 cache */
455 /* flush and disable L1 I/D cache */
469 /* unmap any other random cs's that might overlap with bootcs */
470 mv64x60_set_32bit_window(&bh
, MV64x60_CPU2DEV_0_WIN
, 0, 0, 0);
471 bh
.ci
->disable_window_32bit(&bh
, MV64x60_CPU2DEV_0_WIN
);
472 mv64x60_set_32bit_window(&bh
, MV64x60_CPU2DEV_1_WIN
, 0, 0, 0);
473 bh
.ci
->disable_window_32bit(&bh
, MV64x60_CPU2DEV_1_WIN
);
474 mv64x60_set_32bit_window(&bh
, MV64x60_CPU2DEV_2_WIN
, 0, 0, 0);
475 bh
.ci
->disable_window_32bit(&bh
, MV64x60_CPU2DEV_2_WIN
);
476 mv64x60_set_32bit_window(&bh
, MV64x60_CPU2DEV_3_WIN
, 0, 0, 0);
477 bh
.ci
->disable_window_32bit(&bh
, MV64x60_CPU2DEV_3_WIN
);
479 /* map bootrom back in to gt @ reset defaults */
480 mv64x60_set_32bit_window(&bh
, MV64x60_CPU2BOOT_WIN
,
481 0xff800000, 8*1024*1024, 0);
482 bh
.ci
->enable_window_32bit(&bh
, MV64x60_CPU2BOOT_WIN
);
484 /* move reg base back to default, setup default pci0 */
485 mv64x60_write(&bh
, MV64x60_INTERNAL_SPACE_DECODE
,
486 (1<<24) | CONFIG_MV64X60_BASE
>> 20);
488 /* NOTE: FROM NOW ON no more GT_REGS accesses.. 0x1 is not mapped
489 * via BAT or MMU, and MSR IR/DR is ON */
490 /* SRR0 has system reset vector, SRR1 has default MSR value */
491 /* rfi restores MSR from SRR1 and sets the PC to the SRR0 value */
492 /* NOTE: assumes reset vector is at 0xfff00100 */
504 ev64260_restart(char *cmd
)
506 volatile ulong i
= 10000000;
508 ev64260_reset_board((void *)0xfff00100);
511 panic("restart failed\n");
523 ev64260_power_off(void)
530 ev64260_show_cpuinfo(struct seq_file
*m
)
534 pvid
= mfspr(SPRN_PVR
);
535 seq_printf(m
, "vendor\t\t: " BOARD_VENDOR
"\n");
536 seq_printf(m
, "machine\t\t: " BOARD_MACHINE
"\n");
537 seq_printf(m
, "cpu MHz\t\t: %d\n", ev64260_get_cpu_speed()/1000/1000);
538 seq_printf(m
, "bus MHz\t\t: %d\n", ev64260_get_bus_speed()/1000/1000);
543 /* DS1501 RTC has too much variation to use RTC for calibration */
545 ev64260_calibrate_decr(void)
549 freq
= ev64260_get_bus_speed()/4;
551 printk(KERN_INFO
"time_init: decrementer frequency = %lu.%.6lu MHz\n",
552 freq
/1000000, freq
%1000000);
554 tb_ticks_per_jiffy
= freq
/ HZ
;
555 tb_to_us
= mulhwu_scale_factor(freq
, 1000000);
561 * Set BAT 3 to map 0xfb000000 to 0xfc000000 of physical memory space.
563 static __inline__
void
564 ev64260_set_bat(void)
567 mtspr(SPRN_DBAT1U
, 0xfb0001fe);
568 mtspr(SPRN_DBAT1L
, 0xfb00002a);
574 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
578 io_block_mapping(0xfb000000, 0xfb000000, 0x01000000, _PAGE_IO
);
583 platform_init(unsigned long r3
, unsigned long r4
, unsigned long r5
,
584 unsigned long r6
, unsigned long r7
)
586 #ifdef CONFIG_BLK_DEV_INITRD
587 extern int initrd_below_start_ok
;
589 initrd_start
=initrd_end
=0;
590 initrd_below_start_ok
=0;
591 #endif /* CONFIG_BLK_DEV_INITRD */
593 parse_bootinfo(find_bootinfo());
596 isa_io_base
= EV64260_PCI0_IO_CPU_BASE
;
597 pci_dram_offset
= EV64260_PCI0_MEM_CPU_BASE
;
599 loops_per_jiffy
= ev64260_get_cpu_speed() / HZ
;
601 ppc_md
.setup_arch
= ev64260_setup_arch
;
602 ppc_md
.show_cpuinfo
= ev64260_show_cpuinfo
;
603 ppc_md
.init_IRQ
= gt64260_init_irq
;
604 ppc_md
.get_irq
= gt64260_get_irq
;
606 ppc_md
.restart
= ev64260_restart
;
607 ppc_md
.power_off
= ev64260_power_off
;
608 ppc_md
.halt
= ev64260_halt
;
610 ppc_md
.find_end_of_memory
= ev64260_find_end_of_memory
;
614 ppc_md
.time_init
= todc_time_init
;
615 ppc_md
.set_rtc_time
= todc_set_rtc_time
;
616 ppc_md
.get_rtc_time
= todc_get_rtc_time
;
617 ppc_md
.nvram_read_val
= todc_direct_read_val
;
618 ppc_md
.nvram_write_val
= todc_direct_write_val
;
619 ppc_md
.calibrate_decr
= ev64260_calibrate_decr
;
621 bh
.p_base
= CONFIG_MV64X60_NEW_BASE
;
625 #ifdef CONFIG_SERIAL_8250
626 #if defined(CONFIG_SERIAL_TEXT_DEBUG)
627 ppc_md
.setup_io_mappings
= ev64260_map_io
;
628 ppc_md
.progress
= gen550_progress
;
630 #if defined(CONFIG_KGDB)
631 ppc_md
.setup_io_mappings
= ev64260_map_io
;
632 ppc_md
.early_serial_map
= ev64260_early_serial_map
;
634 #elif defined(CONFIG_SERIAL_MPSC_CONSOLE)
635 #ifdef CONFIG_SERIAL_TEXT_DEBUG
636 ppc_md
.setup_io_mappings
= ev64260_map_io
;
637 ppc_md
.progress
= mv64x60_mpsc_progress
;
638 mv64x60_progress_init(CONFIG_MV64X60_NEW_BASE
);
639 #endif /* CONFIG_SERIAL_TEXT_DEBUG */
641 ppc_md
.setup_io_mappings
= ev64260_map_io
;
642 ppc_md
.early_serial_map
= ev64260_early_serial_map
;
643 #endif /* CONFIG_KGDB */
647 #if defined(CONFIG_SERIAL_MPSC)
648 platform_notify
= ev64260_platform_notify
;