arch/ppc/platforms/ev64360.c

   1 /*
   2  * arch/ppc/platforms/ev64360.c
   3  *
   4  * Board setup routines for the Marvell EV-64360-BP Evaluation Board.
   5  *
   6  * Author: Lee Nicks <allinux@gmail.com>
   7  *
   8  * Based on code done by Rabeeh Khoury - rabeeh@galileo.co.il
   9  * Based on code done by - Mark A. Greer <mgreer@mvista.com>
  10  *
  11  * This program is free software; you can redistribute it and/or modify it
  12  * under the terms of the GNU General Public License as published by the
  13  * Free Software Foundation; either version 2 of the License, or (at your
  14  * option) any later version.
  15  */
  16 #include <linux/config.h>
  17 #include <linux/kernel.h>
  18 #include <linux/pci.h>
  19 #include <linux/kdev_t.h>
  20 #include <linux/console.h>
  21 #include <linux/initrd.h>
  22 #include <linux/root_dev.h>
  23 #include <linux/delay.h>
  24 #include <linux/seq_file.h>
  25 #include <linux/bootmem.h>
  26 #include <linux/mtd/physmap.h>
  27 #include <linux/mv643xx.h>
  28 #include <linux/platform_device.h>
  29 #ifdef CONFIG_BOOTIMG
  30 #include <linux/bootimg.h>
  31 #endif
  32 #include <asm/page.h>
  33 #include <asm/time.h>
  34 #include <asm/smp.h>
  35 #include <asm/todc.h>
  36 #include <asm/bootinfo.h>
  37 #include <asm/ppcboot.h>
  38 #include <asm/mv64x60.h>
  39 #include <platforms/ev64360.h>
  40
  41 #define BOARD_VENDOR    "Marvell"
  42 #define BOARD_MACHINE   "EV-64360-BP"
  43
  44 static struct           mv64x60_handle bh;
  45 static void __iomem     *sram_base;
  46
  47 static u32              ev64360_flash_size_0;
  48 static u32              ev64360_flash_size_1;
  49
  50 static u32              ev64360_bus_frequency;
  51
  52 unsigned char   __res[sizeof(bd_t)];
  53
  54 static int __init
  55 ev64360_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
  56 {
  57         return 0;
  58 }
  59
  60 static void __init
  61 ev64360_setup_bridge(void)
  62 {
  63         struct mv64x60_setup_info si;
  64         int i;
  65
  66         memset(&si, 0, sizeof(si));
  67
  68         si.phys_reg_base = CONFIG_MV64X60_NEW_BASE;
  69
  70         #ifdef CONFIG_PCI
  71         si.pci_1.enable_bus = 1;
  72         si.pci_1.pci_io.cpu_base = EV64360_PCI1_IO_START_PROC_ADDR;
  73         si.pci_1.pci_io.pci_base_hi = 0;
  74         si.pci_1.pci_io.pci_base_lo = EV64360_PCI1_IO_START_PCI_ADDR;
  75         si.pci_1.pci_io.size = EV64360_PCI1_IO_SIZE;
  76         si.pci_1.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE;
  77         si.pci_1.pci_mem[0].cpu_base = EV64360_PCI1_MEM_START_PROC_ADDR;
  78         si.pci_1.pci_mem[0].pci_base_hi = EV64360_PCI1_MEM_START_PCI_HI_ADDR;
  79         si.pci_1.pci_mem[0].pci_base_lo = EV64360_PCI1_MEM_START_PCI_LO_ADDR;
  80         si.pci_1.pci_mem[0].size = EV64360_PCI1_MEM_SIZE;
  81         si.pci_1.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE;
  82         si.pci_1.pci_cmd_bits = 0;
  83         si.pci_1.latency_timer = 0x80;
  84         #else
  85         si.pci_0.enable_bus = 0;
  86         si.pci_1.enable_bus = 0;
  87         #endif
  88
  89         for (i = 0; i < MV64x60_CPU2MEM_WINDOWS; i++) {
  90 #if defined(CONFIG_NOT_COHERENT_CACHE)
  91                 si.cpu_prot_options[i] = 0;
  92                 si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE;
  93                 si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE;
  94                 si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE;
  95
  96                 si.pci_1.acc_cntl_options[i] =
  97                     MV64360_PCI_ACC_CNTL_SNOOP_NONE |
  98                     MV64360_PCI_ACC_CNTL_SWAP_NONE |
  99                     MV64360_PCI_ACC_CNTL_MBURST_128_BYTES |
 100                     MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;
 101 #else
 102                 si.cpu_prot_options[i] = 0;
 103                 si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE; /* errata */
 104                 si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE; /* errata */
 105                 si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE; /* errata */
 106
 107                 si.pci_1.acc_cntl_options[i] =
 108                     MV64360_PCI_ACC_CNTL_SNOOP_WB |
 109                     MV64360_PCI_ACC_CNTL_SWAP_NONE |
 110                     MV64360_PCI_ACC_CNTL_MBURST_32_BYTES |
 111                     MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES;
 112 #endif
 113         }
 114
 115         if (mv64x60_init(&bh, &si))
 116                 printk(KERN_WARNING "Bridge initialization failed.\n");
 117
 118         #ifdef CONFIG_PCI
 119         pci_dram_offset = 0; /* sys mem at same addr on PCI & cpu bus */
 120         ppc_md.pci_swizzle = common_swizzle;
 121         ppc_md.pci_map_irq = ev64360_map_irq;
 122         ppc_md.pci_exclude_device = mv64x60_pci_exclude_device;
 123
 124         mv64x60_set_bus(&bh, 1, 0);
 125         bh.hose_b->first_busno = 0;
 126         bh.hose_b->last_busno = 0xff;
 127         #endif
 128 }
 129
 130 /* Bridge & platform setup routines */
 131 void __init
 132 ev64360_intr_setup(void)
 133 {
 134         /* MPP 8, 9, and 10 */
 135         mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_1, 0xfff);
 136
 137         /*
 138          * Define GPP 8,9,and 10 interrupt polarity as active low
 139          * input signal and level triggered
 140          */
 141         mv64x60_set_bits(&bh, MV64x60_GPP_LEVEL_CNTL, 0x700);
 142         mv64x60_clr_bits(&bh, MV64x60_GPP_IO_CNTL, 0x700);
 143
 144         /* Config GPP intr ctlr to respond to level trigger */
 145         mv64x60_set_bits(&bh, MV64x60_COMM_ARBITER_CNTL, (1<<10));
 146
 147         /* Erranum FEr PCI-#8 */
 148         mv64x60_clr_bits(&bh, MV64x60_PCI0_CMD, (1<<5) | (1<<9));
 149         mv64x60_clr_bits(&bh, MV64x60_PCI1_CMD, (1<<5) | (1<<9));
 150
 151         /*
 152          * Dismiss and then enable interrupt on GPP interrupt cause
 153          * for CPU #0
 154          */
 155         mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, ~0x700);
 156         mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK, 0x700);
 157
 158         /*
 159          * Dismiss and then enable interrupt on CPU #0 high cause reg
 160          * BIT25 summarizes GPP interrupts 8-15
 161          */
 162         mv64x60_set_bits(&bh, MV64360_IC_CPU0_INTR_MASK_HI, (1<<25));
 163 }
 164
 165 void __init
 166 ev64360_setup_peripherals(void)
 167 {
 168         u32 base;
 169
 170         /* Set up window for boot CS */
 171         mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN,
 172                  EV64360_BOOT_WINDOW_BASE, EV64360_BOOT_WINDOW_SIZE, 0);
 173         bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);
 174
 175         /* We only use the 32-bit flash */
 176         mv64x60_get_32bit_window(&bh, MV64x60_CPU2BOOT_WIN, &base,
 177                 &ev64360_flash_size_0);
 178         ev64360_flash_size_1 = 0;
 179
 180         mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN,
 181                  EV64360_RTC_WINDOW_BASE, EV64360_RTC_WINDOW_SIZE, 0);
 182         bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN);
 183
 184         mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN,
 185                  EV64360_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, 0);
 186         bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN);
 187         sram_base = ioremap(EV64360_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE);
 188
 189         /* Set up Enet->SRAM window */
 190         mv64x60_set_32bit_window(&bh, MV64x60_ENET2MEM_4_WIN,
 191                 EV64360_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, 0x2);
 192         bh.ci->enable_window_32bit(&bh, MV64x60_ENET2MEM_4_WIN);
 193
 194         /* Give enet r/w access to memory region */
 195         mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_0, (0x3 << (4 << 1)));
 196         mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_1, (0x3 << (4 << 1)));
 197         mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_2, (0x3 << (4 << 1)));
 198
 199         mv64x60_clr_bits(&bh, MV64x60_PCI1_PCI_DECODE_CNTL, (1 << 3));
 200         mv64x60_clr_bits(&bh, MV64x60_TIMR_CNTR_0_3_CNTL,
 201                          ((1 << 0) | (1 << 8) | (1 << 16) | (1 << 24)));
 202
 203 #if defined(CONFIG_NOT_COHERENT_CACHE)
 204         mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x00160000);
 205 #else
 206         mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b2);
 207 #endif
 208
 209         /*
 210          * Setting the SRAM to 0. Note that this generates parity errors on
 211          * internal data path in SRAM since it's first time accessing it
 212          * while after reset it's not configured.
 213          */
 214         memset(sram_base, 0, MV64360_SRAM_SIZE);
 215
 216         /* set up PCI interrupt controller */
 217         ev64360_intr_setup();
 218 }
 219
 220 static void __init
 221 ev64360_setup_arch(void)
 222 {
 223         if (ppc_md.progress)
 224                 ppc_md.progress("ev64360_setup_arch: enter", 0);
 225
 226         set_tb(0, 0);
 227
 228 #ifdef CONFIG_BLK_DEV_INITRD
 229         if (initrd_start)
 230                 ROOT_DEV = Root_RAM0;
 231         else
 232 #endif
 233 #ifdef   CONFIG_ROOT_NFS
 234                 ROOT_DEV = Root_NFS;
 235 #else
 236                 ROOT_DEV = Root_SDA2;
 237 #endif
 238
 239         /*
 240          * Set up the L2CR register.
 241          */
 242         _set_L2CR(L2CR_L2E | L2CR_L2PE);
 243
 244         if (ppc_md.progress)
 245                 ppc_md.progress("ev64360_setup_arch: calling setup_bridge", 0);
 246
 247         ev64360_setup_bridge();
 248         ev64360_setup_peripherals();
 249         ev64360_bus_frequency = ev64360_bus_freq();
 250
 251         printk(KERN_INFO "%s %s port (C) 2005 Lee Nicks "
 252                 "(allinux@gmail.com)\n", BOARD_VENDOR, BOARD_MACHINE);
 253         if (ppc_md.progress)
 254                 ppc_md.progress("ev64360_setup_arch: exit", 0);
 255 }
 256
 257 /* Platform device data fixup routines. */
 258 #if defined(CONFIG_SERIAL_MPSC)
 259 static void __init
 260 ev64360_fixup_mpsc_pdata(struct platform_device *pdev)
 261 {
 262         struct mpsc_pdata *pdata;
 263
 264         pdata = (struct mpsc_pdata *)pdev->dev.platform_data;
 265
 266         pdata->max_idle = 40;
 267         pdata->default_baud = EV64360_DEFAULT_BAUD;
 268         pdata->brg_clk_src = EV64360_MPSC_CLK_SRC;
 269         /*
 270          * TCLK (not SysCLk) is routed to BRG, then to the MPSC.  On most parts,
 271          * TCLK == SysCLK but on 64460, they are separate pins.
 272          * SysCLK can go up to 200 MHz but TCLK can only go up to 133 MHz.
 273          */
 274         pdata->brg_clk_freq = min(ev64360_bus_frequency, MV64x60_TCLK_FREQ_MAX);
 275 }
 276 #endif
 277
 278 #if defined(CONFIG_MV643XX_ETH)
 279 static void __init
 280 ev64360_fixup_eth_pdata(struct platform_device *pdev)
 281 {
 282         struct mv643xx_eth_platform_data *eth_pd;
 283         static u16 phy_addr[] = {
 284                 EV64360_ETH0_PHY_ADDR,
 285                 EV64360_ETH1_PHY_ADDR,
 286                 EV64360_ETH2_PHY_ADDR,
 287         };
 288
 289         eth_pd = pdev->dev.platform_data;
 290         eth_pd->force_phy_addr = 1;
 291         eth_pd->phy_addr = phy_addr[pdev->id];
 292         eth_pd->tx_queue_size = EV64360_ETH_TX_QUEUE_SIZE;
 293         eth_pd->rx_queue_size = EV64360_ETH_RX_QUEUE_SIZE;
 294 }
 295 #endif
 296
 297 static int __init
 298 ev64360_platform_notify(struct device *dev)
 299 {
 300         static struct {
 301                 char    *bus_id;
 302                 void    ((*rtn)(struct platform_device *pdev));
 303         } dev_map[] = {
 304 #if defined(CONFIG_SERIAL_MPSC)
 305                 { MPSC_CTLR_NAME ".0", ev64360_fixup_mpsc_pdata },
 306                 { MPSC_CTLR_NAME ".1", ev64360_fixup_mpsc_pdata },
 307 #endif
 308 #if defined(CONFIG_MV643XX_ETH)
 309                 { MV643XX_ETH_NAME ".0", ev64360_fixup_eth_pdata },
 310                 { MV643XX_ETH_NAME ".1", ev64360_fixup_eth_pdata },
 311                 { MV643XX_ETH_NAME ".2", ev64360_fixup_eth_pdata },
 312 #endif
 313         };
 314         struct platform_device  *pdev;
 315         int     i;
 316
 317         if (dev && dev->bus_id)
 318                 for (i=0; i<ARRAY_SIZE(dev_map); i++)
 319                         if (!strncmp(dev->bus_id, dev_map[i].bus_id,
 320                                 BUS_ID_SIZE)) {
 321
 322                                 pdev = container_of(dev,
 323                                         struct platform_device, dev);
 324                                 dev_map[i].rtn(pdev);
 325                         }
 326
 327         return 0;
 328 }
 329
 330 #ifdef CONFIG_MTD_PHYSMAP
 331
 332 #ifndef MB
 333 #define MB      (1 << 20)
 334 #endif
 335
 336 /*
 337  * MTD Layout.
 338  *
 339  * FLASH Amount:        0xff000000 - 0xffffffff
 340  * -------------        -----------------------
 341  * Reserved:            0xff000000 - 0xff03ffff
 342  * JFFS2 file system:   0xff040000 - 0xffefffff
 343  * U-boot:              0xfff00000 - 0xffffffff
 344  */
 345 static int __init
 346 ev64360_setup_mtd(void)
 347 {
 348         u32     size;
 349         int     ptbl_entries;
 350         static struct mtd_partition     *ptbl;
 351
 352         size = ev64360_flash_size_0 + ev64360_flash_size_1;
 353         if (!size)
 354                 return -ENOMEM;
 355
 356         ptbl_entries = 3;
 357
 358         if ((ptbl = kmalloc(ptbl_entries * sizeof(struct mtd_partition),
 359                 GFP_KERNEL)) == NULL) {
 360
 361                 printk(KERN_WARNING "Can't alloc MTD partition table\n");
 362                 return -ENOMEM;
 363         }
 364         memset(ptbl, 0, ptbl_entries * sizeof(struct mtd_partition));
 365
 366         ptbl[0].name = "reserved";
 367         ptbl[0].offset = 0;
 368         ptbl[0].size = EV64360_MTD_RESERVED_SIZE;
 369         ptbl[1].name = "jffs2";
 370         ptbl[1].offset = EV64360_MTD_RESERVED_SIZE;
 371         ptbl[1].size = EV64360_MTD_JFFS2_SIZE;
 372         ptbl[2].name = "U-BOOT";
 373         ptbl[2].offset = EV64360_MTD_RESERVED_SIZE + EV64360_MTD_JFFS2_SIZE;
 374         ptbl[2].size = EV64360_MTD_UBOOT_SIZE;
 375
 376         physmap_map.size = size;
 377         physmap_set_partitions(ptbl, ptbl_entries);
 378         return 0;
 379 }
 380
 381 arch_initcall(ev64360_setup_mtd);
 382 #endif
 383
 384 static void
 385 ev64360_restart(char *cmd)
 386 {
 387         ulong   i = 0xffffffff;
 388         volatile unsigned char * rtc_base = ioremap(EV64360_RTC_WINDOW_BASE,0x4000);
 389
 390         /* issue hard reset */
 391         rtc_base[0xf] = 0x80;
 392         rtc_base[0xc] = 0x00;
 393         rtc_base[0xd] = 0x01;
 394         rtc_base[0xf] = 0x83;
 395
 396         while (i-- > 0) ;
 397         panic("restart failed\n");
 398 }
 399
 400 static void
 401 ev64360_halt(void)
 402 {
 403         while (1) ;
 404         /* NOTREACHED */
 405 }
 406
 407 static void
 408 ev64360_power_off(void)
 409 {
 410         ev64360_halt();
 411         /* NOTREACHED */
 412 }
 413
 414 static int
 415 ev64360_show_cpuinfo(struct seq_file *m)
 416 {
 417         seq_printf(m, "vendor\t\t: " BOARD_VENDOR "\n");
 418         seq_printf(m, "machine\t\t: " BOARD_MACHINE "\n");
 419         seq_printf(m, "bus speed\t: %dMHz\n", ev64360_bus_frequency/1000/1000);
 420
 421         return 0;
 422 }
 423
 424 static void __init
 425 ev64360_calibrate_decr(void)
 426 {
 427         u32 freq;
 428
 429         freq = ev64360_bus_frequency / 4;
 430
 431         printk(KERN_INFO "time_init: decrementer frequency = %lu.%.6lu MHz\n",
 432                (long)freq / 1000000, (long)freq % 1000000);
 433
 434         tb_ticks_per_jiffy = freq / HZ;
 435         tb_to_us = mulhwu_scale_factor(freq, 1000000);
 436 }
 437
 438 unsigned long __init
 439 ev64360_find_end_of_memory(void)
 440 {
 441         return mv64x60_get_mem_size(CONFIG_MV64X60_NEW_BASE,
 442                 MV64x60_TYPE_MV64360);
 443 }
 444
 445 static inline void
 446 ev64360_set_bat(void)
 447 {
 448         mb();
 449         mtspr(SPRN_DBAT2U, 0xf0001ffe);
 450         mtspr(SPRN_DBAT2L, 0xf000002a);
 451         mb();
 452 }
 453
 454 #if defined(CONFIG_SERIAL_TEXT_DEBUG) && defined(CONFIG_SERIAL_MPSC_CONSOLE)
 455 static void __init
 456 ev64360_map_io(void)
 457 {
 458         io_block_mapping(CONFIG_MV64X60_NEW_BASE, \
 459                          CONFIG_MV64X60_NEW_BASE, \
 460                          0x00020000, _PAGE_IO);
 461 }
 462 #endif
 463
 464 void __init
 465 platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
 466               unsigned long r6, unsigned long r7)
 467 {
 468         parse_bootinfo(find_bootinfo());
 469
 470         /* ASSUMPTION:  If both r3 (bd_t pointer) and r6 (cmdline pointer)
 471          * are non-zero, then we should use the board info from the bd_t
 472          * structure and the cmdline pointed to by r6 instead of the
 473          * information from birecs, if any.  Otherwise, use the information
 474          * from birecs as discovered by the preceeding call to
 475          * parse_bootinfo().  This rule should work with both PPCBoot, which
 476          * uses a bd_t board info structure, and the kernel boot wrapper,
 477          * which uses birecs.
 478          */
 479         if (r3 && r6) {
 480                 /* copy board info structure */
 481                 memcpy( (void *)__res,(void *)(r3+KERNELBASE), sizeof(bd_t) );
 482                 /* copy command line */
 483                 *(char *)(r7+KERNELBASE) = 0;
 484                 strcpy(cmd_line, (char *)(r6+KERNELBASE));
 485         }
 486         #ifdef CONFIG_ISA
 487         isa_mem_base = 0;
 488         #endif
 489
 490         ppc_md.setup_arch = ev64360_setup_arch;
 491         ppc_md.show_cpuinfo = ev64360_show_cpuinfo;
 492         ppc_md.init_IRQ = mv64360_init_irq;
 493         ppc_md.get_irq = mv64360_get_irq;
 494         ppc_md.restart = ev64360_restart;
 495         ppc_md.power_off = ev64360_power_off;
 496         ppc_md.halt = ev64360_halt;
 497         ppc_md.find_end_of_memory = ev64360_find_end_of_memory;
 498         ppc_md.calibrate_decr = ev64360_calibrate_decr;
 499
 500 #if defined(CONFIG_SERIAL_TEXT_DEBUG) && defined(CONFIG_SERIAL_MPSC_CONSOLE)
 501         ppc_md.setup_io_mappings = ev64360_map_io;
 502         ppc_md.progress = mv64x60_mpsc_progress;
 503         mv64x60_progress_init(CONFIG_MV64X60_NEW_BASE);
 504 #endif
 505
 506 #if defined(CONFIG_SERIAL_MPSC) || defined(CONFIG_MV643XX_ETH)
 507         platform_notify = ev64360_platform_notify;
 508 #endif
 509
 510         ev64360_set_bat(); /* Need for ev64360_find_end_of_memory and progress */
 511 }