arch/ppc/platforms/mpc8272ads_setup.c

   1 /*
   2  * arch/ppc/platforms/mpc8272ads_setup.c
   3  *
   4  * MPC82xx Board-specific PlatformDevice descriptions
   5  *
   6  * 2005 (c) MontaVista Software, Inc.
   7  * Vitaly Bordug <vbordug@ru.mvista.com>
   8  *
   9  * This file is licensed under the terms of the GNU General Public License
  10  * version 2. This program is licensed "as is" without any warranty of any
  11  * kind, whether express or implied.
  12  */
  13
  14
  15 #include <linux/init.h>
  16 #include <linux/module.h>
  17 #include <linux/device.h>
  18 #include <linux/ioport.h>
  19 #include <linux/fs_enet_pd.h>
  20 #include <linux/platform_device.h>
  21
  22 #include <asm/io.h>
  23 #include <asm/mpc8260.h>
  24 #include <asm/cpm2.h>
  25 #include <asm/immap_cpm2.h>
  26 #include <asm/irq.h>
  27 #include <asm/ppc_sys.h>
  28 #include <asm/ppcboot.h>
  29 #include <linux/fs_uart_pd.h>
  30
  31 #include "pq2ads_pd.h"
  32
  33 static void init_fcc1_ioports(void);
  34 static void init_fcc2_ioports(void);
  35 static void init_scc1_uart_ioports(void);
  36 static void init_scc4_uart_ioports(void);
  37
  38 static struct fs_uart_platform_info mpc8272_uart_pdata[] = {
  39         [fsid_scc1_uart] = {
  40                 .init_ioports   = init_scc1_uart_ioports,
  41                 .fs_no          = fsid_scc1_uart,
  42                 .brg            = 1,
  43                 .tx_num_fifo    = 4,
  44                 .tx_buf_size    = 32,
  45                 .rx_num_fifo    = 4,
  46                 .rx_buf_size    = 32,
  47         },
  48         [fsid_scc4_uart] = {
  49                 .init_ioports   = init_scc4_uart_ioports,
  50                 .fs_no          = fsid_scc4_uart,
  51                 .brg            = 4,
  52                 .tx_num_fifo    = 4,
  53                 .tx_buf_size    = 32,
  54                 .rx_num_fifo    = 4,
  55                 .rx_buf_size    = 32,
  56         },
  57 };
  58
  59 static struct fs_mii_bb_platform_info m82xx_mii_bb_pdata = {
  60         .mdio_dat.bit   = 18,
  61         .mdio_dir.bit   = 18,
  62         .mdc_dat.bit    = 19,
  63         .delay          = 1,
  64 };
  65
  66 static struct fs_platform_info mpc82xx_enet_pdata[] = {
  67         [fsid_fcc1] = {
  68                 .fs_no          = fsid_fcc1,
  69                 .cp_page        = CPM_CR_FCC1_PAGE,
  70                 .cp_block       = CPM_CR_FCC1_SBLOCK,
  71
  72                 .clk_trx        = (PC_F1RXCLK | PC_F1TXCLK),
  73                 .clk_route      = CMX1_CLK_ROUTE,
  74                 .clk_mask       = CMX1_CLK_MASK,
  75                 .init_ioports   = init_fcc1_ioports,
  76
  77                 .mem_offset     = FCC1_MEM_OFFSET,
  78
  79                 .rx_ring        = 32,
  80                 .tx_ring        = 32,
  81                 .rx_copybreak   = 240,
  82                 .use_napi       = 0,
  83                 .napi_weight    = 17,
  84                 .bus_id         = "0:00",
  85         },
  86         [fsid_fcc2] = {
  87                 .fs_no          = fsid_fcc2,
  88                 .cp_page        = CPM_CR_FCC2_PAGE,
  89                 .cp_block       = CPM_CR_FCC2_SBLOCK,
  90                 .clk_trx        = (PC_F2RXCLK | PC_F2TXCLK),
  91                 .clk_route      = CMX2_CLK_ROUTE,
  92                 .clk_mask       = CMX2_CLK_MASK,
  93                 .init_ioports   = init_fcc2_ioports,
  94
  95                 .mem_offset     = FCC2_MEM_OFFSET,
  96
  97                 .rx_ring        = 32,
  98                 .tx_ring        = 32,
  99                 .rx_copybreak   = 240,
 100                 .use_napi       = 0,
 101                 .napi_weight    = 17,
 102                 .bus_id         = "0:03",
 103         },
 104 };
 105
 106 static void init_fcc1_ioports(struct fs_platform_info*)
 107 {
 108         struct io_port *io;
 109         u32 tempval;
 110         cpm2_map_t* immap = ioremap(CPM_MAP_ADDR, sizeof(cpm2_map_t));
 111         u32 *bcsr = ioremap(BCSR_ADDR+4, sizeof(u32));
 112
 113         io = &immap->im_ioport;
 114
 115         /* Enable the PHY */
 116         clrbits32(bcsr, BCSR1_FETHIEN);
 117         setbits32(bcsr, BCSR1_FETH_RST);
 118
 119         /* FCC1 pins are on port A/C. */
 120         /* Configure port A and C pins for FCC1 Ethernet. */
 121
 122         tempval = in_be32(&io->iop_pdira);
 123         tempval &= ~PA1_DIRA0;
 124         tempval |= PA1_DIRA1;
 125         out_be32(&io->iop_pdira, tempval);
 126
 127         tempval = in_be32(&io->iop_psora);
 128         tempval &= ~PA1_PSORA0;
 129         tempval |= PA1_PSORA1;
 130         out_be32(&io->iop_psora, tempval);
 131
 132         setbits32(&io->iop_ppara,PA1_DIRA0 | PA1_DIRA1);
 133
 134         /* Alter clocks */
 135         tempval = PC_F1TXCLK|PC_F1RXCLK;
 136
 137         clrbits32(&io->iop_psorc, tempval);
 138         clrbits32(&io->iop_pdirc, tempval);
 139         setbits32(&io->iop_pparc, tempval);
 140
 141         clrbits32(&immap->im_cpmux.cmx_fcr, CMX1_CLK_MASK);
 142         setbits32(&immap->im_cpmux.cmx_fcr, CMX1_CLK_ROUTE);
 143         iounmap(bcsr);
 144         iounmap(immap);
 145 }
 146
 147 static void init_fcc2_ioports(struct fs_platform_info*)
 148 {
 149         cpm2_map_t* immap = ioremap(CPM_MAP_ADDR, sizeof(cpm2_map_t));
 150         u32 *bcsr = ioremap(BCSR_ADDR+12, sizeof(u32));
 151
 152         struct io_port *io;
 153         u32 tempval;
 154
 155         immap = cpm2_immr;
 156
 157         io = &immap->im_ioport;
 158
 159         /* Enable the PHY */
 160         clrbits32(bcsr, BCSR3_FETHIEN2);
 161         setbits32(bcsr, BCSR3_FETH2_RST);
 162
 163         /* FCC2 are port B/C. */
 164         /* Configure port A and C pins for FCC2 Ethernet. */
 165
 166         tempval = in_be32(&io->iop_pdirb);
 167         tempval &= ~PB2_DIRB0;
 168         tempval |= PB2_DIRB1;
 169         out_be32(&io->iop_pdirb, tempval);
 170
 171         tempval = in_be32(&io->iop_psorb);
 172         tempval &= ~PB2_PSORB0;
 173         tempval |= PB2_PSORB1;
 174         out_be32(&io->iop_psorb, tempval);
 175
 176         setbits32(&io->iop_pparb,PB2_DIRB0 | PB2_DIRB1);
 177
 178         tempval = PC_F2RXCLK|PC_F2TXCLK;
 179
 180         /* Alter clocks */
 181         clrbits32(&io->iop_psorc,tempval);
 182         clrbits32(&io->iop_pdirc,tempval);
 183         setbits32(&io->iop_pparc,tempval);
 184
 185         clrbits32(&immap->im_cpmux.cmx_fcr, CMX2_CLK_MASK);
 186         setbits32(&immap->im_cpmux.cmx_fcr, CMX2_CLK_ROUTE);
 187
 188         iounmap(bcsr);
 189         iounmap(immap);
 190 }
 191
 192
 193 static void __init mpc8272ads_fixup_enet_pdata(struct platform_device *pdev,
 194                                               int idx)
 195 {
 196         bd_t* bi = (void*)__res;
 197         int fs_no = fsid_fcc1+pdev->id-1;
 198
 199         if(fs_no > ARRAY_SIZE(mpc82xx_enet_pdata)) {
 200                 return;
 201         }
 202
 203         mpc82xx_enet_pdata[fs_no].dpram_offset=
 204                         (u32)cpm2_immr->im_dprambase;
 205         mpc82xx_enet_pdata[fs_no].fcc_regs_c =
 206                         (u32)cpm2_immr->im_fcc_c;
 207         memcpy(&mpc82xx_enet_pdata[fs_no].macaddr,bi->bi_enetaddr,6);
 208
 209         /* prevent dup mac */
 210         if(fs_no == fsid_fcc2)
 211                 mpc82xx_enet_pdata[fs_no].macaddr[5] ^= 1;
 212
 213         pdev->dev.platform_data = &mpc82xx_enet_pdata[fs_no];
 214 }
 215
 216 static void mpc8272ads_fixup_uart_pdata(struct platform_device *pdev,
 217                                               int idx)
 218 {
 219         bd_t *bd = (bd_t *) __res;
 220         struct fs_uart_platform_info *pinfo;
 221         int num = ARRAY_SIZE(mpc8272_uart_pdata);
 222         int id = fs_uart_id_scc2fsid(idx);
 223
 224         /* no need to alter anything if console */
 225         if ((id <= num) && (!pdev->dev.platform_data)) {
 226                 pinfo = &mpc8272_uart_pdata[id];
 227                 pinfo->uart_clk = bd->bi_intfreq;
 228                 pdev->dev.platform_data = pinfo;
 229         }
 230 }
 231
 232 static void init_scc1_uart_ioports(struct fs_uart_platform_info*)
 233 {
 234         cpm2_map_t* immap = ioremap(CPM_MAP_ADDR, sizeof(cpm2_map_t));
 235
 236         /* SCC1 is only on port D */
 237         setbits32(&immap->im_ioport.iop_ppard,0x00000003);
 238         clrbits32(&immap->im_ioport.iop_psord,0x00000001);
 239         setbits32(&immap->im_ioport.iop_psord,0x00000002);
 240         clrbits32(&immap->im_ioport.iop_pdird,0x00000001);
 241         setbits32(&immap->im_ioport.iop_pdird,0x00000002);
 242
 243         /* Wire BRG1 to SCC1 */
 244         clrbits32(&immap->im_cpmux.cmx_scr,0x00ffffff);
 245
 246         iounmap(immap);
 247 }
 248
 249 static void init_scc4_uart_ioports(struct fs_uart_platform_info*)
 250 {
 251         cpm2_map_t* immap = ioremap(CPM_MAP_ADDR, sizeof(cpm2_map_t));
 252
 253         setbits32(&immap->im_ioport.iop_ppard,0x00000600);
 254         clrbits32(&immap->im_ioport.iop_psord,0x00000600);
 255         clrbits32(&immap->im_ioport.iop_pdird,0x00000200);
 256         setbits32(&immap->im_ioport.iop_pdird,0x00000400);
 257
 258         /* Wire BRG4 to SCC4 */
 259         clrbits32(&immap->im_cpmux.cmx_scr,0x000000ff);
 260         setbits32(&immap->im_cpmux.cmx_scr,0x0000001b);
 261
 262         iounmap(immap);
 263 }
 264
 265 static void __init mpc8272ads_fixup_mdio_pdata(struct platform_device *pdev,
 266                                               int idx)
 267 {
 268         m82xx_mii_bb_pdata.irq[0] = PHY_INTERRUPT;
 269         m82xx_mii_bb_pdata.irq[1] = -1;
 270         m82xx_mii_bb_pdata.irq[2] = -1;
 271         m82xx_mii_bb_pdata.irq[3] = PHY_INTERRUPT;
 272         m82xx_mii_bb_pdata.irq[31] = -1;
 273
 274
 275         m82xx_mii_bb_pdata.mdio_dat.offset =
 276                                 (u32)&cpm2_immr->im_ioport.iop_pdatc;
 277
 278         m82xx_mii_bb_pdata.mdio_dir.offset =
 279                                 (u32)&cpm2_immr->im_ioport.iop_pdirc;
 280
 281         m82xx_mii_bb_pdata.mdc_dat.offset =
 282                                 (u32)&cpm2_immr->im_ioport.iop_pdatc;
 283
 284
 285         pdev->dev.platform_data = &m82xx_mii_bb_pdata;
 286 }
 287
 288 static int mpc8272ads_platform_notify(struct device *dev)
 289 {
 290         static const struct platform_notify_dev_map dev_map[] = {
 291                 {
 292                         .bus_id = "fsl-cpm-fcc",
 293                         .rtn = mpc8272ads_fixup_enet_pdata,
 294                 },
 295                 {
 296                         .bus_id = "fsl-cpm-scc:uart",
 297                         .rtn = mpc8272ads_fixup_uart_pdata,
 298                 },
 299                 {
 300                         .bus_id = "fsl-bb-mdio",
 301                         .rtn = mpc8272ads_fixup_mdio_pdata,
 302                 },
 303                 {
 304                         .bus_id = NULL
 305                 }
 306         };
 307         platform_notify_map(dev_map,dev);
 308
 309         return 0;
 310
 311 }
 312
 313 int __init mpc8272ads_init(void)
 314 {
 315         printk(KERN_NOTICE "mpc8272ads: Init\n");
 316
 317         platform_notify = mpc8272ads_platform_notify;
 318
 319         ppc_sys_device_initfunc();
 320
 321         ppc_sys_device_disable_all();
 322         ppc_sys_device_enable(MPC82xx_CPM_FCC1);
 323         ppc_sys_device_enable(MPC82xx_CPM_FCC2);
 324
 325         /* to be ready for console, let's attach pdata here */
 326 #ifdef CONFIG_SERIAL_CPM_SCC1
 327         ppc_sys_device_setfunc(MPC82xx_CPM_SCC1, PPC_SYS_FUNC_UART);
 328         ppc_sys_device_enable(MPC82xx_CPM_SCC1);
 329
 330 #endif
 331
 332 #ifdef CONFIG_SERIAL_CPM_SCC4
 333         ppc_sys_device_setfunc(MPC82xx_CPM_SCC4, PPC_SYS_FUNC_UART);
 334         ppc_sys_device_enable(MPC82xx_CPM_SCC4);
 335 #endif
 336
 337         ppc_sys_device_enable(MPC82xx_MDIO_BB);
 338
 339         return 0;
 340 }
 341
 342 /*
 343    To prevent confusion, console selection is gross:
 344    by 0 assumed SCC1 and by 1 assumed SCC4
 345  */
 346 struct platform_device* early_uart_get_pdev(int index)
 347 {
 348         bd_t *bd = (bd_t *) __res;
 349         struct fs_uart_platform_info *pinfo;
 350
 351         struct platform_device* pdev = NULL;
 352         if(index) { /*assume SCC4 here*/
 353                 pdev = &ppc_sys_platform_devices[MPC82xx_CPM_SCC4];
 354                 pinfo = &mpc8272_uart_pdata[fsid_scc4_uart];
 355         } else { /*over SCC1*/
 356                 pdev = &ppc_sys_platform_devices[MPC82xx_CPM_SCC1];
 357                 pinfo = &mpc8272_uart_pdata[fsid_scc1_uart];
 358         }
 359
 360         pinfo->uart_clk = bd->bi_intfreq;
 361         pdev->dev.platform_data = pinfo;
 362         ppc_sys_fixup_mem_resource(pdev, CPM_MAP_ADDR);
 363         return NULL;
 364 }
 365
 366 arch_initcall(mpc8272ads_init);