arch/ppc/syslib/ibm44x_common.c

   1 /*
   2  * arch/ppc/syslib/ibm44x_common.c
   3  *
   4  * PPC44x system library
   5  *
   6  * Matt Porter <mporter@kernel.crashing.org>
   7  * Copyright 2002-2005 MontaVista Software Inc.
   8  *
   9  * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
  10  * Copyright (c) 2003, 2004 Zultys Technologies
  11  *
  12  * This program is free software; you can redistribute  it and/or modify it
  13  * under  the terms of  the GNU General  Public License as published by the
  14  * Free Software Foundation;  either version 2 of the  License, or (at your
  15  * option) any later version.
  16  *
  17  */
  18 #include <linux/config.h>
  19 #include <linux/time.h>
  20 #include <linux/types.h>
  21 #include <linux/serial.h>
  22 #include <linux/module.h>
  23
  24 #include <asm/ibm44x.h>
  25 #include <asm/mmu.h>
  26 #include <asm/machdep.h>
  27 #include <asm/time.h>
  28 #include <asm/ppc4xx_pic.h>
  29 #include <asm/param.h>
  30 #include <asm/bootinfo.h>
  31 #include <asm/ppcboot.h>
  32
  33 #include <syslib/gen550.h>
  34
  35 /* Global Variables */
  36 bd_t __res;
  37
  38 phys_addr_t fixup_bigphys_addr(phys_addr_t addr, phys_addr_t size)
  39 {
  40         phys_addr_t page_4gb = 0;
  41
  42         /*
  43          * Trap the least significant 32-bit portions of an
  44          * address in the 440's 36-bit address space.  Fix
  45          * them up with the appropriate ERPN
  46          */
  47         if ((addr >= PPC44x_IO_LO) && (addr <= PPC44x_IO_HI))
  48                 page_4gb = PPC44x_IO_PAGE;
  49         else if ((addr >= PPC44x_PCI0CFG_LO) && (addr <= PPC44x_PCI0CFG_HI))
  50                 page_4gb = PPC44x_PCICFG_PAGE;
  51 #ifdef CONFIG_440SP
  52         else if ((addr >= PPC44x_PCI1CFG_LO) && (addr <= PPC44x_PCI1CFG_HI))
  53                 page_4gb = PPC44x_PCICFG_PAGE;
  54         else if ((addr >= PPC44x_PCI2CFG_LO) && (addr <= PPC44x_PCI2CFG_HI))
  55                 page_4gb = PPC44x_PCICFG_PAGE;
  56 #endif
  57         else if ((addr >= PPC44x_PCIMEM_LO) && (addr <= PPC44x_PCIMEM_HI))
  58                 page_4gb = PPC44x_PCIMEM_PAGE;
  59
  60         return (page_4gb | addr);
  61 };
  62 EXPORT_SYMBOL(fixup_bigphys_addr);
  63
  64 void __init ibm44x_calibrate_decr(unsigned int freq)
  65 {
  66         tb_ticks_per_jiffy = freq / HZ;
  67         tb_to_us = mulhwu_scale_factor(freq, 1000000);
  68
  69         /* Set the time base to zero */
  70         mtspr(SPRN_TBWL, 0);
  71         mtspr(SPRN_TBWU, 0);
  72
  73         /* Clear any pending timer interrupts */
  74         mtspr(SPRN_TSR, TSR_ENW | TSR_WIS | TSR_DIS | TSR_FIS);
  75
  76         /* Enable decrementer interrupt */
  77         mtspr(SPRN_TCR, TCR_DIE);
  78 }
  79
  80 extern void abort(void);
  81
  82 static void ibm44x_restart(char *cmd)
  83 {
  84         local_irq_disable();
  85         abort();
  86 }
  87
  88 static void ibm44x_power_off(void)
  89 {
  90         local_irq_disable();
  91         for(;;);
  92 }
  93
  94 static void ibm44x_halt(void)
  95 {
  96         local_irq_disable();
  97         for(;;);
  98 }
  99
 100 /*
 101  * Read the 44x memory controller to get size of system memory.
 102  */
 103 static unsigned long __init ibm44x_find_end_of_memory(void)
 104 {
 105         u32 i, bank_config;
 106         u32 mem_size = 0;
 107
 108         for (i=0; i<4; i++)
 109         {
 110                 switch (i)
 111                 {
 112                         case 0:
 113                                 mtdcr(DCRN_SDRAM0_CFGADDR, SDRAM0_B0CR);
 114                                 break;
 115                         case 1:
 116                                 mtdcr(DCRN_SDRAM0_CFGADDR, SDRAM0_B1CR);
 117                                 break;
 118                         case 2:
 119                                 mtdcr(DCRN_SDRAM0_CFGADDR, SDRAM0_B2CR);
 120                                 break;
 121                         case 3:
 122                                 mtdcr(DCRN_SDRAM0_CFGADDR, SDRAM0_B3CR);
 123                                 break;
 124                 }
 125
 126                 bank_config = mfdcr(DCRN_SDRAM0_CFGDATA);
 127
 128                 if (!(bank_config & SDRAM_CONFIG_BANK_ENABLE))
 129                         continue;
 130                 switch (SDRAM_CONFIG_BANK_SIZE(bank_config))
 131                 {
 132                         case SDRAM_CONFIG_SIZE_8M:
 133                                 mem_size += PPC44x_MEM_SIZE_8M;
 134                                 break;
 135                         case SDRAM_CONFIG_SIZE_16M:
 136                                 mem_size += PPC44x_MEM_SIZE_16M;
 137                                 break;
 138                         case SDRAM_CONFIG_SIZE_32M:
 139                                 mem_size += PPC44x_MEM_SIZE_32M;
 140                                 break;
 141                         case SDRAM_CONFIG_SIZE_64M:
 142                                 mem_size += PPC44x_MEM_SIZE_64M;
 143                                 break;
 144                         case SDRAM_CONFIG_SIZE_128M:
 145                                 mem_size += PPC44x_MEM_SIZE_128M;
 146                                 break;
 147                         case SDRAM_CONFIG_SIZE_256M:
 148                                 mem_size += PPC44x_MEM_SIZE_256M;
 149                                 break;
 150                         case SDRAM_CONFIG_SIZE_512M:
 151                                 mem_size += PPC44x_MEM_SIZE_512M;
 152                                 break;
 153                 }
 154         }
 155         return mem_size;
 156 }
 157
 158 void __init ibm44x_platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
 159                                  unsigned long r6, unsigned long r7)
 160 {
 161         parse_bootinfo(find_bootinfo());
 162
 163         /*
 164          * If we were passed in a board information, copy it into the
 165          * residual data area.
 166          */
 167         if (r3)
 168                 __res = *(bd_t *)(r3 + KERNELBASE);
 169
 170 #if defined(CONFIG_BLK_DEV_INITRD)
 171         /*
 172          * If the init RAM disk has been configured in, and there's a valid
 173          * starting address for it, set it up.
 174          */
 175         if (r4) {
 176                 initrd_start = r4 + KERNELBASE;
 177                 initrd_end = r5 + KERNELBASE;
 178         }
 179 #endif  /* CONFIG_BLK_DEV_INITRD */
 180
 181         /* Copy the kernel command line arguments to a safe place. */
 182
 183         if (r6) {
 184                 *(char *) (r7 + KERNELBASE) = 0;
 185                 strcpy(cmd_line, (char *) (r6 + KERNELBASE));
 186         }
 187
 188         ppc_md.init_IRQ = ppc4xx_pic_init;
 189         ppc_md.find_end_of_memory = ibm44x_find_end_of_memory;
 190         ppc_md.restart = ibm44x_restart;
 191         ppc_md.power_off = ibm44x_power_off;
 192         ppc_md.halt = ibm44x_halt;
 193
 194 #ifdef CONFIG_SERIAL_TEXT_DEBUG
 195         ppc_md.progress = gen550_progress;
 196 #endif /* CONFIG_SERIAL_TEXT_DEBUG */
 197 #ifdef CONFIG_KGDB
 198         ppc_md.kgdb_map_scc = gen550_kgdb_map_scc;
 199 #endif
 200
 201         /*
 202          * The Abatron BDI JTAG debugger does not tolerate others
 203          * mucking with the debug registers.
 204          */
 205 #if !defined(CONFIG_BDI_SWITCH)
 206         /* Enable internal debug mode */
 207         mtspr(SPRN_DBCR0, (DBCR0_IDM));
 208
 209         /* Clear any residual debug events */
 210         mtspr(SPRN_DBSR, 0xffffffff);
 211 #endif
 212 }
 213
 214 /* Called from machine_check_exception */
 215 void platform_machine_check(struct pt_regs *regs)
 216 {
 217 #ifdef CONFIG_440SP
 218         printk("PLB0: BEAR=0x%08x%08x ACR=  0x%08x BESR= 0x%08x%08x\n",
 219                mfdcr(DCRN_PLB0_BEARH), mfdcr(DCRN_PLB0_BEARL),
 220                mfdcr(DCRN_PLB0_ACR), mfdcr(DCRN_PLB0_BESRH),
 221                mfdcr(DCRN_PLB0_BESRL));
 222         printk("PLB1: BEAR=0x%08x%08x ACR=  0x%08x BESR= 0x%08x%08x\n",
 223                mfdcr(DCRN_PLB1_BEARH), mfdcr(DCRN_PLB1_BEARL),
 224                mfdcr(DCRN_PLB1_ACR), mfdcr(DCRN_PLB1_BESRH),
 225                mfdcr(DCRN_PLB1_BESRL));
 226 #else
 227         printk("PLB0: BEAR=0x%08x%08x ACR=  0x%08x BESR= 0x%08x\n",
 228                 mfdcr(DCRN_PLB0_BEARH), mfdcr(DCRN_PLB0_BEARL),
 229                 mfdcr(DCRN_PLB0_ACR),  mfdcr(DCRN_PLB0_BESR));
 230 #endif
 231         printk("POB0: BEAR=0x%08x%08x BESR0=0x%08x BESR1=0x%08x\n",
 232                 mfdcr(DCRN_POB0_BEARH), mfdcr(DCRN_POB0_BEARL),
 233                 mfdcr(DCRN_POB0_BESR0), mfdcr(DCRN_POB0_BESR1));
 234         printk("OPB0: BEAR=0x%08x%08x BSTAT=0x%08x\n",
 235                 mfdcr(DCRN_OPB0_BEARH), mfdcr(DCRN_OPB0_BEARL),
 236                 mfdcr(DCRN_OPB0_BSTAT));
 237 }