arch/ppc/syslib/ppc85xx_setup.c

   1 /*
   2  * MPC85XX common board code
   3  *
   4  * Maintainer: Kumar Gala <galak@kernel.crashing.org>
   5  *
   6  * Copyright 2004 Freescale Semiconductor Inc.
   7  *
   8  * This program is free software; you can redistribute  it and/or modify it
   9  * under  the terms of  the GNU General  Public License as published by the
  10  * Free Software Foundation;  either version 2 of the  License, or (at your
  11  * option) any later version.
  12  */
  13
  14 #include <linux/config.h>
  15 #include <linux/types.h>
  16 #include <linux/module.h>
  17 #include <linux/init.h>
  18 #include <linux/pci.h>
  19 #include <linux/serial.h>
  20 #include <linux/tty.h>  /* for linux/serial_core.h */
  21 #include <linux/serial_core.h>
  22 #include <linux/serial_8250.h>
  23
  24 #include <asm/time.h>
  25 #include <asm/mpc85xx.h>
  26 #include <asm/immap_85xx.h>
  27 #include <asm/mmu.h>
  28 #include <asm/ppc_sys.h>
  29 #include <asm/kgdb.h>
  30 #include <asm/machdep.h>
  31
  32 #include <syslib/ppc85xx_setup.h>
  33
  34 extern void abort(void);
  35
  36 /* Return the amount of memory */
  37 unsigned long __init
  38 mpc85xx_find_end_of_memory(void)
  39 {
  40         bd_t *binfo;
  41
  42         binfo = (bd_t *) __res;
  43
  44         return binfo->bi_memsize;
  45 }
  46
  47 /* The decrementer counts at the system (internal) clock freq divided by 8 */
  48 void __init
  49 mpc85xx_calibrate_decr(void)
  50 {
  51         bd_t *binfo = (bd_t *) __res;
  52         unsigned int freq, divisor;
  53
  54         /* get the core frequency */
  55         freq = binfo->bi_busfreq;
  56
  57         /* The timebase is updated every 8 bus clocks, HID0[SEL_TBCLK] = 0 */
  58         divisor = 8;
  59         tb_ticks_per_jiffy = freq / divisor / HZ;
  60         tb_to_us = mulhwu_scale_factor(freq / divisor, 1000000);
  61
  62         /* Set the time base to zero */
  63         mtspr(SPRN_TBWL, 0);
  64         mtspr(SPRN_TBWU, 0);
  65
  66         /* Clear any pending timer interrupts */
  67         mtspr(SPRN_TSR, TSR_ENW | TSR_WIS | TSR_DIS | TSR_FIS);
  68
  69         /* Enable decrementer interrupt */
  70         mtspr(SPRN_TCR, TCR_DIE);
  71 }
  72
  73 #ifdef CONFIG_SERIAL_8250
  74 void __init
  75 mpc85xx_early_serial_map(void)
  76 {
  77 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
  78         struct uart_port serial_req;
  79 #endif
  80         struct plat_serial8250_port *pdata;
  81         bd_t *binfo = (bd_t *) __res;
  82         pdata = (struct plat_serial8250_port *) ppc_sys_get_pdata(MPC85xx_DUART);
  83
  84         /* Setup serial port access */
  85         pdata[0].uartclk = binfo->bi_busfreq;
  86         pdata[0].mapbase += binfo->bi_immr_base;
  87         pdata[0].membase = ioremap(pdata[0].mapbase, MPC85xx_UART0_SIZE);
  88
  89 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
  90         memset(&serial_req, 0, sizeof (serial_req));
  91         serial_req.iotype = UPIO_MEM;
  92         serial_req.mapbase = pdata[0].mapbase;
  93         serial_req.membase = pdata[0].membase;
  94         serial_req.regshift = 0;
  95
  96         gen550_init(0, &serial_req);
  97 #endif
  98
  99         pdata[1].uartclk = binfo->bi_busfreq;
 100         pdata[1].mapbase += binfo->bi_immr_base;
 101         pdata[1].membase = ioremap(pdata[1].mapbase, MPC85xx_UART0_SIZE);
 102
 103 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
 104         /* Assume gen550_init() doesn't modify serial_req */
 105         serial_req.mapbase = pdata[1].mapbase;
 106         serial_req.membase = pdata[1].membase;
 107
 108         gen550_init(1, &serial_req);
 109 #endif
 110 }
 111 #endif
 112
 113 void
 114 mpc85xx_restart(char *cmd)
 115 {
 116         local_irq_disable();
 117         abort();
 118 }
 119
 120 void
 121 mpc85xx_power_off(void)
 122 {
 123         local_irq_disable();
 124         for(;;);
 125 }
 126
 127 void
 128 mpc85xx_halt(void)
 129 {
 130         local_irq_disable();
 131         for(;;);
 132 }
 133
 134 #ifdef CONFIG_PCI
 135
 136 #if defined(CONFIG_MPC8555_CDS) || defined(CONFIG_MPC8548_CDS)
 137 extern void mpc85xx_cds_enable_via(struct pci_controller *hose);
 138 extern void mpc85xx_cds_fixup_via(struct pci_controller *hose);
 139 #endif
 140
 141 static void __init
 142 mpc85xx_setup_pci1(struct pci_controller *hose)
 143 {
 144         volatile struct ccsr_pci *pci;
 145         volatile struct ccsr_guts *guts;
 146         unsigned short temps;
 147         bd_t *binfo = (bd_t *) __res;
 148
 149         pci = ioremap(binfo->bi_immr_base + MPC85xx_PCI1_OFFSET,
 150                     MPC85xx_PCI1_SIZE);
 151
 152         guts = ioremap(binfo->bi_immr_base + MPC85xx_GUTS_OFFSET,
 153                     MPC85xx_GUTS_SIZE);
 154
 155         early_read_config_word(hose, 0, 0, PCI_COMMAND, &temps);
 156         temps |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
 157         early_write_config_word(hose, 0, 0, PCI_COMMAND, temps);
 158
 159 #define PORDEVSR_PCI    (0x00800000)    /* PCI Mode */
 160         if (guts->pordevsr & PORDEVSR_PCI) {
 161                 early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
 162         } else {
 163                 /* PCI-X init */
 164                 temps = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
 165                         | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
 166                 early_write_config_word(hose, 0, 0, PCIX_COMMAND, temps);
 167         }
 168
 169         /* Disable all windows (except powar0 since its ignored) */
 170         pci->powar1 = 0;
 171         pci->powar2 = 0;
 172         pci->powar3 = 0;
 173         pci->powar4 = 0;
 174         pci->piwar1 = 0;
 175         pci->piwar2 = 0;
 176         pci->piwar3 = 0;
 177
 178         /* Setup Phys:PCI 1:1 outbound mem window @ MPC85XX_PCI1_LOWER_MEM */
 179         pci->potar1 = (MPC85XX_PCI1_LOWER_MEM >> 12) & 0x000fffff;
 180         pci->potear1 = 0x00000000;
 181         pci->powbar1 = (MPC85XX_PCI1_LOWER_MEM >> 12) & 0x000fffff;
 182         /* Enable, Mem R/W */
 183         pci->powar1 = 0x80044000 |
 184            (__ilog2(MPC85XX_PCI1_UPPER_MEM - MPC85XX_PCI1_LOWER_MEM + 1) - 1);
 185
 186         /* Setup outbound IO windows @ MPC85XX_PCI1_IO_BASE */
 187         pci->potar2 = (MPC85XX_PCI1_LOWER_IO >> 12) & 0x000fffff;
 188         pci->potear2 = 0x00000000;
 189         pci->powbar2 = (MPC85XX_PCI1_IO_BASE >> 12) & 0x000fffff;
 190         /* Enable, IO R/W */
 191         pci->powar2 = 0x80088000 | (__ilog2(MPC85XX_PCI1_IO_SIZE) - 1);
 192
 193         /* Setup 2G inbound Memory Window @ 0 */
 194         pci->pitar1 = 0x00000000;
 195         pci->piwbar1 = 0x00000000;
 196         pci->piwar1 = 0xa0f5501e;       /* Enable, Prefetch, Local
 197                                            Mem, Snoop R/W, 2G */
 198 }
 199
 200
 201 extern int mpc85xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin);
 202 extern int mpc85xx_exclude_device(u_char bus, u_char devfn);
 203
 204 #ifdef CONFIG_85xx_PCI2
 205 static void __init
 206 mpc85xx_setup_pci2(struct pci_controller *hose)
 207 {
 208         volatile struct ccsr_pci *pci;
 209         unsigned short temps;
 210         bd_t *binfo = (bd_t *) __res;
 211
 212         pci = ioremap(binfo->bi_immr_base + MPC85xx_PCI2_OFFSET,
 213                     MPC85xx_PCI2_SIZE);
 214
 215         early_read_config_word(hose, hose->bus_offset, 0, PCI_COMMAND, &temps);
 216         temps |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
 217         early_write_config_word(hose, hose->bus_offset, 0, PCI_COMMAND, temps);
 218         early_write_config_byte(hose, hose->bus_offset, 0, PCI_LATENCY_TIMER, 0x80);
 219
 220         /* Disable all windows (except powar0 since its ignored) */
 221         pci->powar1 = 0;
 222         pci->powar2 = 0;
 223         pci->powar3 = 0;
 224         pci->powar4 = 0;
 225         pci->piwar1 = 0;
 226         pci->piwar2 = 0;
 227         pci->piwar3 = 0;
 228
 229         /* Setup Phys:PCI 1:1 outbound mem window @ MPC85XX_PCI2_LOWER_MEM */
 230         pci->potar1 = (MPC85XX_PCI2_LOWER_MEM >> 12) & 0x000fffff;
 231         pci->potear1 = 0x00000000;
 232         pci->powbar1 = (MPC85XX_PCI2_LOWER_MEM >> 12) & 0x000fffff;
 233         /* Enable, Mem R/W */
 234         pci->powar1 = 0x80044000 |
 235            (__ilog2(MPC85XX_PCI2_UPPER_MEM - MPC85XX_PCI2_LOWER_MEM + 1) - 1);
 236
 237         /* Setup outbound IO windows @ MPC85XX_PCI2_IO_BASE */
 238         pci->potar2 = (MPC85XX_PCI2_LOWER_IO >> 12) & 0x000fffff;
 239         pci->potear2 = 0x00000000;
 240         pci->powbar2 = (MPC85XX_PCI2_IO_BASE >> 12) & 0x000fffff;
 241         /* Enable, IO R/W */
 242         pci->powar2 = 0x80088000 | (__ilog2(MPC85XX_PCI2_IO_SIZE) - 1);
 243
 244         /* Setup 2G inbound Memory Window @ 0 */
 245         pci->pitar1 = 0x00000000;
 246         pci->piwbar1 = 0x00000000;
 247         pci->piwar1 = 0xa0f5501e;       /* Enable, Prefetch, Local
 248                                            Mem, Snoop R/W, 2G */
 249 }
 250 #endif /* CONFIG_85xx_PCI2 */
 251
 252 int mpc85xx_pci1_last_busno = 0;
 253
 254 void __init
 255 mpc85xx_setup_hose(void)
 256 {
 257         struct pci_controller *hose_a;
 258 #ifdef CONFIG_85xx_PCI2
 259         struct pci_controller *hose_b;
 260 #endif
 261         bd_t *binfo = (bd_t *) __res;
 262
 263         hose_a = pcibios_alloc_controller();
 264
 265         if (!hose_a)
 266                 return;
 267
 268         ppc_md.pci_swizzle = common_swizzle;
 269         ppc_md.pci_map_irq = mpc85xx_map_irq;
 270
 271         hose_a->first_busno = 0;
 272         hose_a->bus_offset = 0;
 273         hose_a->last_busno = 0xff;
 274
 275         setup_indirect_pci(hose_a, binfo->bi_immr_base + PCI1_CFG_ADDR_OFFSET,
 276                            binfo->bi_immr_base + PCI1_CFG_DATA_OFFSET);
 277         hose_a->set_cfg_type = 1;
 278
 279         mpc85xx_setup_pci1(hose_a);
 280
 281         hose_a->pci_mem_offset = MPC85XX_PCI1_MEM_OFFSET;
 282         hose_a->mem_space.start = MPC85XX_PCI1_LOWER_MEM;
 283         hose_a->mem_space.end = MPC85XX_PCI1_UPPER_MEM;
 284
 285         hose_a->io_space.start = MPC85XX_PCI1_LOWER_IO;
 286         hose_a->io_space.end = MPC85XX_PCI1_UPPER_IO;
 287         hose_a->io_base_phys = MPC85XX_PCI1_IO_BASE;
 288 #ifdef CONFIG_85xx_PCI2
 289         hose_a->io_base_virt =  ioremap(MPC85XX_PCI1_IO_BASE,
 290                                         MPC85XX_PCI1_IO_SIZE +
 291                                         MPC85XX_PCI2_IO_SIZE);
 292 #else
 293         hose_a->io_base_virt =  ioremap(MPC85XX_PCI1_IO_BASE,
 294                                         MPC85XX_PCI1_IO_SIZE);
 295 #endif
 296         isa_io_base = (unsigned long)hose_a->io_base_virt;
 297
 298         /* setup resources */
 299         pci_init_resource(&hose_a->mem_resources[0],
 300                         MPC85XX_PCI1_LOWER_MEM,
 301                         MPC85XX_PCI1_UPPER_MEM,
 302                         IORESOURCE_MEM, "PCI1 host bridge");
 303
 304         pci_init_resource(&hose_a->io_resource,
 305                         MPC85XX_PCI1_LOWER_IO,
 306                         MPC85XX_PCI1_UPPER_IO,
 307                         IORESOURCE_IO, "PCI1 host bridge");
 308
 309         ppc_md.pci_exclude_device = mpc85xx_exclude_device;
 310
 311 #if defined(CONFIG_MPC8555_CDS) || defined(CONFIG_MPC8548_CDS)
 312         /* Pre pciauto_bus_scan VIA init */
 313         mpc85xx_cds_enable_via(hose_a);
 314 #endif
 315
 316         hose_a->last_busno = pciauto_bus_scan(hose_a, hose_a->first_busno);
 317
 318 #if defined(CONFIG_MPC8555_CDS) || defined(CONFIG_MPC8548_CDS)
 319         /* Post pciauto_bus_scan VIA fixup */
 320         mpc85xx_cds_fixup_via(hose_a);
 321 #endif
 322
 323 #ifdef CONFIG_85xx_PCI2
 324         hose_b = pcibios_alloc_controller();
 325
 326         if (!hose_b)
 327                 return;
 328
 329         hose_b->bus_offset = hose_a->last_busno + 1;
 330         hose_b->first_busno = hose_a->last_busno + 1;
 331         hose_b->last_busno = 0xff;
 332
 333         setup_indirect_pci(hose_b, binfo->bi_immr_base + PCI2_CFG_ADDR_OFFSET,
 334                            binfo->bi_immr_base + PCI2_CFG_DATA_OFFSET);
 335         hose_b->set_cfg_type = 1;
 336
 337         mpc85xx_setup_pci2(hose_b);
 338
 339         hose_b->pci_mem_offset = MPC85XX_PCI2_MEM_OFFSET;
 340         hose_b->mem_space.start = MPC85XX_PCI2_LOWER_MEM;
 341         hose_b->mem_space.end = MPC85XX_PCI2_UPPER_MEM;
 342
 343         hose_b->io_space.start = MPC85XX_PCI2_LOWER_IO;
 344         hose_b->io_space.end = MPC85XX_PCI2_UPPER_IO;
 345         hose_b->io_base_phys = MPC85XX_PCI2_IO_BASE;
 346         hose_b->io_base_virt = hose_a->io_base_virt + MPC85XX_PCI1_IO_SIZE;
 347
 348         /* setup resources */
 349         pci_init_resource(&hose_b->mem_resources[0],
 350                         MPC85XX_PCI2_LOWER_MEM,
 351                         MPC85XX_PCI2_UPPER_MEM,
 352                         IORESOURCE_MEM, "PCI2 host bridge");
 353
 354         pci_init_resource(&hose_b->io_resource,
 355                         MPC85XX_PCI2_LOWER_IO,
 356                         MPC85XX_PCI2_UPPER_IO,
 357                         IORESOURCE_IO, "PCI2 host bridge");
 358
 359         hose_b->last_busno = pciauto_bus_scan(hose_b, hose_b->first_busno);
 360
 361         /* let board code know what the last bus number was on PCI1 */
 362         mpc85xx_pci1_last_busno = hose_a->last_busno;
 363 #endif
 364         return;
 365 }
 366 #endif /* CONFIG_PCI */
 367
 368