arch/ppc64/kernel/cputable.c

   1 /*
   2  *  arch/ppc64/kernel/cputable.c
   3  *
   4  *  Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org)
   5  *
   6  *  Modifications for ppc64:
   7  *      Copyright (C) 2003 Dave Engebretsen <engebret@us.ibm.com>
   8  *
   9  *  This program is free software; you can redistribute it and/or
  10  *  modify it under the terms of the GNU General Public License
  11  *  as published by the Free Software Foundation; either version
  12  *  2 of the License, or (at your option) any later version.
  13  */
  14
  15 #include <linux/config.h>
  16 #include <linux/string.h>
  17 #include <linux/sched.h>
  18 #include <linux/threads.h>
  19 #include <linux/init.h>
  20 #include <linux/module.h>
  21
  22 #include <asm/cputable.h>
  23
  24 struct cpu_spec* cur_cpu_spec = NULL;
  25 EXPORT_SYMBOL(cur_cpu_spec);
  26
  27 /* NOTE:
  28  * Unlike ppc32, ppc64 will only call this once for the boot CPU, it's
  29  * the responsibility of the appropriate CPU save/restore functions to
  30  * eventually copy these settings over. Those save/restore aren't yet
  31  * part of the cputable though. That has to be fixed for both ppc32
  32  * and ppc64
  33  */
  34 extern void __setup_cpu_power3(unsigned long offset, struct cpu_spec* spec);
  35 extern void __setup_cpu_power4(unsigned long offset, struct cpu_spec* spec);
  36 extern void __setup_cpu_ppc970(unsigned long offset, struct cpu_spec* spec);
  37 extern void __setup_cpu_be(unsigned long offset, struct cpu_spec* spec);
  38
  39
  40 /* We only set the altivec features if the kernel was compiled with altivec
  41  * support
  42  */
  43 #ifdef CONFIG_ALTIVEC
  44 #define CPU_FTR_ALTIVEC_COMP    CPU_FTR_ALTIVEC
  45 #define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
  46 #else
  47 #define CPU_FTR_ALTIVEC_COMP    0
  48 #define PPC_FEATURE_HAS_ALTIVEC_COMP    0
  49 #endif
  50
  51 struct cpu_spec cpu_specs[] = {
  52         {       /* Power3 */
  53                 .pvr_mask               = 0xffff0000,
  54                 .pvr_value              = 0x00400000,
  55                 .cpu_name               = "POWER3 (630)",
  56                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
  57                         CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
  58                         CPU_FTR_PMC8,
  59                 .cpu_user_features = COMMON_USER_PPC64,
  60                 .icache_bsize           = 128,
  61                 .dcache_bsize           = 128,
  62                 .cpu_setup              = __setup_cpu_power3,
  63                 .firmware_features      = COMMON_PPC64_FW,
  64         },
  65         {       /* Power3+ */
  66                 .pvr_mask               = 0xffff0000,
  67                 .pvr_value              = 0x00410000,
  68                 .cpu_name               = "POWER3 (630+)",
  69                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
  70                         CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
  71                         CPU_FTR_PMC8,
  72                 .cpu_user_features      = COMMON_USER_PPC64,
  73                 .icache_bsize           = 128,
  74                 .dcache_bsize           = 128,
  75                 .cpu_setup              = __setup_cpu_power3,
  76                 .firmware_features      = COMMON_PPC64_FW,
  77         },
  78         {       /* Northstar */
  79                 .pvr_mask               = 0xffff0000,
  80                 .pvr_value              = 0x00330000,
  81                 .cpu_name               = "RS64-II (northstar)",
  82                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
  83                         CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
  84                         CPU_FTR_PMC8 | CPU_FTR_MMCRA | CPU_FTR_CTRL,
  85                 .cpu_user_features      = COMMON_USER_PPC64,
  86                 .icache_bsize           = 128,
  87                 .dcache_bsize           = 128,
  88                 .cpu_setup              = __setup_cpu_power3,
  89                 .firmware_features      = COMMON_PPC64_FW,
  90         },
  91         {       /* Pulsar */
  92                 .pvr_mask               = 0xffff0000,
  93                 .pvr_value              = 0x00340000,
  94                 .cpu_name               = "RS64-III (pulsar)",
  95                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
  96                         CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
  97                         CPU_FTR_PMC8 | CPU_FTR_MMCRA | CPU_FTR_CTRL,
  98                 .cpu_user_features      = COMMON_USER_PPC64,
  99                 .icache_bsize           = 128,
 100                 .dcache_bsize           = 128,
 101                 .cpu_setup              = __setup_cpu_power3,
 102                 .firmware_features      = COMMON_PPC64_FW,
 103         },
 104         {       /* I-star */
 105                 .pvr_mask               = 0xffff0000,
 106                 .pvr_value              = 0x00360000,
 107                 .cpu_name               = "RS64-III (icestar)",
 108                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
 109                         CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
 110                         CPU_FTR_PMC8 | CPU_FTR_MMCRA | CPU_FTR_CTRL,
 111                 .cpu_user_features      = COMMON_USER_PPC64,
 112                 .icache_bsize           = 128,
 113                 .dcache_bsize           = 128,
 114                 .cpu_setup              = __setup_cpu_power3,
 115                 .firmware_features      = COMMON_PPC64_FW,
 116         },
 117         {       /* S-star */
 118                 .pvr_mask               = 0xffff0000,
 119                 .pvr_value              = 0x00370000,
 120                 .cpu_name               = "RS64-IV (sstar)",
 121                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
 122                         CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
 123                         CPU_FTR_PMC8 | CPU_FTR_MMCRA | CPU_FTR_CTRL,
 124                 .cpu_user_features      = COMMON_USER_PPC64,
 125                 .icache_bsize           = 128,
 126                 .dcache_bsize           = 128,
 127                 .cpu_setup              = __setup_cpu_power3,
 128                 .firmware_features      = COMMON_PPC64_FW,
 129         },
 130         {       /* Power4 */
 131                 .pvr_mask               = 0xffff0000,
 132                 .pvr_value              = 0x00350000,
 133                 .cpu_name               = "POWER4 (gp)",
 134                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
 135                         CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
 136                         CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
 137                 .cpu_user_features      = COMMON_USER_PPC64,
 138                 .icache_bsize           = 128,
 139                 .dcache_bsize           = 128,
 140                 .cpu_setup              = __setup_cpu_power4,
 141                 .firmware_features      = COMMON_PPC64_FW,
 142         },
 143         {       /* Power4+ */
 144                 .pvr_mask               = 0xffff0000,
 145                 .pvr_value              = 0x00380000,
 146                 .cpu_name               = "POWER4+ (gq)",
 147                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
 148                         CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
 149                         CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
 150                 .cpu_user_features      = COMMON_USER_PPC64,
 151                 .icache_bsize           = 128,
 152                 .dcache_bsize           = 128,
 153                 .cpu_setup              = __setup_cpu_power4,
 154                 .firmware_features      = COMMON_PPC64_FW,
 155         },
 156         {       /* PPC970 */
 157                 .pvr_mask               = 0xffff0000,
 158                 .pvr_value              = 0x00390000,
 159                 .cpu_name               = "PPC970",
 160                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
 161                         CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
 162                         CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
 163                         CPU_FTR_CAN_NAP | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
 164                 .cpu_user_features      = COMMON_USER_PPC64 |
 165                         PPC_FEATURE_HAS_ALTIVEC_COMP,
 166                 .icache_bsize           = 128,
 167                 .dcache_bsize           = 128,
 168                 .cpu_setup              = __setup_cpu_ppc970,
 169                 .firmware_features      = COMMON_PPC64_FW,
 170         },
 171         {       /* PPC970FX */
 172                 .pvr_mask               = 0xffff0000,
 173                 .pvr_value              = 0x003c0000,
 174                 .cpu_name               = "PPC970FX",
 175                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
 176                         CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
 177                         CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
 178                         CPU_FTR_CAN_NAP | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
 179                 .cpu_user_features      = COMMON_USER_PPC64 |
 180                         PPC_FEATURE_HAS_ALTIVEC_COMP,
 181                 .icache_bsize           = 128,
 182                 .dcache_bsize           = 128,
 183                 .cpu_setup              = __setup_cpu_ppc970,
 184                 .firmware_features      = COMMON_PPC64_FW,
 185         },
 186         {       /* PPC970MP */
 187                 .pvr_mask               = 0xffff0000,
 188                 .pvr_value              = 0x00440000,
 189                 .cpu_name               = "PPC970MP",
 190                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
 191                         CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
 192                         CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
 193                         CPU_FTR_CAN_NAP | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
 194                 .cpu_user_features      = COMMON_USER_PPC64 |
 195                         PPC_FEATURE_HAS_ALTIVEC_COMP,
 196                 .icache_bsize           = 128,
 197                 .dcache_bsize           = 128,
 198                 .cpu_setup              = __setup_cpu_ppc970,
 199                 .firmware_features      = COMMON_PPC64_FW,
 200         },
 201         {       /* Power5 */
 202                 .pvr_mask               = 0xffff0000,
 203                 .pvr_value              = 0x003a0000,
 204                 .cpu_name               = "POWER5 (gr)",
 205                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
 206                         CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
 207                         CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA | CPU_FTR_SMT |
 208                         CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE |
 209                         CPU_FTR_MMCRA_SIHV,
 210                 .cpu_user_features      = COMMON_USER_PPC64,
 211                 .icache_bsize           = 128,
 212                 .dcache_bsize           = 128,
 213                 .cpu_setup              = __setup_cpu_power4,
 214                 .firmware_features      = COMMON_PPC64_FW,
 215         },
 216         {       /* Power5 */
 217                 .pvr_mask               = 0xffff0000,
 218                 .pvr_value              = 0x003b0000,
 219                 .cpu_name               = "POWER5 (gs)",
 220                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
 221                         CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
 222                         CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA | CPU_FTR_SMT |
 223                         CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE |
 224                         CPU_FTR_MMCRA_SIHV,
 225                 .cpu_user_features      = COMMON_USER_PPC64,
 226                 .icache_bsize           = 128,
 227                 .dcache_bsize           = 128,
 228                 .cpu_setup              = __setup_cpu_power4,
 229                 .firmware_features      = COMMON_PPC64_FW,
 230         },
 231         {       /* BE DD1.x */
 232                 .pvr_mask               = 0xffff0000,
 233                 .pvr_value              = 0x00700000,
 234                 .cpu_name               = "Broadband Engine",
 235                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
 236                         CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
 237                         CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
 238                         CPU_FTR_SMT,
 239                 .cpu_user_features      = COMMON_USER_PPC64 |
 240                         PPC_FEATURE_HAS_ALTIVEC_COMP,
 241                 .icache_bsize           = 128,
 242                 .dcache_bsize           = 128,
 243                 .cpu_setup              = __setup_cpu_be,
 244                 .firmware_features      = COMMON_PPC64_FW,
 245         },
 246         {       /* default match */
 247                 .pvr_mask               = 0x00000000,
 248                 .pvr_value              = 0x00000000,
 249                 .cpu_name               = "POWER4 (compatible)",
 250                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
 251                         CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
 252                         CPU_FTR_PPCAS_ARCH_V2,
 253                 .cpu_user_features      = COMMON_USER_PPC64,
 254                 .icache_bsize           = 128,
 255                 .dcache_bsize           = 128,
 256                 .cpu_setup              = __setup_cpu_power4,
 257                 .firmware_features      = COMMON_PPC64_FW,
 258         }
 259 };
 260
 261 firmware_feature_t firmware_features_table[FIRMWARE_MAX_FEATURES] = {
 262         {FW_FEATURE_PFT,                "hcall-pft"},
 263         {FW_FEATURE_TCE,                "hcall-tce"},
 264         {FW_FEATURE_SPRG0,              "hcall-sprg0"},
 265         {FW_FEATURE_DABR,               "hcall-dabr"},
 266         {FW_FEATURE_COPY,               "hcall-copy"},
 267         {FW_FEATURE_ASR,                "hcall-asr"},
 268         {FW_FEATURE_DEBUG,              "hcall-debug"},
 269         {FW_FEATURE_PERF,               "hcall-perf"},
 270         {FW_FEATURE_DUMP,               "hcall-dump"},
 271         {FW_FEATURE_INTERRUPT,          "hcall-interrupt"},
 272         {FW_FEATURE_MIGRATE,            "hcall-migrate"},
 273         {FW_FEATURE_PERFMON,            "hcall-perfmon"},
 274         {FW_FEATURE_CRQ,                "hcall-crq"},
 275         {FW_FEATURE_VIO,                "hcall-vio"},
 276         {FW_FEATURE_RDMA,               "hcall-rdma"},
 277         {FW_FEATURE_LLAN,               "hcall-lLAN"},
 278         {FW_FEATURE_BULK,               "hcall-bulk"},
 279         {FW_FEATURE_XDABR,              "hcall-xdabr"},
 280         {FW_FEATURE_MULTITCE,           "hcall-multi-tce"},
 281         {FW_FEATURE_SPLPAR,             "hcall-splpar"},
 282 };