2 * Port for PPC64 David Engebretsen, IBM Corp.
3 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
5 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
6 * Rework, based on alpha PCI code.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
16 #include <linux/config.h>
17 #include <linux/kernel.h>
18 #include <linux/pci.h>
19 #include <linux/string.h>
20 #include <linux/init.h>
21 #include <linux/bootmem.h>
23 #include <linux/list.h>
24 #include <linux/syscalls.h>
26 #include <asm/processor.h>
29 #include <asm/pci-bridge.h>
30 #include <asm/byteorder.h>
32 #include <asm/machdep.h>
38 #define DBG(fmt...) udbg_printf(fmt)
43 unsigned long pci_probe_only
= 1;
44 unsigned long pci_assign_all_buses
= 0;
47 * legal IO pages under MAX_ISA_PORT. This is to ensure we don't touch
48 * devices we don't have access to.
50 unsigned long io_page_mask
;
52 EXPORT_SYMBOL(io_page_mask
);
54 #ifdef CONFIG_PPC_MULTIPLATFORM
55 static void fixup_resource(struct resource
*res
, struct pci_dev
*dev
);
56 static void do_bus_setup(struct pci_bus
*bus
);
59 unsigned int pcibios_assign_all_busses(void)
61 return pci_assign_all_buses
;
64 /* pci_io_base -- the base address from which io bars are offsets.
65 * This is the lowest I/O base address (so bar values are always positive),
66 * and it *must* be the start of ISA space if an ISA bus exists because
67 * ISA drivers use hard coded offsets. If no ISA bus exists a dummy
68 * page is mapped and isa_io_limit prevents access to it.
70 unsigned long isa_io_base
; /* NULL if no ISA bus */
71 EXPORT_SYMBOL(isa_io_base
);
72 unsigned long pci_io_base
;
73 EXPORT_SYMBOL(pci_io_base
);
75 void iSeries_pcibios_init(void);
79 struct dma_mapping_ops pci_dma_ops
;
80 EXPORT_SYMBOL(pci_dma_ops
);
82 int global_phb_number
; /* Global phb counter */
84 /* Cached ISA bridge dev. */
85 struct pci_dev
*ppc64_isabridge_dev
= NULL
;
87 static void fixup_broken_pcnet32(struct pci_dev
* dev
)
89 if ((dev
->class>>8 == PCI_CLASS_NETWORK_ETHERNET
)) {
90 dev
->vendor
= PCI_VENDOR_ID_AMD
;
91 pci_write_config_word(dev
, PCI_VENDOR_ID
, PCI_VENDOR_ID_AMD
);
94 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TRIDENT
, PCI_ANY_ID
, fixup_broken_pcnet32
);
96 void pcibios_resource_to_bus(struct pci_dev
*dev
, struct pci_bus_region
*region
,
99 unsigned long offset
= 0;
100 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
105 if (res
->flags
& IORESOURCE_IO
)
106 offset
= (unsigned long)hose
->io_base_virt
- pci_io_base
;
108 if (res
->flags
& IORESOURCE_MEM
)
109 offset
= hose
->pci_mem_offset
;
111 region
->start
= res
->start
- offset
;
112 region
->end
= res
->end
- offset
;
115 void pcibios_bus_to_resource(struct pci_dev
*dev
, struct resource
*res
,
116 struct pci_bus_region
*region
)
118 unsigned long offset
= 0;
119 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
124 if (res
->flags
& IORESOURCE_IO
)
125 offset
= (unsigned long)hose
->io_base_virt
- pci_io_base
;
127 if (res
->flags
& IORESOURCE_MEM
)
128 offset
= hose
->pci_mem_offset
;
130 res
->start
= region
->start
+ offset
;
131 res
->end
= region
->end
+ offset
;
134 #ifdef CONFIG_HOTPLUG
135 EXPORT_SYMBOL(pcibios_resource_to_bus
);
136 EXPORT_SYMBOL(pcibios_bus_to_resource
);
140 * We need to avoid collisions with `mirrored' VGA ports
141 * and other strange ISA hardware, so we always want the
142 * addresses to be allocated in the 0x000-0x0ff region
145 * Why? Because some silly external IO cards only decode
146 * the low 10 bits of the IO address. The 0x00-0xff region
147 * is reserved for motherboard devices that decode all 16
148 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
149 * but we want to try to avoid allocating at 0x2900-0x2bff
150 * which might have be mirrored at 0x0100-0x03ff..
152 void pcibios_align_resource(void *data
, struct resource
*res
,
153 unsigned long size
, unsigned long align
)
155 struct pci_dev
*dev
= data
;
156 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
157 unsigned long start
= res
->start
;
158 unsigned long alignto
;
160 if (res
->flags
& IORESOURCE_IO
) {
161 unsigned long offset
= (unsigned long)hose
->io_base_virt
-
163 /* Make sure we start at our min on all hoses */
164 if (start
- offset
< PCIBIOS_MIN_IO
)
165 start
= PCIBIOS_MIN_IO
+ offset
;
168 * Put everything into 0x00-0xff region modulo 0x400
171 start
= (start
+ 0x3ff) & ~0x3ff;
173 } else if (res
->flags
& IORESOURCE_MEM
) {
174 /* Make sure we start at our min on all hoses */
175 if (start
- hose
->pci_mem_offset
< PCIBIOS_MIN_MEM
)
176 start
= PCIBIOS_MIN_MEM
+ hose
->pci_mem_offset
;
178 /* Align to multiple of size of minimum base. */
179 alignto
= max(0x1000UL
, align
);
180 start
= ALIGN(start
, alignto
);
186 static DEFINE_SPINLOCK(hose_spinlock
);
189 * pci_controller(phb) initialized common variables.
191 void __devinit
pci_setup_pci_controller(struct pci_controller
*hose
)
193 memset(hose
, 0, sizeof(struct pci_controller
));
195 spin_lock(&hose_spinlock
);
196 hose
->global_number
= global_phb_number
++;
197 list_add_tail(&hose
->list_node
, &hose_list
);
198 spin_unlock(&hose_spinlock
);
201 static void __init
pcibios_claim_one_bus(struct pci_bus
*b
)
204 struct pci_bus
*child_bus
;
206 list_for_each_entry(dev
, &b
->devices
, bus_list
) {
209 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++) {
210 struct resource
*r
= &dev
->resource
[i
];
212 if (r
->parent
|| !r
->start
|| !r
->flags
)
214 pci_claim_resource(dev
, i
);
218 list_for_each_entry(child_bus
, &b
->children
, node
)
219 pcibios_claim_one_bus(child_bus
);
222 #ifndef CONFIG_PPC_ISERIES
223 static void __init
pcibios_claim_of_setup(void)
227 list_for_each_entry(b
, &pci_root_buses
, node
)
228 pcibios_claim_one_bus(b
);
232 #ifdef CONFIG_PPC_MULTIPLATFORM
233 static u32
get_int_prop(struct device_node
*np
, const char *name
, u32 def
)
238 prop
= (u32
*) get_property(np
, name
, &len
);
239 if (prop
&& len
>= 4)
244 static unsigned int pci_parse_of_flags(u32 addr0
)
246 unsigned int flags
= 0;
248 if (addr0
& 0x02000000) {
249 flags
= IORESOURCE_MEM
| PCI_BASE_ADDRESS_SPACE_MEMORY
;
250 flags
|= (addr0
>> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64
;
251 flags
|= (addr0
>> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M
;
252 if (addr0
& 0x40000000)
253 flags
|= IORESOURCE_PREFETCH
254 | PCI_BASE_ADDRESS_MEM_PREFETCH
;
255 } else if (addr0
& 0x01000000)
256 flags
= IORESOURCE_IO
| PCI_BASE_ADDRESS_SPACE_IO
;
260 #define GET_64BIT(prop, i) ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1])
262 static void pci_parse_of_addrs(struct device_node
*node
, struct pci_dev
*dev
)
266 struct resource
*res
;
270 addrs
= (u32
*) get_property(node
, "assigned-addresses", &proplen
);
273 for (; proplen
>= 20; proplen
-= 20, addrs
+= 5) {
274 flags
= pci_parse_of_flags(addrs
[0]);
277 base
= GET_64BIT(addrs
, 1);
278 size
= GET_64BIT(addrs
, 3);
282 if (PCI_BASE_ADDRESS_0
<= i
&& i
<= PCI_BASE_ADDRESS_5
) {
283 res
= &dev
->resource
[(i
- PCI_BASE_ADDRESS_0
) >> 2];
284 } else if (i
== dev
->rom_base_reg
) {
285 res
= &dev
->resource
[PCI_ROM_RESOURCE
];
286 flags
|= IORESOURCE_READONLY
| IORESOURCE_CACHEABLE
;
288 printk(KERN_ERR
"PCI: bad cfg reg num 0x%x\n", i
);
292 res
->end
= base
+ size
- 1;
294 res
->name
= pci_name(dev
);
295 fixup_resource(res
, dev
);
299 static struct pci_dev
*of_create_pci_dev(struct device_node
*node
,
300 struct pci_bus
*bus
, int devfn
)
305 dev
= kmalloc(sizeof(struct pci_dev
), GFP_KERNEL
);
308 type
= get_property(node
, "device_type", NULL
);
312 memset(dev
, 0, sizeof(struct pci_dev
));
315 dev
->dev
.parent
= bus
->bridge
;
316 dev
->dev
.bus
= &pci_bus_type
;
318 dev
->multifunction
= 0; /* maybe a lie? */
320 dev
->vendor
= get_int_prop(node
, "vendor-id", 0xffff);
321 dev
->device
= get_int_prop(node
, "device-id", 0xffff);
322 dev
->subsystem_vendor
= get_int_prop(node
, "subsystem-vendor-id", 0);
323 dev
->subsystem_device
= get_int_prop(node
, "subsystem-id", 0);
325 dev
->cfg_size
= 256; /*pci_cfg_space_size(dev);*/
327 sprintf(pci_name(dev
), "%04x:%02x:%02x.%d", pci_domain_nr(bus
),
328 dev
->bus
->number
, PCI_SLOT(devfn
), PCI_FUNC(devfn
));
329 dev
->class = get_int_prop(node
, "class-code", 0);
331 dev
->current_state
= 4; /* unknown power state */
333 if (!strcmp(type
, "pci")) {
334 /* a PCI-PCI bridge */
335 dev
->hdr_type
= PCI_HEADER_TYPE_BRIDGE
;
336 dev
->rom_base_reg
= PCI_ROM_ADDRESS1
;
337 } else if (!strcmp(type
, "cardbus")) {
338 dev
->hdr_type
= PCI_HEADER_TYPE_CARDBUS
;
340 dev
->hdr_type
= PCI_HEADER_TYPE_NORMAL
;
341 dev
->rom_base_reg
= PCI_ROM_ADDRESS
;
343 if (node
->n_intrs
> 0) {
344 dev
->irq
= node
->intrs
[0].line
;
345 pci_write_config_byte(dev
, PCI_INTERRUPT_LINE
,
350 pci_parse_of_addrs(node
, dev
);
352 pci_device_add(dev
, bus
);
354 /* XXX pci_scan_msi_device(dev); */
359 static void of_scan_pci_bridge(struct device_node
*node
, struct pci_dev
*dev
);
361 static void __devinit
of_scan_bus(struct device_node
*node
,
364 struct device_node
*child
= NULL
;
369 while ((child
= of_get_next_child(node
, child
)) != NULL
) {
370 reg
= (u32
*) get_property(child
, "reg", ®len
);
371 if (reg
== NULL
|| reglen
< 20)
373 devfn
= (reg
[0] >> 8) & 0xff;
374 /* create a new pci_dev for this device */
375 dev
= of_create_pci_dev(child
, bus
, devfn
);
378 if (dev
->hdr_type
== PCI_HEADER_TYPE_BRIDGE
||
379 dev
->hdr_type
== PCI_HEADER_TYPE_CARDBUS
)
380 of_scan_pci_bridge(child
, dev
);
386 static void __devinit
of_scan_pci_bridge(struct device_node
*node
,
390 u32
*busrange
, *ranges
;
392 struct resource
*res
;
396 /* parse bus-range property */
397 busrange
= (u32
*) get_property(node
, "bus-range", &len
);
398 if (busrange
== NULL
|| len
!= 8) {
399 printk(KERN_ERR
"Can't get bus-range for PCI-PCI bridge %s\n",
403 ranges
= (u32
*) get_property(node
, "ranges", &len
);
404 if (ranges
== NULL
) {
405 printk(KERN_ERR
"Can't get ranges for PCI-PCI bridge %s\n",
410 bus
= pci_add_new_bus(dev
->bus
, dev
, busrange
[0]);
412 printk(KERN_ERR
"Failed to create pci bus for %s\n",
417 bus
->primary
= dev
->bus
->number
;
418 bus
->subordinate
= busrange
[1];
422 /* parse ranges property */
423 /* PCI #address-cells == 3 and #size-cells == 2 always */
424 res
= &dev
->resource
[PCI_BRIDGE_RESOURCES
];
425 for (i
= 0; i
< PCI_NUM_RESOURCES
- PCI_BRIDGE_RESOURCES
; ++i
) {
427 bus
->resource
[i
] = res
;
431 for (; len
>= 32; len
-= 32, ranges
+= 8) {
432 flags
= pci_parse_of_flags(ranges
[0]);
433 size
= GET_64BIT(ranges
, 6);
434 if (flags
== 0 || size
== 0)
436 if (flags
& IORESOURCE_IO
) {
437 res
= bus
->resource
[0];
439 printk(KERN_ERR
"PCI: ignoring extra I/O range"
440 " for bridge %s\n", node
->full_name
);
444 if (i
>= PCI_NUM_RESOURCES
- PCI_BRIDGE_RESOURCES
) {
445 printk(KERN_ERR
"PCI: too many memory ranges"
446 " for bridge %s\n", node
->full_name
);
449 res
= bus
->resource
[i
];
452 res
->start
= GET_64BIT(ranges
, 1);
453 res
->end
= res
->start
+ size
- 1;
455 fixup_resource(res
, dev
);
457 sprintf(bus
->name
, "PCI Bus %04x:%02x", pci_domain_nr(bus
),
460 mode
= PCI_PROBE_NORMAL
;
461 if (ppc_md
.pci_probe_mode
)
462 mode
= ppc_md
.pci_probe_mode(bus
);
463 if (mode
== PCI_PROBE_DEVTREE
)
464 of_scan_bus(node
, bus
);
465 else if (mode
== PCI_PROBE_NORMAL
)
466 pci_scan_child_bus(bus
);
468 #endif /* CONFIG_PPC_MULTIPLATFORM */
470 static void __devinit
scan_phb(struct pci_controller
*hose
)
473 struct device_node
*node
= hose
->arch_data
;
475 struct resource
*res
;
477 bus
= pci_create_bus(NULL
, hose
->first_busno
, hose
->ops
, node
);
479 printk(KERN_ERR
"Failed to create bus for PCI domain %04x\n",
480 hose
->global_number
);
483 bus
->secondary
= hose
->first_busno
;
486 bus
->resource
[0] = res
= &hose
->io_resource
;
487 if (res
->flags
&& request_resource(&ioport_resource
, res
))
488 printk(KERN_ERR
"Failed to request PCI IO region "
489 "on PCI domain %04x\n", hose
->global_number
);
491 for (i
= 0; i
< 3; ++i
) {
492 res
= &hose
->mem_resources
[i
];
493 bus
->resource
[i
+1] = res
;
494 if (res
->flags
&& request_resource(&iomem_resource
, res
))
495 printk(KERN_ERR
"Failed to request PCI memory region "
496 "on PCI domain %04x\n", hose
->global_number
);
499 mode
= PCI_PROBE_NORMAL
;
500 #ifdef CONFIG_PPC_MULTIPLATFORM
501 if (ppc_md
.pci_probe_mode
)
502 mode
= ppc_md
.pci_probe_mode(bus
);
503 if (mode
== PCI_PROBE_DEVTREE
) {
504 bus
->subordinate
= hose
->last_busno
;
505 of_scan_bus(node
, bus
);
507 #endif /* CONFIG_PPC_MULTIPLATFORM */
508 if (mode
== PCI_PROBE_NORMAL
)
509 hose
->last_busno
= bus
->subordinate
= pci_scan_child_bus(bus
);
510 pci_bus_add_devices(bus
);
513 static int __init
pcibios_init(void)
515 struct pci_controller
*hose
, *tmp
;
517 /* For now, override phys_mem_access_prot. If we need it,
518 * later, we may move that initialization to each ppc_md
520 ppc_md
.phys_mem_access_prot
= pci_phys_mem_access_prot
;
522 #ifdef CONFIG_PPC_ISERIES
523 iSeries_pcibios_init();
526 printk("PCI: Probing PCI hardware\n");
528 /* Scan all of the recorded PCI controllers. */
529 list_for_each_entry_safe(hose
, tmp
, &hose_list
, list_node
)
532 #ifndef CONFIG_PPC_ISERIES
534 pcibios_claim_of_setup();
536 /* FIXME: `else' will be removed when
537 pci_assign_unassigned_resources() is able to work
538 correctly with [partially] allocated PCI tree. */
539 pci_assign_unassigned_resources();
540 #endif /* !CONFIG_PPC_ISERIES */
542 /* Call machine dependent final fixup */
543 if (ppc_md
.pcibios_fixup
)
544 ppc_md
.pcibios_fixup();
546 /* Cache the location of the ISA bridge (if we have one) */
547 ppc64_isabridge_dev
= pci_get_class(PCI_CLASS_BRIDGE_ISA
<< 8, NULL
);
548 if (ppc64_isabridge_dev
!= NULL
)
549 printk("ISA bridge at %s\n", pci_name(ppc64_isabridge_dev
));
551 printk("PCI: Probing PCI hardware done\n");
556 subsys_initcall(pcibios_init
);
558 char __init
*pcibios_setup(char *str
)
563 int pcibios_enable_device(struct pci_dev
*dev
, int mask
)
568 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
571 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++) {
572 struct resource
*res
= &dev
->resource
[i
];
574 /* Only set up the requested stuff */
575 if (!(mask
& (1<<i
)))
578 if (res
->flags
& IORESOURCE_IO
)
579 cmd
|= PCI_COMMAND_IO
;
580 if (res
->flags
& IORESOURCE_MEM
)
581 cmd
|= PCI_COMMAND_MEMORY
;
585 printk(KERN_DEBUG
"PCI: Enabling device: (%s), cmd %x\n",
587 /* Enable the appropriate bits in the PCI command register. */
588 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
594 * Return the domain number for this bus.
596 int pci_domain_nr(struct pci_bus
*bus
)
598 #ifdef CONFIG_PPC_ISERIES
601 struct pci_controller
*hose
= pci_bus_to_host(bus
);
603 return hose
->global_number
;
607 EXPORT_SYMBOL(pci_domain_nr
);
609 /* Decide whether to display the domain number in /proc */
610 int pci_proc_domain(struct pci_bus
*bus
)
612 #ifdef CONFIG_PPC_ISERIES
615 struct pci_controller
*hose
= pci_bus_to_host(bus
);
621 * Platform support for /proc/bus/pci/X/Y mmap()s,
622 * modelled on the sparc64 implementation by Dave Miller.
627 * Adjust vm_pgoff of VMA such that it is the physical page offset
628 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
630 * Basically, the user finds the base address for his device which he wishes
631 * to mmap. They read the 32-bit value from the config space base register,
632 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
633 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
635 * Returns negative error code on failure, zero on success.
637 static struct resource
*__pci_mmap_make_offset(struct pci_dev
*dev
,
638 unsigned long *offset
,
639 enum pci_mmap_state mmap_state
)
641 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
642 unsigned long io_offset
= 0;
646 return NULL
; /* should never happen */
648 /* If memory, add on the PCI bridge address offset */
649 if (mmap_state
== pci_mmap_mem
) {
650 *offset
+= hose
->pci_mem_offset
;
651 res_bit
= IORESOURCE_MEM
;
653 io_offset
= (unsigned long)hose
->io_base_virt
- pci_io_base
;
654 *offset
+= io_offset
;
655 res_bit
= IORESOURCE_IO
;
659 * Check that the offset requested corresponds to one of the
660 * resources of the device.
662 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++) {
663 struct resource
*rp
= &dev
->resource
[i
];
664 int flags
= rp
->flags
;
666 /* treat ROM as memory (should be already) */
667 if (i
== PCI_ROM_RESOURCE
)
668 flags
|= IORESOURCE_MEM
;
670 /* Active and same type? */
671 if ((flags
& res_bit
) == 0)
674 /* In the range of this resource? */
675 if (*offset
< (rp
->start
& PAGE_MASK
) || *offset
> rp
->end
)
678 /* found it! construct the final physical address */
679 if (mmap_state
== pci_mmap_io
)
680 *offset
+= hose
->io_base_phys
- io_offset
;
688 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
691 static pgprot_t
__pci_mmap_set_pgprot(struct pci_dev
*dev
, struct resource
*rp
,
693 enum pci_mmap_state mmap_state
,
696 unsigned long prot
= pgprot_val(protection
);
698 /* Write combine is always 0 on non-memory space mappings. On
699 * memory space, if the user didn't pass 1, we check for a
700 * "prefetchable" resource. This is a bit hackish, but we use
701 * this to workaround the inability of /sysfs to provide a write
704 if (mmap_state
!= pci_mmap_mem
)
706 else if (write_combine
== 0) {
707 if (rp
->flags
& IORESOURCE_PREFETCH
)
711 /* XXX would be nice to have a way to ask for write-through */
712 prot
|= _PAGE_NO_CACHE
;
714 prot
&= ~_PAGE_GUARDED
;
716 prot
|= _PAGE_GUARDED
;
718 printk("PCI map for %s:%lx, prot: %lx\n", pci_name(dev
), rp
->start
,
721 return __pgprot(prot
);
725 * This one is used by /dev/mem and fbdev who have no clue about the
726 * PCI device, it tries to find the PCI device first and calls the
729 pgprot_t
pci_phys_mem_access_prot(struct file
*file
,
730 unsigned long offset
,
734 struct pci_dev
*pdev
= NULL
;
735 struct resource
*found
= NULL
;
736 unsigned long prot
= pgprot_val(protection
);
739 if (page_is_ram(offset
>> PAGE_SHIFT
))
740 return __pgprot(prot
);
742 prot
|= _PAGE_NO_CACHE
| _PAGE_GUARDED
;
744 for_each_pci_dev(pdev
) {
745 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++) {
746 struct resource
*rp
= &pdev
->resource
[i
];
747 int flags
= rp
->flags
;
749 /* Active and same type? */
750 if ((flags
& IORESOURCE_MEM
) == 0)
752 /* In the range of this resource? */
753 if (offset
< (rp
->start
& PAGE_MASK
) ||
763 if (found
->flags
& IORESOURCE_PREFETCH
)
764 prot
&= ~_PAGE_GUARDED
;
768 DBG("non-PCI map for %lx, prot: %lx\n", offset
, prot
);
770 return __pgprot(prot
);
775 * Perform the actual remap of the pages for a PCI device mapping, as
776 * appropriate for this architecture. The region in the process to map
777 * is described by vm_start and vm_end members of VMA, the base physical
778 * address is found in vm_pgoff.
779 * The pci device structure is provided so that architectures may make mapping
780 * decisions on a per-device or per-bus basis.
782 * Returns a negative error code on failure, zero on success.
784 int pci_mmap_page_range(struct pci_dev
*dev
, struct vm_area_struct
*vma
,
785 enum pci_mmap_state mmap_state
,
788 unsigned long offset
= vma
->vm_pgoff
<< PAGE_SHIFT
;
792 rp
= __pci_mmap_make_offset(dev
, &offset
, mmap_state
);
796 vma
->vm_pgoff
= offset
>> PAGE_SHIFT
;
797 vma
->vm_flags
|= VM_SHM
| VM_LOCKED
| VM_IO
;
798 vma
->vm_page_prot
= __pci_mmap_set_pgprot(dev
, rp
,
800 mmap_state
, write_combine
);
802 ret
= remap_pfn_range(vma
, vma
->vm_start
, vma
->vm_pgoff
,
803 vma
->vm_end
- vma
->vm_start
, vma
->vm_page_prot
);
808 #ifdef CONFIG_PPC_MULTIPLATFORM
809 static ssize_t
pci_show_devspec(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
811 struct pci_dev
*pdev
;
812 struct device_node
*np
;
814 pdev
= to_pci_dev (dev
);
815 np
= pci_device_to_OF_node(pdev
);
816 if (np
== NULL
|| np
->full_name
== NULL
)
818 return sprintf(buf
, "%s", np
->full_name
);
820 static DEVICE_ATTR(devspec
, S_IRUGO
, pci_show_devspec
, NULL
);
821 #endif /* CONFIG_PPC_MULTIPLATFORM */
823 void pcibios_add_platform_entries(struct pci_dev
*pdev
)
825 #ifdef CONFIG_PPC_MULTIPLATFORM
826 device_create_file(&pdev
->dev
, &dev_attr_devspec
);
827 #endif /* CONFIG_PPC_MULTIPLATFORM */
830 #ifdef CONFIG_PPC_MULTIPLATFORM
832 #define ISA_SPACE_MASK 0x1
833 #define ISA_SPACE_IO 0x1
835 static void __devinit
pci_process_ISA_OF_ranges(struct device_node
*isa_node
,
836 unsigned long phb_io_base_phys
,
837 void __iomem
* phb_io_base_virt
)
839 struct isa_range
*range
;
840 unsigned long pci_addr
;
841 unsigned int isa_addr
;
845 range
= (struct isa_range
*) get_property(isa_node
, "ranges", &rlen
);
846 if (range
== NULL
|| (rlen
< sizeof(struct isa_range
))) {
847 printk(KERN_ERR
"no ISA ranges or unexpected isa range size,"
849 __ioremap_explicit(phb_io_base_phys
,
850 (unsigned long)phb_io_base_virt
,
851 0x10000, _PAGE_NO_CACHE
| _PAGE_GUARDED
);
855 /* From "ISA Binding to 1275"
856 * The ranges property is laid out as an array of elements,
857 * each of which comprises:
858 * cells 0 - 1: an ISA address
859 * cells 2 - 4: a PCI address
860 * (size depending on dev->n_addr_cells)
861 * cell 5: the size of the range
863 if ((range
->isa_addr
.a_hi
&& ISA_SPACE_MASK
) == ISA_SPACE_IO
) {
864 isa_addr
= range
->isa_addr
.a_lo
;
865 pci_addr
= (unsigned long) range
->pci_addr
.a_mid
<< 32 |
866 range
->pci_addr
.a_lo
;
868 /* Assume these are both zero */
869 if ((pci_addr
!= 0) || (isa_addr
!= 0)) {
870 printk(KERN_ERR
"unexpected isa to pci mapping: %s\n",
875 size
= PAGE_ALIGN(range
->size
);
877 __ioremap_explicit(phb_io_base_phys
,
878 (unsigned long) phb_io_base_virt
,
879 size
, _PAGE_NO_CACHE
| _PAGE_GUARDED
);
883 void __devinit
pci_process_bridge_OF_ranges(struct pci_controller
*hose
,
884 struct device_node
*dev
)
886 unsigned int *ranges
;
890 struct resource
*res
;
891 int np
, na
= prom_n_addr_cells(dev
);
892 unsigned long pci_addr
, cpu_phys_addr
;
896 /* From "PCI Binding to 1275"
897 * The ranges property is laid out as an array of elements,
898 * each of which comprises:
899 * cells 0 - 2: a PCI address
900 * cells 3 or 3+4: a CPU physical address
901 * (size depending on dev->n_addr_cells)
902 * cells 4+5 or 5+6: the size of the range
905 hose
->io_base_phys
= 0;
906 ranges
= (unsigned int *) get_property(dev
, "ranges", &rlen
);
907 while ((rlen
-= np
* sizeof(unsigned int)) >= 0) {
909 pci_addr
= (unsigned long)ranges
[1] << 32 | ranges
[2];
911 cpu_phys_addr
= ranges
[3];
913 cpu_phys_addr
= cpu_phys_addr
<< 32 | ranges
[4];
915 size
= (unsigned long)ranges
[na
+3] << 32 | ranges
[na
+4];
918 switch ((ranges
[0] >> 24) & 0x3) {
919 case 1: /* I/O space */
920 hose
->io_base_phys
= cpu_phys_addr
;
921 hose
->pci_io_size
= size
;
923 res
= &hose
->io_resource
;
924 res
->flags
= IORESOURCE_IO
;
925 res
->start
= pci_addr
;
926 DBG("phb%d: IO 0x%lx -> 0x%lx\n", hose
->global_number
,
927 res
->start
, res
->start
+ size
- 1);
929 case 2: /* memory space */
931 while (memno
< 3 && hose
->mem_resources
[memno
].flags
)
935 hose
->pci_mem_offset
= cpu_phys_addr
- pci_addr
;
937 res
= &hose
->mem_resources
[memno
];
938 res
->flags
= IORESOURCE_MEM
;
939 res
->start
= cpu_phys_addr
;
940 DBG("phb%d: MEM 0x%lx -> 0x%lx\n", hose
->global_number
,
941 res
->start
, res
->start
+ size
- 1);
946 res
->name
= dev
->full_name
;
947 res
->end
= res
->start
+ size
- 1;
956 void __init
pci_setup_phb_io(struct pci_controller
*hose
, int primary
)
958 unsigned long size
= hose
->pci_io_size
;
959 unsigned long io_virt_offset
;
960 struct resource
*res
;
961 struct device_node
*isa_dn
;
963 hose
->io_base_virt
= reserve_phb_iospace(size
);
964 DBG("phb%d io_base_phys 0x%lx io_base_virt 0x%lx\n",
965 hose
->global_number
, hose
->io_base_phys
,
966 (unsigned long) hose
->io_base_virt
);
969 pci_io_base
= (unsigned long)hose
->io_base_virt
;
970 isa_dn
= of_find_node_by_type(NULL
, "isa");
972 isa_io_base
= pci_io_base
;
973 pci_process_ISA_OF_ranges(isa_dn
, hose
->io_base_phys
,
981 io_virt_offset
= (unsigned long)hose
->io_base_virt
- pci_io_base
;
982 res
= &hose
->io_resource
;
983 res
->start
+= io_virt_offset
;
984 res
->end
+= io_virt_offset
;
987 void __devinit
pci_setup_phb_io_dynamic(struct pci_controller
*hose
,
990 unsigned long size
= hose
->pci_io_size
;
991 unsigned long io_virt_offset
;
992 struct resource
*res
;
994 hose
->io_base_virt
= __ioremap(hose
->io_base_phys
, size
,
995 _PAGE_NO_CACHE
| _PAGE_GUARDED
);
996 DBG("phb%d io_base_phys 0x%lx io_base_virt 0x%lx\n",
997 hose
->global_number
, hose
->io_base_phys
,
998 (unsigned long) hose
->io_base_virt
);
1001 pci_io_base
= (unsigned long)hose
->io_base_virt
;
1003 io_virt_offset
= (unsigned long)hose
->io_base_virt
- pci_io_base
;
1004 res
= &hose
->io_resource
;
1005 res
->start
+= io_virt_offset
;
1006 res
->end
+= io_virt_offset
;
1010 static int get_bus_io_range(struct pci_bus
*bus
, unsigned long *start_phys
,
1011 unsigned long *start_virt
, unsigned long *size
)
1013 struct pci_controller
*hose
= pci_bus_to_host(bus
);
1014 struct pci_bus_region region
;
1015 struct resource
*res
;
1018 res
= bus
->resource
[0];
1019 pcibios_resource_to_bus(bus
->self
, ®ion
, res
);
1020 *start_phys
= hose
->io_base_phys
+ region
.start
;
1021 *start_virt
= (unsigned long) hose
->io_base_virt
+
1023 if (region
.end
> region
.start
)
1024 *size
= region
.end
- region
.start
+ 1;
1026 printk("%s(): unexpected region 0x%lx->0x%lx\n",
1027 __FUNCTION__
, region
.start
, region
.end
);
1033 res
= &hose
->io_resource
;
1034 *start_phys
= hose
->io_base_phys
;
1035 *start_virt
= (unsigned long) hose
->io_base_virt
;
1036 if (res
->end
> res
->start
)
1037 *size
= res
->end
- res
->start
+ 1;
1039 printk("%s(): unexpected region 0x%lx->0x%lx\n",
1040 __FUNCTION__
, res
->start
, res
->end
);
1048 int unmap_bus_range(struct pci_bus
*bus
)
1050 unsigned long start_phys
;
1051 unsigned long start_virt
;
1055 printk(KERN_ERR
"%s() expected bus\n", __FUNCTION__
);
1059 if (get_bus_io_range(bus
, &start_phys
, &start_virt
, &size
))
1061 if (iounmap_explicit((void __iomem
*) start_virt
, size
))
1066 EXPORT_SYMBOL(unmap_bus_range
);
1068 int remap_bus_range(struct pci_bus
*bus
)
1070 unsigned long start_phys
;
1071 unsigned long start_virt
;
1075 printk(KERN_ERR
"%s() expected bus\n", __FUNCTION__
);
1080 if (get_bus_io_range(bus
, &start_phys
, &start_virt
, &size
))
1082 printk("mapping IO %lx -> %lx, size: %lx\n", start_phys
, start_virt
, size
);
1083 if (__ioremap_explicit(start_phys
, start_virt
, size
,
1084 _PAGE_NO_CACHE
| _PAGE_GUARDED
))
1089 EXPORT_SYMBOL(remap_bus_range
);
1091 void phbs_remap_io(void)
1093 struct pci_controller
*hose
, *tmp
;
1095 list_for_each_entry_safe(hose
, tmp
, &hose_list
, list_node
)
1096 remap_bus_range(hose
->bus
);
1100 * ppc64 can have multifunction devices that do not respond to function 0.
1101 * In this case we must scan all functions.
1102 * XXX this can go now, we use the OF device tree in all the
1103 * cases that caused problems. -- paulus
1105 int pcibios_scan_all_fns(struct pci_bus
*bus
, int devfn
)
1110 static void __devinit
fixup_resource(struct resource
*res
, struct pci_dev
*dev
)
1112 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
1113 unsigned long start
, end
, mask
, offset
;
1115 if (res
->flags
& IORESOURCE_IO
) {
1116 offset
= (unsigned long)hose
->io_base_virt
- pci_io_base
;
1118 start
= res
->start
+= offset
;
1119 end
= res
->end
+= offset
;
1121 /* Need to allow IO access to pages that are in the
1123 if (start
< MAX_ISA_PORT
) {
1124 if (end
> MAX_ISA_PORT
)
1127 start
>>= PAGE_SHIFT
;
1130 /* get the range of pages for the map */
1131 mask
= ((1 << (end
+1)) - 1) ^ ((1 << start
) - 1);
1132 io_page_mask
|= mask
;
1134 } else if (res
->flags
& IORESOURCE_MEM
) {
1135 res
->start
+= hose
->pci_mem_offset
;
1136 res
->end
+= hose
->pci_mem_offset
;
1140 void __devinit
pcibios_fixup_device_resources(struct pci_dev
*dev
,
1141 struct pci_bus
*bus
)
1143 /* Update device resources. */
1146 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++)
1147 if (dev
->resource
[i
].flags
)
1148 fixup_resource(&dev
->resource
[i
], dev
);
1150 EXPORT_SYMBOL(pcibios_fixup_device_resources
);
1152 static void __devinit
do_bus_setup(struct pci_bus
*bus
)
1154 struct pci_dev
*dev
;
1156 ppc_md
.iommu_bus_setup(bus
);
1158 list_for_each_entry(dev
, &bus
->devices
, bus_list
)
1159 ppc_md
.iommu_dev_setup(dev
);
1161 if (ppc_md
.irq_bus_setup
)
1162 ppc_md
.irq_bus_setup(bus
);
1165 void __devinit
pcibios_fixup_bus(struct pci_bus
*bus
)
1167 struct pci_dev
*dev
= bus
->self
;
1169 if (dev
&& pci_probe_only
&&
1170 (dev
->class >> 8) == PCI_CLASS_BRIDGE_PCI
) {
1171 /* This is a subordinate bridge */
1173 pci_read_bridge_bases(bus
);
1174 pcibios_fixup_device_resources(dev
, bus
);
1179 if (!pci_probe_only
)
1182 list_for_each_entry(dev
, &bus
->devices
, bus_list
)
1183 if ((dev
->class >> 8) != PCI_CLASS_BRIDGE_PCI
)
1184 pcibios_fixup_device_resources(dev
, bus
);
1186 EXPORT_SYMBOL(pcibios_fixup_bus
);
1189 * Reads the interrupt pin to determine if interrupt is use by card.
1190 * If the interrupt is used, then gets the interrupt line from the
1191 * openfirmware and sets it in the pci_dev and pci_config line.
1193 int pci_read_irq_line(struct pci_dev
*pci_dev
)
1196 struct device_node
*node
;
1198 pci_read_config_byte(pci_dev
, PCI_INTERRUPT_PIN
, &intpin
);
1202 node
= pci_device_to_OF_node(pci_dev
);
1206 if (node
->n_intrs
== 0)
1209 pci_dev
->irq
= node
->intrs
[0].line
;
1211 pci_write_config_byte(pci_dev
, PCI_INTERRUPT_LINE
, pci_dev
->irq
);
1215 EXPORT_SYMBOL(pci_read_irq_line
);
1217 void pci_resource_to_user(const struct pci_dev
*dev
, int bar
,
1218 const struct resource
*rsrc
,
1219 u64
*start
, u64
*end
)
1221 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
1222 unsigned long offset
= 0;
1227 if (rsrc
->flags
& IORESOURCE_IO
)
1228 offset
= pci_io_base
- (unsigned long)hose
->io_base_virt
+
1231 *start
= rsrc
->start
+ offset
;
1232 *end
= rsrc
->end
+ offset
;
1235 #endif /* CONFIG_PPC_MULTIPLATFORM */
1238 #define IOBASE_BRIDGE_NUMBER 0
1239 #define IOBASE_MEMORY 1
1241 #define IOBASE_ISA_IO 3
1242 #define IOBASE_ISA_MEM 4
1244 long sys_pciconfig_iobase(long which
, unsigned long in_bus
,
1245 unsigned long in_devfn
)
1247 struct pci_controller
* hose
;
1248 struct list_head
*ln
;
1249 struct pci_bus
*bus
= NULL
;
1250 struct device_node
*hose_node
;
1252 /* Argh ! Please forgive me for that hack, but that's the
1253 * simplest way to get existing XFree to not lockup on some
1254 * G5 machines... So when something asks for bus 0 io base
1255 * (bus 0 is HT root), we return the AGP one instead.
1257 #ifdef CONFIG_PPC_PMAC
1258 if (systemcfg
->platform
== PLATFORM_POWERMAC
&&
1259 machine_is_compatible("MacRISC4"))
1262 #endif /* CONFIG_PPC_PMAC */
1264 /* That syscall isn't quite compatible with PCI domains, but it's
1265 * used on pre-domains setup. We return the first match
1268 for (ln
= pci_root_buses
.next
; ln
!= &pci_root_buses
; ln
= ln
->next
) {
1269 bus
= pci_bus_b(ln
);
1270 if (in_bus
>= bus
->number
&& in_bus
< (bus
->number
+ bus
->subordinate
))
1274 if (bus
== NULL
|| bus
->sysdata
== NULL
)
1277 hose_node
= (struct device_node
*)bus
->sysdata
;
1278 hose
= PCI_DN(hose_node
)->phb
;
1281 case IOBASE_BRIDGE_NUMBER
:
1282 return (long)hose
->first_busno
;
1284 return (long)hose
->pci_mem_offset
;
1286 return (long)hose
->io_base_phys
;
1288 return (long)isa_io_base
;
1289 case IOBASE_ISA_MEM
: