arch/s390/include/asm/barrier.h

   1 /*
   2  * Copyright IBM Corp. 1999, 2009
   3  *
   4  * Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>
   5  */
   6
   7 #ifndef __ASM_BARRIER_H
   8 #define __ASM_BARRIER_H
   9
  10 /*
  11  * Force strict CPU ordering.
  12  * And yes, this is required on UP too when we're talking
  13  * to devices.
  14  */
  15
  16 #ifdef CONFIG_HAVE_MARCH_Z196_FEATURES
  17 /* Fast-BCR without checkpoint synchronization */
  18 #define __ASM_BARRIER "bcr 14,0\n"
  19 #else
  20 #define __ASM_BARRIER "bcr 15,0\n"
  21 #endif
  22
  23 #define mb() do {  asm volatile(__ASM_BARRIER : : : "memory"); } while (0)
  24
  25 #define rmb()                           barrier()
  26 #define wmb()                           barrier()
  27 #define dma_rmb()                       mb()
  28 #define dma_wmb()                       mb()
  29 #define smp_mb()                        mb()
  30 #define smp_rmb()                       rmb()
  31 #define smp_wmb()                       wmb()
  32
  33 #define smp_store_release(p, v)                                         \
  34 do {                                                                    \
  35         compiletime_assert_atomic_type(*p);                             \
  36         barrier();                                                      \
  37         WRITE_ONCE(*p, v);                                              \
  38 } while (0)
  39
  40 #define smp_load_acquire(p)                                             \
  41 ({                                                                      \
  42         typeof(*p) ___p1 = READ_ONCE(*p);                               \
  43         compiletime_assert_atomic_type(*p);                             \
  44         barrier();                                                      \
  45         ___p1;                                                          \
  46 })
  47
  48 #include <asm-generic/barrier.h>
  49
  50 #endif /* __ASM_BARRIER_H */