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Merge branch 'for-linus-4.4' of git://git.kernel.org/pub/scm/linux/kernel/git/mason...
[deliverable/linux.git] / arch / s390 / include / asm / pgtable.h
1 /*
2 * S390 version
3 * Copyright IBM Corp. 1999, 2000
4 * Author(s): Hartmut Penner (hp@de.ibm.com)
5 * Ulrich Weigand (weigand@de.ibm.com)
6 * Martin Schwidefsky (schwidefsky@de.ibm.com)
7 *
8 * Derived from "include/asm-i386/pgtable.h"
9 */
10
11 #ifndef _ASM_S390_PGTABLE_H
12 #define _ASM_S390_PGTABLE_H
13
14 /*
15 * The Linux memory management assumes a three-level page table setup.
16 * For s390 64 bit we use up to four of the five levels the hardware
17 * provides (region first tables are not used).
18 *
19 * The "pgd_xxx()" functions are trivial for a folded two-level
20 * setup: the pgd is never bad, and a pmd always exists (as it's folded
21 * into the pgd entry)
22 *
23 * This file contains the functions and defines necessary to modify and use
24 * the S390 page table tree.
25 */
26 #ifndef __ASSEMBLY__
27 #include <linux/sched.h>
28 #include <linux/mm_types.h>
29 #include <linux/page-flags.h>
30 #include <linux/radix-tree.h>
31 #include <asm/bug.h>
32 #include <asm/page.h>
33
34 extern pgd_t swapper_pg_dir[] __attribute__ ((aligned (4096)));
35 extern void paging_init(void);
36 extern void vmem_map_init(void);
37
38 /*
39 * The S390 doesn't have any external MMU info: the kernel page
40 * tables contain all the necessary information.
41 */
42 #define update_mmu_cache(vma, address, ptep) do { } while (0)
43 #define update_mmu_cache_pmd(vma, address, ptep) do { } while (0)
44
45 /*
46 * ZERO_PAGE is a global shared page that is always zero; used
47 * for zero-mapped memory areas etc..
48 */
49
50 extern unsigned long empty_zero_page;
51 extern unsigned long zero_page_mask;
52
53 #define ZERO_PAGE(vaddr) \
54 (virt_to_page((void *)(empty_zero_page + \
55 (((unsigned long)(vaddr)) &zero_page_mask))))
56 #define __HAVE_COLOR_ZERO_PAGE
57
58 /* TODO: s390 cannot support io_remap_pfn_range... */
59 #endif /* !__ASSEMBLY__ */
60
61 /*
62 * PMD_SHIFT determines the size of the area a second-level page
63 * table can map
64 * PGDIR_SHIFT determines what a third-level page table entry can map
65 */
66 #define PMD_SHIFT 20
67 #define PUD_SHIFT 31
68 #define PGDIR_SHIFT 42
69
70 #define PMD_SIZE (1UL << PMD_SHIFT)
71 #define PMD_MASK (~(PMD_SIZE-1))
72 #define PUD_SIZE (1UL << PUD_SHIFT)
73 #define PUD_MASK (~(PUD_SIZE-1))
74 #define PGDIR_SIZE (1UL << PGDIR_SHIFT)
75 #define PGDIR_MASK (~(PGDIR_SIZE-1))
76
77 /*
78 * entries per page directory level: the S390 is two-level, so
79 * we don't really have any PMD directory physically.
80 * for S390 segment-table entries are combined to one PGD
81 * that leads to 1024 pte per pgd
82 */
83 #define PTRS_PER_PTE 256
84 #define PTRS_PER_PMD 2048
85 #define PTRS_PER_PUD 2048
86 #define PTRS_PER_PGD 2048
87
88 #define FIRST_USER_ADDRESS 0UL
89
90 #define pte_ERROR(e) \
91 printk("%s:%d: bad pte %p.\n", __FILE__, __LINE__, (void *) pte_val(e))
92 #define pmd_ERROR(e) \
93 printk("%s:%d: bad pmd %p.\n", __FILE__, __LINE__, (void *) pmd_val(e))
94 #define pud_ERROR(e) \
95 printk("%s:%d: bad pud %p.\n", __FILE__, __LINE__, (void *) pud_val(e))
96 #define pgd_ERROR(e) \
97 printk("%s:%d: bad pgd %p.\n", __FILE__, __LINE__, (void *) pgd_val(e))
98
99 #ifndef __ASSEMBLY__
100 /*
101 * The vmalloc and module area will always be on the topmost area of the
102 * kernel mapping. We reserve 128GB (64bit) for vmalloc and modules.
103 * On 64 bit kernels we have a 2GB area at the top of the vmalloc area where
104 * modules will reside. That makes sure that inter module branches always
105 * happen without trampolines and in addition the placement within a 2GB frame
106 * is branch prediction unit friendly.
107 */
108 extern unsigned long VMALLOC_START;
109 extern unsigned long VMALLOC_END;
110 extern struct page *vmemmap;
111
112 #define VMEM_MAX_PHYS ((unsigned long) vmemmap)
113
114 extern unsigned long MODULES_VADDR;
115 extern unsigned long MODULES_END;
116 #define MODULES_VADDR MODULES_VADDR
117 #define MODULES_END MODULES_END
118 #define MODULES_LEN (1UL << 31)
119
120 static inline int is_module_addr(void *addr)
121 {
122 BUILD_BUG_ON(MODULES_LEN > (1UL << 31));
123 if (addr < (void *)MODULES_VADDR)
124 return 0;
125 if (addr > (void *)MODULES_END)
126 return 0;
127 return 1;
128 }
129
130 /*
131 * A 64 bit pagetable entry of S390 has following format:
132 * | PFRA |0IPC| OS |
133 * 0000000000111111111122222222223333333333444444444455555555556666
134 * 0123456789012345678901234567890123456789012345678901234567890123
135 *
136 * I Page-Invalid Bit: Page is not available for address-translation
137 * P Page-Protection Bit: Store access not possible for page
138 * C Change-bit override: HW is not required to set change bit
139 *
140 * A 64 bit segmenttable entry of S390 has following format:
141 * | P-table origin | TT
142 * 0000000000111111111122222222223333333333444444444455555555556666
143 * 0123456789012345678901234567890123456789012345678901234567890123
144 *
145 * I Segment-Invalid Bit: Segment is not available for address-translation
146 * C Common-Segment Bit: Segment is not private (PoP 3-30)
147 * P Page-Protection Bit: Store access not possible for page
148 * TT Type 00
149 *
150 * A 64 bit region table entry of S390 has following format:
151 * | S-table origin | TF TTTL
152 * 0000000000111111111122222222223333333333444444444455555555556666
153 * 0123456789012345678901234567890123456789012345678901234567890123
154 *
155 * I Segment-Invalid Bit: Segment is not available for address-translation
156 * TT Type 01
157 * TF
158 * TL Table length
159 *
160 * The 64 bit regiontable origin of S390 has following format:
161 * | region table origon | DTTL
162 * 0000000000111111111122222222223333333333444444444455555555556666
163 * 0123456789012345678901234567890123456789012345678901234567890123
164 *
165 * X Space-Switch event:
166 * G Segment-Invalid Bit:
167 * P Private-Space Bit:
168 * S Storage-Alteration:
169 * R Real space
170 * TL Table-Length:
171 *
172 * A storage key has the following format:
173 * | ACC |F|R|C|0|
174 * 0 3 4 5 6 7
175 * ACC: access key
176 * F : fetch protection bit
177 * R : referenced bit
178 * C : changed bit
179 */
180
181 /* Hardware bits in the page table entry */
182 #define _PAGE_PROTECT 0x200 /* HW read-only bit */
183 #define _PAGE_INVALID 0x400 /* HW invalid bit */
184 #define _PAGE_LARGE 0x800 /* Bit to mark a large pte */
185
186 /* Software bits in the page table entry */
187 #define _PAGE_PRESENT 0x001 /* SW pte present bit */
188 #define _PAGE_YOUNG 0x004 /* SW pte young bit */
189 #define _PAGE_DIRTY 0x008 /* SW pte dirty bit */
190 #define _PAGE_READ 0x010 /* SW pte read bit */
191 #define _PAGE_WRITE 0x020 /* SW pte write bit */
192 #define _PAGE_SPECIAL 0x040 /* SW associated with special page */
193 #define _PAGE_UNUSED 0x080 /* SW bit for pgste usage state */
194 #define __HAVE_ARCH_PTE_SPECIAL
195
196 #ifdef CONFIG_MEM_SOFT_DIRTY
197 #define _PAGE_SOFT_DIRTY 0x002 /* SW pte soft dirty bit */
198 #else
199 #define _PAGE_SOFT_DIRTY 0x000
200 #endif
201
202 /* Set of bits not changed in pte_modify */
203 #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_SPECIAL | _PAGE_DIRTY | \
204 _PAGE_YOUNG | _PAGE_SOFT_DIRTY)
205
206 /*
207 * handle_pte_fault uses pte_present and pte_none to find out the pte type
208 * WITHOUT holding the page table lock. The _PAGE_PRESENT bit is used to
209 * distinguish present from not-present ptes. It is changed only with the page
210 * table lock held.
211 *
212 * The following table gives the different possible bit combinations for
213 * the pte hardware and software bits in the last 12 bits of a pte
214 * (. unassigned bit, x don't care, t swap type):
215 *
216 * 842100000000
217 * 000084210000
218 * 000000008421
219 * .IR.uswrdy.p
220 * empty .10.00000000
221 * swap .11..ttttt.0
222 * prot-none, clean, old .11.xx0000.1
223 * prot-none, clean, young .11.xx0001.1
224 * prot-none, dirty, old .10.xx0010.1
225 * prot-none, dirty, young .10.xx0011.1
226 * read-only, clean, old .11.xx0100.1
227 * read-only, clean, young .01.xx0101.1
228 * read-only, dirty, old .11.xx0110.1
229 * read-only, dirty, young .01.xx0111.1
230 * read-write, clean, old .11.xx1100.1
231 * read-write, clean, young .01.xx1101.1
232 * read-write, dirty, old .10.xx1110.1
233 * read-write, dirty, young .00.xx1111.1
234 * HW-bits: R read-only, I invalid
235 * SW-bits: p present, y young, d dirty, r read, w write, s special,
236 * u unused, l large
237 *
238 * pte_none is true for the bit pattern .10.00000000, pte == 0x400
239 * pte_swap is true for the bit pattern .11..ooooo.0, (pte & 0x201) == 0x200
240 * pte_present is true for the bit pattern .xx.xxxxxx.1, (pte & 0x001) == 0x001
241 */
242
243 /* Bits in the segment/region table address-space-control-element */
244 #define _ASCE_ORIGIN ~0xfffUL/* segment table origin */
245 #define _ASCE_PRIVATE_SPACE 0x100 /* private space control */
246 #define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */
247 #define _ASCE_SPACE_SWITCH 0x40 /* space switch event */
248 #define _ASCE_REAL_SPACE 0x20 /* real space control */
249 #define _ASCE_TYPE_MASK 0x0c /* asce table type mask */
250 #define _ASCE_TYPE_REGION1 0x0c /* region first table type */
251 #define _ASCE_TYPE_REGION2 0x08 /* region second table type */
252 #define _ASCE_TYPE_REGION3 0x04 /* region third table type */
253 #define _ASCE_TYPE_SEGMENT 0x00 /* segment table type */
254 #define _ASCE_TABLE_LENGTH 0x03 /* region table length */
255
256 /* Bits in the region table entry */
257 #define _REGION_ENTRY_ORIGIN ~0xfffUL/* region/segment table origin */
258 #define _REGION_ENTRY_PROTECT 0x200 /* region protection bit */
259 #define _REGION_ENTRY_INVALID 0x20 /* invalid region table entry */
260 #define _REGION_ENTRY_TYPE_MASK 0x0c /* region/segment table type mask */
261 #define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type */
262 #define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type */
263 #define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type */
264 #define _REGION_ENTRY_LENGTH 0x03 /* region third length */
265
266 #define _REGION1_ENTRY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_LENGTH)
267 #define _REGION1_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_INVALID)
268 #define _REGION2_ENTRY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_LENGTH)
269 #define _REGION2_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_INVALID)
270 #define _REGION3_ENTRY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_LENGTH)
271 #define _REGION3_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_INVALID)
272
273 #define _REGION3_ENTRY_LARGE 0x400 /* RTTE-format control, large page */
274 #define _REGION3_ENTRY_RO 0x200 /* page protection bit */
275
276 /* Bits in the segment table entry */
277 #define _SEGMENT_ENTRY_BITS 0xfffffffffffffe33UL
278 #define _SEGMENT_ENTRY_BITS_LARGE 0xfffffffffff0ff33UL
279 #define _SEGMENT_ENTRY_ORIGIN_LARGE ~0xfffffUL /* large page address */
280 #define _SEGMENT_ENTRY_ORIGIN ~0x7ffUL/* segment table origin */
281 #define _SEGMENT_ENTRY_PROTECT 0x200 /* page protection bit */
282 #define _SEGMENT_ENTRY_INVALID 0x20 /* invalid segment table entry */
283
284 #define _SEGMENT_ENTRY (0)
285 #define _SEGMENT_ENTRY_EMPTY (_SEGMENT_ENTRY_INVALID)
286
287 #define _SEGMENT_ENTRY_DIRTY 0x2000 /* SW segment dirty bit */
288 #define _SEGMENT_ENTRY_YOUNG 0x1000 /* SW segment young bit */
289 #define _SEGMENT_ENTRY_SPLIT 0x0800 /* THP splitting bit */
290 #define _SEGMENT_ENTRY_LARGE 0x0400 /* STE-format control, large page */
291 #define _SEGMENT_ENTRY_READ 0x0002 /* SW segment read bit */
292 #define _SEGMENT_ENTRY_WRITE 0x0001 /* SW segment write bit */
293
294 #ifdef CONFIG_MEM_SOFT_DIRTY
295 #define _SEGMENT_ENTRY_SOFT_DIRTY 0x4000 /* SW segment soft dirty bit */
296 #else
297 #define _SEGMENT_ENTRY_SOFT_DIRTY 0x0000 /* SW segment soft dirty bit */
298 #endif
299
300 /*
301 * Segment table entry encoding (R = read-only, I = invalid, y = young bit):
302 * dy..R...I...wr
303 * prot-none, clean, old 00..1...1...00
304 * prot-none, clean, young 01..1...1...00
305 * prot-none, dirty, old 10..1...1...00
306 * prot-none, dirty, young 11..1...1...00
307 * read-only, clean, old 00..1...1...01
308 * read-only, clean, young 01..1...0...01
309 * read-only, dirty, old 10..1...1...01
310 * read-only, dirty, young 11..1...0...01
311 * read-write, clean, old 00..1...1...11
312 * read-write, clean, young 01..1...0...11
313 * read-write, dirty, old 10..0...1...11
314 * read-write, dirty, young 11..0...0...11
315 * The segment table origin is used to distinguish empty (origin==0) from
316 * read-write, old segment table entries (origin!=0)
317 * HW-bits: R read-only, I invalid
318 * SW-bits: y young, d dirty, r read, w write
319 */
320
321 #define _SEGMENT_ENTRY_SPLIT_BIT 11 /* THP splitting bit number */
322
323 /* Page status table bits for virtualization */
324 #define PGSTE_ACC_BITS 0xf000000000000000UL
325 #define PGSTE_FP_BIT 0x0800000000000000UL
326 #define PGSTE_PCL_BIT 0x0080000000000000UL
327 #define PGSTE_HR_BIT 0x0040000000000000UL
328 #define PGSTE_HC_BIT 0x0020000000000000UL
329 #define PGSTE_GR_BIT 0x0004000000000000UL
330 #define PGSTE_GC_BIT 0x0002000000000000UL
331 #define PGSTE_UC_BIT 0x0000800000000000UL /* user dirty (migration) */
332 #define PGSTE_IN_BIT 0x0000400000000000UL /* IPTE notify bit */
333
334 /* Guest Page State used for virtualization */
335 #define _PGSTE_GPS_ZERO 0x0000000080000000UL
336 #define _PGSTE_GPS_USAGE_MASK 0x0000000003000000UL
337 #define _PGSTE_GPS_USAGE_STABLE 0x0000000000000000UL
338 #define _PGSTE_GPS_USAGE_UNUSED 0x0000000001000000UL
339
340 /*
341 * A user page table pointer has the space-switch-event bit, the
342 * private-space-control bit and the storage-alteration-event-control
343 * bit set. A kernel page table pointer doesn't need them.
344 */
345 #define _ASCE_USER_BITS (_ASCE_SPACE_SWITCH | _ASCE_PRIVATE_SPACE | \
346 _ASCE_ALT_EVENT)
347
348 /*
349 * Page protection definitions.
350 */
351 #define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_INVALID)
352 #define PAGE_READ __pgprot(_PAGE_PRESENT | _PAGE_READ | \
353 _PAGE_INVALID | _PAGE_PROTECT)
354 #define PAGE_WRITE __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \
355 _PAGE_INVALID | _PAGE_PROTECT)
356
357 #define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \
358 _PAGE_YOUNG | _PAGE_DIRTY)
359 #define PAGE_KERNEL __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \
360 _PAGE_YOUNG | _PAGE_DIRTY)
361 #define PAGE_KERNEL_RO __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_YOUNG | \
362 _PAGE_PROTECT)
363
364 /*
365 * On s390 the page table entry has an invalid bit and a read-only bit.
366 * Read permission implies execute permission and write permission
367 * implies read permission.
368 */
369 /*xwr*/
370 #define __P000 PAGE_NONE
371 #define __P001 PAGE_READ
372 #define __P010 PAGE_READ
373 #define __P011 PAGE_READ
374 #define __P100 PAGE_READ
375 #define __P101 PAGE_READ
376 #define __P110 PAGE_READ
377 #define __P111 PAGE_READ
378
379 #define __S000 PAGE_NONE
380 #define __S001 PAGE_READ
381 #define __S010 PAGE_WRITE
382 #define __S011 PAGE_WRITE
383 #define __S100 PAGE_READ
384 #define __S101 PAGE_READ
385 #define __S110 PAGE_WRITE
386 #define __S111 PAGE_WRITE
387
388 /*
389 * Segment entry (large page) protection definitions.
390 */
391 #define SEGMENT_NONE __pgprot(_SEGMENT_ENTRY_INVALID | \
392 _SEGMENT_ENTRY_PROTECT)
393 #define SEGMENT_READ __pgprot(_SEGMENT_ENTRY_PROTECT | \
394 _SEGMENT_ENTRY_READ)
395 #define SEGMENT_WRITE __pgprot(_SEGMENT_ENTRY_READ | \
396 _SEGMENT_ENTRY_WRITE)
397
398 static inline int mm_has_pgste(struct mm_struct *mm)
399 {
400 #ifdef CONFIG_PGSTE
401 if (unlikely(mm->context.has_pgste))
402 return 1;
403 #endif
404 return 0;
405 }
406
407 static inline int mm_alloc_pgste(struct mm_struct *mm)
408 {
409 #ifdef CONFIG_PGSTE
410 if (unlikely(mm->context.alloc_pgste))
411 return 1;
412 #endif
413 return 0;
414 }
415
416 /*
417 * In the case that a guest uses storage keys
418 * faults should no longer be backed by zero pages
419 */
420 #define mm_forbids_zeropage mm_use_skey
421 static inline int mm_use_skey(struct mm_struct *mm)
422 {
423 #ifdef CONFIG_PGSTE
424 if (mm->context.use_skey)
425 return 1;
426 #endif
427 return 0;
428 }
429
430 /*
431 * pgd/pmd/pte query functions
432 */
433 static inline int pgd_present(pgd_t pgd)
434 {
435 if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2)
436 return 1;
437 return (pgd_val(pgd) & _REGION_ENTRY_ORIGIN) != 0UL;
438 }
439
440 static inline int pgd_none(pgd_t pgd)
441 {
442 if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2)
443 return 0;
444 return (pgd_val(pgd) & _REGION_ENTRY_INVALID) != 0UL;
445 }
446
447 static inline int pgd_bad(pgd_t pgd)
448 {
449 /*
450 * With dynamic page table levels the pgd can be a region table
451 * entry or a segment table entry. Check for the bit that are
452 * invalid for either table entry.
453 */
454 unsigned long mask =
455 ~_SEGMENT_ENTRY_ORIGIN & ~_REGION_ENTRY_INVALID &
456 ~_REGION_ENTRY_TYPE_MASK & ~_REGION_ENTRY_LENGTH;
457 return (pgd_val(pgd) & mask) != 0;
458 }
459
460 static inline int pud_present(pud_t pud)
461 {
462 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3)
463 return 1;
464 return (pud_val(pud) & _REGION_ENTRY_ORIGIN) != 0UL;
465 }
466
467 static inline int pud_none(pud_t pud)
468 {
469 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3)
470 return 0;
471 return (pud_val(pud) & _REGION_ENTRY_INVALID) != 0UL;
472 }
473
474 static inline int pud_large(pud_t pud)
475 {
476 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) != _REGION_ENTRY_TYPE_R3)
477 return 0;
478 return !!(pud_val(pud) & _REGION3_ENTRY_LARGE);
479 }
480
481 static inline int pud_bad(pud_t pud)
482 {
483 /*
484 * With dynamic page table levels the pud can be a region table
485 * entry or a segment table entry. Check for the bit that are
486 * invalid for either table entry.
487 */
488 unsigned long mask =
489 ~_SEGMENT_ENTRY_ORIGIN & ~_REGION_ENTRY_INVALID &
490 ~_REGION_ENTRY_TYPE_MASK & ~_REGION_ENTRY_LENGTH;
491 return (pud_val(pud) & mask) != 0;
492 }
493
494 static inline int pmd_present(pmd_t pmd)
495 {
496 return pmd_val(pmd) != _SEGMENT_ENTRY_INVALID;
497 }
498
499 static inline int pmd_none(pmd_t pmd)
500 {
501 return pmd_val(pmd) == _SEGMENT_ENTRY_INVALID;
502 }
503
504 static inline int pmd_large(pmd_t pmd)
505 {
506 return (pmd_val(pmd) & _SEGMENT_ENTRY_LARGE) != 0;
507 }
508
509 static inline unsigned long pmd_pfn(pmd_t pmd)
510 {
511 unsigned long origin_mask;
512
513 origin_mask = _SEGMENT_ENTRY_ORIGIN;
514 if (pmd_large(pmd))
515 origin_mask = _SEGMENT_ENTRY_ORIGIN_LARGE;
516 return (pmd_val(pmd) & origin_mask) >> PAGE_SHIFT;
517 }
518
519 static inline int pmd_bad(pmd_t pmd)
520 {
521 if (pmd_large(pmd))
522 return (pmd_val(pmd) & ~_SEGMENT_ENTRY_BITS_LARGE) != 0;
523 return (pmd_val(pmd) & ~_SEGMENT_ENTRY_BITS) != 0;
524 }
525
526 #define __HAVE_ARCH_PMDP_SPLITTING_FLUSH
527 extern void pmdp_splitting_flush(struct vm_area_struct *vma,
528 unsigned long addr, pmd_t *pmdp);
529
530 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS
531 extern int pmdp_set_access_flags(struct vm_area_struct *vma,
532 unsigned long address, pmd_t *pmdp,
533 pmd_t entry, int dirty);
534
535 #define __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH
536 extern int pmdp_clear_flush_young(struct vm_area_struct *vma,
537 unsigned long address, pmd_t *pmdp);
538
539 #define __HAVE_ARCH_PMD_WRITE
540 static inline int pmd_write(pmd_t pmd)
541 {
542 return (pmd_val(pmd) & _SEGMENT_ENTRY_WRITE) != 0;
543 }
544
545 static inline int pmd_dirty(pmd_t pmd)
546 {
547 int dirty = 1;
548 if (pmd_large(pmd))
549 dirty = (pmd_val(pmd) & _SEGMENT_ENTRY_DIRTY) != 0;
550 return dirty;
551 }
552
553 static inline int pmd_young(pmd_t pmd)
554 {
555 int young = 1;
556 if (pmd_large(pmd))
557 young = (pmd_val(pmd) & _SEGMENT_ENTRY_YOUNG) != 0;
558 return young;
559 }
560
561 static inline int pte_present(pte_t pte)
562 {
563 /* Bit pattern: (pte & 0x001) == 0x001 */
564 return (pte_val(pte) & _PAGE_PRESENT) != 0;
565 }
566
567 static inline int pte_none(pte_t pte)
568 {
569 /* Bit pattern: pte == 0x400 */
570 return pte_val(pte) == _PAGE_INVALID;
571 }
572
573 static inline int pte_swap(pte_t pte)
574 {
575 /* Bit pattern: (pte & 0x201) == 0x200 */
576 return (pte_val(pte) & (_PAGE_PROTECT | _PAGE_PRESENT))
577 == _PAGE_PROTECT;
578 }
579
580 static inline int pte_special(pte_t pte)
581 {
582 return (pte_val(pte) & _PAGE_SPECIAL);
583 }
584
585 #define __HAVE_ARCH_PTE_SAME
586 static inline int pte_same(pte_t a, pte_t b)
587 {
588 return pte_val(a) == pte_val(b);
589 }
590
591 #ifdef CONFIG_NUMA_BALANCING
592 static inline int pte_protnone(pte_t pte)
593 {
594 return pte_present(pte) && !(pte_val(pte) & _PAGE_READ);
595 }
596
597 static inline int pmd_protnone(pmd_t pmd)
598 {
599 /* pmd_large(pmd) implies pmd_present(pmd) */
600 return pmd_large(pmd) && !(pmd_val(pmd) & _SEGMENT_ENTRY_READ);
601 }
602 #endif
603
604 static inline int pte_soft_dirty(pte_t pte)
605 {
606 return pte_val(pte) & _PAGE_SOFT_DIRTY;
607 }
608 #define pte_swp_soft_dirty pte_soft_dirty
609
610 static inline pte_t pte_mksoft_dirty(pte_t pte)
611 {
612 pte_val(pte) |= _PAGE_SOFT_DIRTY;
613 return pte;
614 }
615 #define pte_swp_mksoft_dirty pte_mksoft_dirty
616
617 static inline pte_t pte_clear_soft_dirty(pte_t pte)
618 {
619 pte_val(pte) &= ~_PAGE_SOFT_DIRTY;
620 return pte;
621 }
622 #define pte_swp_clear_soft_dirty pte_clear_soft_dirty
623
624 static inline int pmd_soft_dirty(pmd_t pmd)
625 {
626 return pmd_val(pmd) & _SEGMENT_ENTRY_SOFT_DIRTY;
627 }
628
629 static inline pmd_t pmd_mksoft_dirty(pmd_t pmd)
630 {
631 pmd_val(pmd) |= _SEGMENT_ENTRY_SOFT_DIRTY;
632 return pmd;
633 }
634
635 static inline pmd_t pmd_clear_soft_dirty(pmd_t pmd)
636 {
637 pmd_val(pmd) &= ~_SEGMENT_ENTRY_SOFT_DIRTY;
638 return pmd;
639 }
640
641 static inline pgste_t pgste_get_lock(pte_t *ptep)
642 {
643 unsigned long new = 0;
644 #ifdef CONFIG_PGSTE
645 unsigned long old;
646
647 preempt_disable();
648 asm(
649 " lg %0,%2\n"
650 "0: lgr %1,%0\n"
651 " nihh %0,0xff7f\n" /* clear PCL bit in old */
652 " oihh %1,0x0080\n" /* set PCL bit in new */
653 " csg %0,%1,%2\n"
654 " jl 0b\n"
655 : "=&d" (old), "=&d" (new), "=Q" (ptep[PTRS_PER_PTE])
656 : "Q" (ptep[PTRS_PER_PTE]) : "cc", "memory");
657 #endif
658 return __pgste(new);
659 }
660
661 static inline void pgste_set_unlock(pte_t *ptep, pgste_t pgste)
662 {
663 #ifdef CONFIG_PGSTE
664 asm(
665 " nihh %1,0xff7f\n" /* clear PCL bit */
666 " stg %1,%0\n"
667 : "=Q" (ptep[PTRS_PER_PTE])
668 : "d" (pgste_val(pgste)), "Q" (ptep[PTRS_PER_PTE])
669 : "cc", "memory");
670 preempt_enable();
671 #endif
672 }
673
674 static inline pgste_t pgste_get(pte_t *ptep)
675 {
676 unsigned long pgste = 0;
677 #ifdef CONFIG_PGSTE
678 pgste = *(unsigned long *)(ptep + PTRS_PER_PTE);
679 #endif
680 return __pgste(pgste);
681 }
682
683 static inline void pgste_set(pte_t *ptep, pgste_t pgste)
684 {
685 #ifdef CONFIG_PGSTE
686 *(pgste_t *)(ptep + PTRS_PER_PTE) = pgste;
687 #endif
688 }
689
690 static inline pgste_t pgste_update_all(pte_t *ptep, pgste_t pgste,
691 struct mm_struct *mm)
692 {
693 #ifdef CONFIG_PGSTE
694 unsigned long address, bits, skey;
695
696 if (!mm_use_skey(mm) || pte_val(*ptep) & _PAGE_INVALID)
697 return pgste;
698 address = pte_val(*ptep) & PAGE_MASK;
699 skey = (unsigned long) page_get_storage_key(address);
700 bits = skey & (_PAGE_CHANGED | _PAGE_REFERENCED);
701 /* Transfer page changed & referenced bit to guest bits in pgste */
702 pgste_val(pgste) |= bits << 48; /* GR bit & GC bit */
703 /* Copy page access key and fetch protection bit to pgste */
704 pgste_val(pgste) &= ~(PGSTE_ACC_BITS | PGSTE_FP_BIT);
705 pgste_val(pgste) |= (skey & (_PAGE_ACC_BITS | _PAGE_FP_BIT)) << 56;
706 #endif
707 return pgste;
708
709 }
710
711 static inline void pgste_set_key(pte_t *ptep, pgste_t pgste, pte_t entry,
712 struct mm_struct *mm)
713 {
714 #ifdef CONFIG_PGSTE
715 unsigned long address;
716 unsigned long nkey;
717
718 if (!mm_use_skey(mm) || pte_val(entry) & _PAGE_INVALID)
719 return;
720 VM_BUG_ON(!(pte_val(*ptep) & _PAGE_INVALID));
721 address = pte_val(entry) & PAGE_MASK;
722 /*
723 * Set page access key and fetch protection bit from pgste.
724 * The guest C/R information is still in the PGSTE, set real
725 * key C/R to 0.
726 */
727 nkey = (pgste_val(pgste) & (PGSTE_ACC_BITS | PGSTE_FP_BIT)) >> 56;
728 nkey |= (pgste_val(pgste) & (PGSTE_GR_BIT | PGSTE_GC_BIT)) >> 48;
729 page_set_storage_key(address, nkey, 0);
730 #endif
731 }
732
733 static inline pgste_t pgste_set_pte(pte_t *ptep, pgste_t pgste, pte_t entry)
734 {
735 if ((pte_val(entry) & _PAGE_PRESENT) &&
736 (pte_val(entry) & _PAGE_WRITE) &&
737 !(pte_val(entry) & _PAGE_INVALID)) {
738 if (!MACHINE_HAS_ESOP) {
739 /*
740 * Without enhanced suppression-on-protection force
741 * the dirty bit on for all writable ptes.
742 */
743 pte_val(entry) |= _PAGE_DIRTY;
744 pte_val(entry) &= ~_PAGE_PROTECT;
745 }
746 if (!(pte_val(entry) & _PAGE_PROTECT))
747 /* This pte allows write access, set user-dirty */
748 pgste_val(pgste) |= PGSTE_UC_BIT;
749 }
750 *ptep = entry;
751 return pgste;
752 }
753
754 /**
755 * struct gmap_struct - guest address space
756 * @crst_list: list of all crst tables used in the guest address space
757 * @mm: pointer to the parent mm_struct
758 * @guest_to_host: radix tree with guest to host address translation
759 * @host_to_guest: radix tree with pointer to segment table entries
760 * @guest_table_lock: spinlock to protect all entries in the guest page table
761 * @table: pointer to the page directory
762 * @asce: address space control element for gmap page table
763 * @pfault_enabled: defines if pfaults are applicable for the guest
764 */
765 struct gmap {
766 struct list_head list;
767 struct list_head crst_list;
768 struct mm_struct *mm;
769 struct radix_tree_root guest_to_host;
770 struct radix_tree_root host_to_guest;
771 spinlock_t guest_table_lock;
772 unsigned long *table;
773 unsigned long asce;
774 unsigned long asce_end;
775 void *private;
776 bool pfault_enabled;
777 };
778
779 /**
780 * struct gmap_notifier - notify function block for page invalidation
781 * @notifier_call: address of callback function
782 */
783 struct gmap_notifier {
784 struct list_head list;
785 void (*notifier_call)(struct gmap *gmap, unsigned long gaddr);
786 };
787
788 struct gmap *gmap_alloc(struct mm_struct *mm, unsigned long limit);
789 void gmap_free(struct gmap *gmap);
790 void gmap_enable(struct gmap *gmap);
791 void gmap_disable(struct gmap *gmap);
792 int gmap_map_segment(struct gmap *gmap, unsigned long from,
793 unsigned long to, unsigned long len);
794 int gmap_unmap_segment(struct gmap *gmap, unsigned long to, unsigned long len);
795 unsigned long __gmap_translate(struct gmap *, unsigned long gaddr);
796 unsigned long gmap_translate(struct gmap *, unsigned long gaddr);
797 int __gmap_link(struct gmap *gmap, unsigned long gaddr, unsigned long vmaddr);
798 int gmap_fault(struct gmap *, unsigned long gaddr, unsigned int fault_flags);
799 void gmap_discard(struct gmap *, unsigned long from, unsigned long to);
800 void __gmap_zap(struct gmap *, unsigned long gaddr);
801 bool gmap_test_and_clear_dirty(unsigned long address, struct gmap *);
802
803
804 void gmap_register_ipte_notifier(struct gmap_notifier *);
805 void gmap_unregister_ipte_notifier(struct gmap_notifier *);
806 int gmap_ipte_notify(struct gmap *, unsigned long start, unsigned long len);
807 void gmap_do_ipte_notify(struct mm_struct *, unsigned long addr, pte_t *);
808
809 static inline pgste_t pgste_ipte_notify(struct mm_struct *mm,
810 unsigned long addr,
811 pte_t *ptep, pgste_t pgste)
812 {
813 #ifdef CONFIG_PGSTE
814 if (pgste_val(pgste) & PGSTE_IN_BIT) {
815 pgste_val(pgste) &= ~PGSTE_IN_BIT;
816 gmap_do_ipte_notify(mm, addr, ptep);
817 }
818 #endif
819 return pgste;
820 }
821
822 /*
823 * Certain architectures need to do special things when PTEs
824 * within a page table are directly modified. Thus, the following
825 * hook is made available.
826 */
827 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
828 pte_t *ptep, pte_t entry)
829 {
830 pgste_t pgste;
831
832 if (mm_has_pgste(mm)) {
833 pgste = pgste_get_lock(ptep);
834 pgste_val(pgste) &= ~_PGSTE_GPS_ZERO;
835 pgste_set_key(ptep, pgste, entry, mm);
836 pgste = pgste_set_pte(ptep, pgste, entry);
837 pgste_set_unlock(ptep, pgste);
838 } else {
839 *ptep = entry;
840 }
841 }
842
843 /*
844 * query functions pte_write/pte_dirty/pte_young only work if
845 * pte_present() is true. Undefined behaviour if not..
846 */
847 static inline int pte_write(pte_t pte)
848 {
849 return (pte_val(pte) & _PAGE_WRITE) != 0;
850 }
851
852 static inline int pte_dirty(pte_t pte)
853 {
854 return (pte_val(pte) & _PAGE_DIRTY) != 0;
855 }
856
857 static inline int pte_young(pte_t pte)
858 {
859 return (pte_val(pte) & _PAGE_YOUNG) != 0;
860 }
861
862 #define __HAVE_ARCH_PTE_UNUSED
863 static inline int pte_unused(pte_t pte)
864 {
865 return pte_val(pte) & _PAGE_UNUSED;
866 }
867
868 /*
869 * pgd/pmd/pte modification functions
870 */
871
872 static inline void pgd_clear(pgd_t *pgd)
873 {
874 if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2)
875 pgd_val(*pgd) = _REGION2_ENTRY_EMPTY;
876 }
877
878 static inline void pud_clear(pud_t *pud)
879 {
880 if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3)
881 pud_val(*pud) = _REGION3_ENTRY_EMPTY;
882 }
883
884 static inline void pmd_clear(pmd_t *pmdp)
885 {
886 pmd_val(*pmdp) = _SEGMENT_ENTRY_INVALID;
887 }
888
889 static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
890 {
891 pte_val(*ptep) = _PAGE_INVALID;
892 }
893
894 /*
895 * The following pte modification functions only work if
896 * pte_present() is true. Undefined behaviour if not..
897 */
898 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
899 {
900 pte_val(pte) &= _PAGE_CHG_MASK;
901 pte_val(pte) |= pgprot_val(newprot);
902 /*
903 * newprot for PAGE_NONE, PAGE_READ and PAGE_WRITE has the
904 * invalid bit set, clear it again for readable, young pages
905 */
906 if ((pte_val(pte) & _PAGE_YOUNG) && (pte_val(pte) & _PAGE_READ))
907 pte_val(pte) &= ~_PAGE_INVALID;
908 /*
909 * newprot for PAGE_READ and PAGE_WRITE has the page protection
910 * bit set, clear it again for writable, dirty pages
911 */
912 if ((pte_val(pte) & _PAGE_DIRTY) && (pte_val(pte) & _PAGE_WRITE))
913 pte_val(pte) &= ~_PAGE_PROTECT;
914 return pte;
915 }
916
917 static inline pte_t pte_wrprotect(pte_t pte)
918 {
919 pte_val(pte) &= ~_PAGE_WRITE;
920 pte_val(pte) |= _PAGE_PROTECT;
921 return pte;
922 }
923
924 static inline pte_t pte_mkwrite(pte_t pte)
925 {
926 pte_val(pte) |= _PAGE_WRITE;
927 if (pte_val(pte) & _PAGE_DIRTY)
928 pte_val(pte) &= ~_PAGE_PROTECT;
929 return pte;
930 }
931
932 static inline pte_t pte_mkclean(pte_t pte)
933 {
934 pte_val(pte) &= ~_PAGE_DIRTY;
935 pte_val(pte) |= _PAGE_PROTECT;
936 return pte;
937 }
938
939 static inline pte_t pte_mkdirty(pte_t pte)
940 {
941 pte_val(pte) |= _PAGE_DIRTY | _PAGE_SOFT_DIRTY;
942 if (pte_val(pte) & _PAGE_WRITE)
943 pte_val(pte) &= ~_PAGE_PROTECT;
944 return pte;
945 }
946
947 static inline pte_t pte_mkold(pte_t pte)
948 {
949 pte_val(pte) &= ~_PAGE_YOUNG;
950 pte_val(pte) |= _PAGE_INVALID;
951 return pte;
952 }
953
954 static inline pte_t pte_mkyoung(pte_t pte)
955 {
956 pte_val(pte) |= _PAGE_YOUNG;
957 if (pte_val(pte) & _PAGE_READ)
958 pte_val(pte) &= ~_PAGE_INVALID;
959 return pte;
960 }
961
962 static inline pte_t pte_mkspecial(pte_t pte)
963 {
964 pte_val(pte) |= _PAGE_SPECIAL;
965 return pte;
966 }
967
968 #ifdef CONFIG_HUGETLB_PAGE
969 static inline pte_t pte_mkhuge(pte_t pte)
970 {
971 pte_val(pte) |= _PAGE_LARGE;
972 return pte;
973 }
974 #endif
975
976 static inline void __ptep_ipte(unsigned long address, pte_t *ptep)
977 {
978 unsigned long pto = (unsigned long) ptep;
979
980 /* Invalidation + global TLB flush for the pte */
981 asm volatile(
982 " ipte %2,%3"
983 : "=m" (*ptep) : "m" (*ptep), "a" (pto), "a" (address));
984 }
985
986 static inline void __ptep_ipte_local(unsigned long address, pte_t *ptep)
987 {
988 unsigned long pto = (unsigned long) ptep;
989
990 /* Invalidation + local TLB flush for the pte */
991 asm volatile(
992 " .insn rrf,0xb2210000,%2,%3,0,1"
993 : "=m" (*ptep) : "m" (*ptep), "a" (pto), "a" (address));
994 }
995
996 static inline void __ptep_ipte_range(unsigned long address, int nr, pte_t *ptep)
997 {
998 unsigned long pto = (unsigned long) ptep;
999
1000 /* Invalidate a range of ptes + global TLB flush of the ptes */
1001 do {
1002 asm volatile(
1003 " .insn rrf,0xb2210000,%2,%0,%1,0"
1004 : "+a" (address), "+a" (nr) : "a" (pto) : "memory");
1005 } while (nr != 255);
1006 }
1007
1008 static inline void ptep_flush_direct(struct mm_struct *mm,
1009 unsigned long address, pte_t *ptep)
1010 {
1011 int active, count;
1012
1013 if (pte_val(*ptep) & _PAGE_INVALID)
1014 return;
1015 active = (mm == current->active_mm) ? 1 : 0;
1016 count = atomic_add_return(0x10000, &mm->context.attach_count);
1017 if (MACHINE_HAS_TLB_LC && (count & 0xffff) <= active &&
1018 cpumask_equal(mm_cpumask(mm), cpumask_of(smp_processor_id())))
1019 __ptep_ipte_local(address, ptep);
1020 else
1021 __ptep_ipte(address, ptep);
1022 atomic_sub(0x10000, &mm->context.attach_count);
1023 }
1024
1025 static inline void ptep_flush_lazy(struct mm_struct *mm,
1026 unsigned long address, pte_t *ptep)
1027 {
1028 int active, count;
1029
1030 if (pte_val(*ptep) & _PAGE_INVALID)
1031 return;
1032 active = (mm == current->active_mm) ? 1 : 0;
1033 count = atomic_add_return(0x10000, &mm->context.attach_count);
1034 if ((count & 0xffff) <= active) {
1035 pte_val(*ptep) |= _PAGE_INVALID;
1036 mm->context.flush_mm = 1;
1037 } else
1038 __ptep_ipte(address, ptep);
1039 atomic_sub(0x10000, &mm->context.attach_count);
1040 }
1041
1042 /*
1043 * Get (and clear) the user dirty bit for a pte.
1044 */
1045 static inline int ptep_test_and_clear_user_dirty(struct mm_struct *mm,
1046 unsigned long addr,
1047 pte_t *ptep)
1048 {
1049 pgste_t pgste;
1050 pte_t pte;
1051 int dirty;
1052
1053 if (!mm_has_pgste(mm))
1054 return 0;
1055 pgste = pgste_get_lock(ptep);
1056 dirty = !!(pgste_val(pgste) & PGSTE_UC_BIT);
1057 pgste_val(pgste) &= ~PGSTE_UC_BIT;
1058 pte = *ptep;
1059 if (dirty && (pte_val(pte) & _PAGE_PRESENT)) {
1060 pgste = pgste_ipte_notify(mm, addr, ptep, pgste);
1061 __ptep_ipte(addr, ptep);
1062 if (MACHINE_HAS_ESOP || !(pte_val(pte) & _PAGE_WRITE))
1063 pte_val(pte) |= _PAGE_PROTECT;
1064 else
1065 pte_val(pte) |= _PAGE_INVALID;
1066 *ptep = pte;
1067 }
1068 pgste_set_unlock(ptep, pgste);
1069 return dirty;
1070 }
1071
1072 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
1073 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma,
1074 unsigned long addr, pte_t *ptep)
1075 {
1076 pgste_t pgste;
1077 pte_t pte, oldpte;
1078 int young;
1079
1080 if (mm_has_pgste(vma->vm_mm)) {
1081 pgste = pgste_get_lock(ptep);
1082 pgste = pgste_ipte_notify(vma->vm_mm, addr, ptep, pgste);
1083 }
1084
1085 oldpte = pte = *ptep;
1086 ptep_flush_direct(vma->vm_mm, addr, ptep);
1087 young = pte_young(pte);
1088 pte = pte_mkold(pte);
1089
1090 if (mm_has_pgste(vma->vm_mm)) {
1091 pgste = pgste_update_all(&oldpte, pgste, vma->vm_mm);
1092 pgste = pgste_set_pte(ptep, pgste, pte);
1093 pgste_set_unlock(ptep, pgste);
1094 } else
1095 *ptep = pte;
1096
1097 return young;
1098 }
1099
1100 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
1101 static inline int ptep_clear_flush_young(struct vm_area_struct *vma,
1102 unsigned long address, pte_t *ptep)
1103 {
1104 return ptep_test_and_clear_young(vma, address, ptep);
1105 }
1106
1107 /*
1108 * This is hard to understand. ptep_get_and_clear and ptep_clear_flush
1109 * both clear the TLB for the unmapped pte. The reason is that
1110 * ptep_get_and_clear is used in common code (e.g. change_pte_range)
1111 * to modify an active pte. The sequence is
1112 * 1) ptep_get_and_clear
1113 * 2) set_pte_at
1114 * 3) flush_tlb_range
1115 * On s390 the tlb needs to get flushed with the modification of the pte
1116 * if the pte is active. The only way how this can be implemented is to
1117 * have ptep_get_and_clear do the tlb flush. In exchange flush_tlb_range
1118 * is a nop.
1119 */
1120 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
1121 static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
1122 unsigned long address, pte_t *ptep)
1123 {
1124 pgste_t pgste;
1125 pte_t pte;
1126
1127 if (mm_has_pgste(mm)) {
1128 pgste = pgste_get_lock(ptep);
1129 pgste = pgste_ipte_notify(mm, address, ptep, pgste);
1130 }
1131
1132 pte = *ptep;
1133 ptep_flush_lazy(mm, address, ptep);
1134 pte_val(*ptep) = _PAGE_INVALID;
1135
1136 if (mm_has_pgste(mm)) {
1137 pgste = pgste_update_all(&pte, pgste, mm);
1138 pgste_set_unlock(ptep, pgste);
1139 }
1140 return pte;
1141 }
1142
1143 #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION
1144 static inline pte_t ptep_modify_prot_start(struct mm_struct *mm,
1145 unsigned long address,
1146 pte_t *ptep)
1147 {
1148 pgste_t pgste;
1149 pte_t pte;
1150
1151 if (mm_has_pgste(mm)) {
1152 pgste = pgste_get_lock(ptep);
1153 pgste_ipte_notify(mm, address, ptep, pgste);
1154 }
1155
1156 pte = *ptep;
1157 ptep_flush_lazy(mm, address, ptep);
1158
1159 if (mm_has_pgste(mm)) {
1160 pgste = pgste_update_all(&pte, pgste, mm);
1161 pgste_set(ptep, pgste);
1162 }
1163 return pte;
1164 }
1165
1166 static inline void ptep_modify_prot_commit(struct mm_struct *mm,
1167 unsigned long address,
1168 pte_t *ptep, pte_t pte)
1169 {
1170 pgste_t pgste;
1171
1172 if (mm_has_pgste(mm)) {
1173 pgste = pgste_get(ptep);
1174 pgste_set_key(ptep, pgste, pte, mm);
1175 pgste = pgste_set_pte(ptep, pgste, pte);
1176 pgste_set_unlock(ptep, pgste);
1177 } else
1178 *ptep = pte;
1179 }
1180
1181 #define __HAVE_ARCH_PTEP_CLEAR_FLUSH
1182 static inline pte_t ptep_clear_flush(struct vm_area_struct *vma,
1183 unsigned long address, pte_t *ptep)
1184 {
1185 pgste_t pgste;
1186 pte_t pte;
1187
1188 if (mm_has_pgste(vma->vm_mm)) {
1189 pgste = pgste_get_lock(ptep);
1190 pgste = pgste_ipte_notify(vma->vm_mm, address, ptep, pgste);
1191 }
1192
1193 pte = *ptep;
1194 ptep_flush_direct(vma->vm_mm, address, ptep);
1195 pte_val(*ptep) = _PAGE_INVALID;
1196
1197 if (mm_has_pgste(vma->vm_mm)) {
1198 if ((pgste_val(pgste) & _PGSTE_GPS_USAGE_MASK) ==
1199 _PGSTE_GPS_USAGE_UNUSED)
1200 pte_val(pte) |= _PAGE_UNUSED;
1201 pgste = pgste_update_all(&pte, pgste, vma->vm_mm);
1202 pgste_set_unlock(ptep, pgste);
1203 }
1204 return pte;
1205 }
1206
1207 /*
1208 * The batched pte unmap code uses ptep_get_and_clear_full to clear the
1209 * ptes. Here an optimization is possible. tlb_gather_mmu flushes all
1210 * tlbs of an mm if it can guarantee that the ptes of the mm_struct
1211 * cannot be accessed while the batched unmap is running. In this case
1212 * full==1 and a simple pte_clear is enough. See tlb.h.
1213 */
1214 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL
1215 static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm,
1216 unsigned long address,
1217 pte_t *ptep, int full)
1218 {
1219 pgste_t pgste;
1220 pte_t pte;
1221
1222 if (!full && mm_has_pgste(mm)) {
1223 pgste = pgste_get_lock(ptep);
1224 pgste = pgste_ipte_notify(mm, address, ptep, pgste);
1225 }
1226
1227 pte = *ptep;
1228 if (!full)
1229 ptep_flush_lazy(mm, address, ptep);
1230 pte_val(*ptep) = _PAGE_INVALID;
1231
1232 if (!full && mm_has_pgste(mm)) {
1233 pgste = pgste_update_all(&pte, pgste, mm);
1234 pgste_set_unlock(ptep, pgste);
1235 }
1236 return pte;
1237 }
1238
1239 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
1240 static inline pte_t ptep_set_wrprotect(struct mm_struct *mm,
1241 unsigned long address, pte_t *ptep)
1242 {
1243 pgste_t pgste;
1244 pte_t pte = *ptep;
1245
1246 if (pte_write(pte)) {
1247 if (mm_has_pgste(mm)) {
1248 pgste = pgste_get_lock(ptep);
1249 pgste = pgste_ipte_notify(mm, address, ptep, pgste);
1250 }
1251
1252 ptep_flush_lazy(mm, address, ptep);
1253 pte = pte_wrprotect(pte);
1254
1255 if (mm_has_pgste(mm)) {
1256 pgste = pgste_set_pte(ptep, pgste, pte);
1257 pgste_set_unlock(ptep, pgste);
1258 } else
1259 *ptep = pte;
1260 }
1261 return pte;
1262 }
1263
1264 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
1265 static inline int ptep_set_access_flags(struct vm_area_struct *vma,
1266 unsigned long address, pte_t *ptep,
1267 pte_t entry, int dirty)
1268 {
1269 pgste_t pgste;
1270 pte_t oldpte;
1271
1272 oldpte = *ptep;
1273 if (pte_same(oldpte, entry))
1274 return 0;
1275 if (mm_has_pgste(vma->vm_mm)) {
1276 pgste = pgste_get_lock(ptep);
1277 pgste = pgste_ipte_notify(vma->vm_mm, address, ptep, pgste);
1278 }
1279
1280 ptep_flush_direct(vma->vm_mm, address, ptep);
1281
1282 if (mm_has_pgste(vma->vm_mm)) {
1283 if (pte_val(oldpte) & _PAGE_INVALID)
1284 pgste_set_key(ptep, pgste, entry, vma->vm_mm);
1285 pgste = pgste_set_pte(ptep, pgste, entry);
1286 pgste_set_unlock(ptep, pgste);
1287 } else
1288 *ptep = entry;
1289 return 1;
1290 }
1291
1292 /*
1293 * Conversion functions: convert a page and protection to a page entry,
1294 * and a page entry and page directory to the page they refer to.
1295 */
1296 static inline pte_t mk_pte_phys(unsigned long physpage, pgprot_t pgprot)
1297 {
1298 pte_t __pte;
1299 pte_val(__pte) = physpage + pgprot_val(pgprot);
1300 return pte_mkyoung(__pte);
1301 }
1302
1303 static inline pte_t mk_pte(struct page *page, pgprot_t pgprot)
1304 {
1305 unsigned long physpage = page_to_phys(page);
1306 pte_t __pte = mk_pte_phys(physpage, pgprot);
1307
1308 if (pte_write(__pte) && PageDirty(page))
1309 __pte = pte_mkdirty(__pte);
1310 return __pte;
1311 }
1312
1313 #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
1314 #define pud_index(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
1315 #define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
1316 #define pte_index(address) (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE-1))
1317
1318 #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
1319 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
1320
1321 #define pmd_deref(pmd) (pmd_val(pmd) & _SEGMENT_ENTRY_ORIGIN)
1322 #define pud_deref(pud) (pud_val(pud) & _REGION_ENTRY_ORIGIN)
1323 #define pgd_deref(pgd) (pgd_val(pgd) & _REGION_ENTRY_ORIGIN)
1324
1325 static inline pud_t *pud_offset(pgd_t *pgd, unsigned long address)
1326 {
1327 pud_t *pud = (pud_t *) pgd;
1328 if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2)
1329 pud = (pud_t *) pgd_deref(*pgd);
1330 return pud + pud_index(address);
1331 }
1332
1333 static inline pmd_t *pmd_offset(pud_t *pud, unsigned long address)
1334 {
1335 pmd_t *pmd = (pmd_t *) pud;
1336 if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3)
1337 pmd = (pmd_t *) pud_deref(*pud);
1338 return pmd + pmd_index(address);
1339 }
1340
1341 #define pfn_pte(pfn,pgprot) mk_pte_phys(__pa((pfn) << PAGE_SHIFT),(pgprot))
1342 #define pte_pfn(x) (pte_val(x) >> PAGE_SHIFT)
1343 #define pte_page(x) pfn_to_page(pte_pfn(x))
1344
1345 #define pmd_page(pmd) pfn_to_page(pmd_pfn(pmd))
1346
1347 /* Find an entry in the lowest level page table.. */
1348 #define pte_offset(pmd, addr) ((pte_t *) pmd_deref(*(pmd)) + pte_index(addr))
1349 #define pte_offset_kernel(pmd, address) pte_offset(pmd,address)
1350 #define pte_offset_map(pmd, address) pte_offset_kernel(pmd, address)
1351 #define pte_unmap(pte) do { } while (0)
1352
1353 #if defined(CONFIG_TRANSPARENT_HUGEPAGE) || defined(CONFIG_HUGETLB_PAGE)
1354 static inline unsigned long massage_pgprot_pmd(pgprot_t pgprot)
1355 {
1356 /*
1357 * pgprot is PAGE_NONE, PAGE_READ, or PAGE_WRITE (see __Pxxx / __Sxxx)
1358 * Convert to segment table entry format.
1359 */
1360 if (pgprot_val(pgprot) == pgprot_val(PAGE_NONE))
1361 return pgprot_val(SEGMENT_NONE);
1362 if (pgprot_val(pgprot) == pgprot_val(PAGE_READ))
1363 return pgprot_val(SEGMENT_READ);
1364 return pgprot_val(SEGMENT_WRITE);
1365 }
1366
1367 static inline pmd_t pmd_wrprotect(pmd_t pmd)
1368 {
1369 pmd_val(pmd) &= ~_SEGMENT_ENTRY_WRITE;
1370 pmd_val(pmd) |= _SEGMENT_ENTRY_PROTECT;
1371 return pmd;
1372 }
1373
1374 static inline pmd_t pmd_mkwrite(pmd_t pmd)
1375 {
1376 pmd_val(pmd) |= _SEGMENT_ENTRY_WRITE;
1377 if (pmd_large(pmd) && !(pmd_val(pmd) & _SEGMENT_ENTRY_DIRTY))
1378 return pmd;
1379 pmd_val(pmd) &= ~_SEGMENT_ENTRY_PROTECT;
1380 return pmd;
1381 }
1382
1383 static inline pmd_t pmd_mkclean(pmd_t pmd)
1384 {
1385 if (pmd_large(pmd)) {
1386 pmd_val(pmd) &= ~_SEGMENT_ENTRY_DIRTY;
1387 pmd_val(pmd) |= _SEGMENT_ENTRY_PROTECT;
1388 }
1389 return pmd;
1390 }
1391
1392 static inline pmd_t pmd_mkdirty(pmd_t pmd)
1393 {
1394 if (pmd_large(pmd)) {
1395 pmd_val(pmd) |= _SEGMENT_ENTRY_DIRTY |
1396 _SEGMENT_ENTRY_SOFT_DIRTY;
1397 if (pmd_val(pmd) & _SEGMENT_ENTRY_WRITE)
1398 pmd_val(pmd) &= ~_SEGMENT_ENTRY_PROTECT;
1399 }
1400 return pmd;
1401 }
1402
1403 static inline pmd_t pmd_mkyoung(pmd_t pmd)
1404 {
1405 if (pmd_large(pmd)) {
1406 pmd_val(pmd) |= _SEGMENT_ENTRY_YOUNG;
1407 if (pmd_val(pmd) & _SEGMENT_ENTRY_READ)
1408 pmd_val(pmd) &= ~_SEGMENT_ENTRY_INVALID;
1409 }
1410 return pmd;
1411 }
1412
1413 static inline pmd_t pmd_mkold(pmd_t pmd)
1414 {
1415 if (pmd_large(pmd)) {
1416 pmd_val(pmd) &= ~_SEGMENT_ENTRY_YOUNG;
1417 pmd_val(pmd) |= _SEGMENT_ENTRY_INVALID;
1418 }
1419 return pmd;
1420 }
1421
1422 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
1423 {
1424 if (pmd_large(pmd)) {
1425 pmd_val(pmd) &= _SEGMENT_ENTRY_ORIGIN_LARGE |
1426 _SEGMENT_ENTRY_DIRTY | _SEGMENT_ENTRY_YOUNG |
1427 _SEGMENT_ENTRY_LARGE | _SEGMENT_ENTRY_SPLIT |
1428 _SEGMENT_ENTRY_SOFT_DIRTY;
1429 pmd_val(pmd) |= massage_pgprot_pmd(newprot);
1430 if (!(pmd_val(pmd) & _SEGMENT_ENTRY_DIRTY))
1431 pmd_val(pmd) |= _SEGMENT_ENTRY_PROTECT;
1432 if (!(pmd_val(pmd) & _SEGMENT_ENTRY_YOUNG))
1433 pmd_val(pmd) |= _SEGMENT_ENTRY_INVALID;
1434 return pmd;
1435 }
1436 pmd_val(pmd) &= _SEGMENT_ENTRY_ORIGIN;
1437 pmd_val(pmd) |= massage_pgprot_pmd(newprot);
1438 return pmd;
1439 }
1440
1441 static inline pmd_t mk_pmd_phys(unsigned long physpage, pgprot_t pgprot)
1442 {
1443 pmd_t __pmd;
1444 pmd_val(__pmd) = physpage + massage_pgprot_pmd(pgprot);
1445 return __pmd;
1446 }
1447
1448 #endif /* CONFIG_TRANSPARENT_HUGEPAGE || CONFIG_HUGETLB_PAGE */
1449
1450 static inline void __pmdp_csp(pmd_t *pmdp)
1451 {
1452 register unsigned long reg2 asm("2") = pmd_val(*pmdp);
1453 register unsigned long reg3 asm("3") = pmd_val(*pmdp) |
1454 _SEGMENT_ENTRY_INVALID;
1455 register unsigned long reg4 asm("4") = ((unsigned long) pmdp) + 5;
1456
1457 asm volatile(
1458 " csp %1,%3"
1459 : "=m" (*pmdp)
1460 : "d" (reg2), "d" (reg3), "d" (reg4), "m" (*pmdp) : "cc");
1461 }
1462
1463 static inline void __pmdp_idte(unsigned long address, pmd_t *pmdp)
1464 {
1465 unsigned long sto;
1466
1467 sto = (unsigned long) pmdp - pmd_index(address) * sizeof(pmd_t);
1468 asm volatile(
1469 " .insn rrf,0xb98e0000,%2,%3,0,0"
1470 : "=m" (*pmdp)
1471 : "m" (*pmdp), "a" (sto), "a" ((address & HPAGE_MASK))
1472 : "cc" );
1473 }
1474
1475 static inline void __pmdp_idte_local(unsigned long address, pmd_t *pmdp)
1476 {
1477 unsigned long sto;
1478
1479 sto = (unsigned long) pmdp - pmd_index(address) * sizeof(pmd_t);
1480 asm volatile(
1481 " .insn rrf,0xb98e0000,%2,%3,0,1"
1482 : "=m" (*pmdp)
1483 : "m" (*pmdp), "a" (sto), "a" ((address & HPAGE_MASK))
1484 : "cc" );
1485 }
1486
1487 static inline void pmdp_flush_direct(struct mm_struct *mm,
1488 unsigned long address, pmd_t *pmdp)
1489 {
1490 int active, count;
1491
1492 if (pmd_val(*pmdp) & _SEGMENT_ENTRY_INVALID)
1493 return;
1494 if (!MACHINE_HAS_IDTE) {
1495 __pmdp_csp(pmdp);
1496 return;
1497 }
1498 active = (mm == current->active_mm) ? 1 : 0;
1499 count = atomic_add_return(0x10000, &mm->context.attach_count);
1500 if (MACHINE_HAS_TLB_LC && (count & 0xffff) <= active &&
1501 cpumask_equal(mm_cpumask(mm), cpumask_of(smp_processor_id())))
1502 __pmdp_idte_local(address, pmdp);
1503 else
1504 __pmdp_idte(address, pmdp);
1505 atomic_sub(0x10000, &mm->context.attach_count);
1506 }
1507
1508 static inline void pmdp_flush_lazy(struct mm_struct *mm,
1509 unsigned long address, pmd_t *pmdp)
1510 {
1511 int active, count;
1512
1513 if (pmd_val(*pmdp) & _SEGMENT_ENTRY_INVALID)
1514 return;
1515 active = (mm == current->active_mm) ? 1 : 0;
1516 count = atomic_add_return(0x10000, &mm->context.attach_count);
1517 if ((count & 0xffff) <= active) {
1518 pmd_val(*pmdp) |= _SEGMENT_ENTRY_INVALID;
1519 mm->context.flush_mm = 1;
1520 } else if (MACHINE_HAS_IDTE)
1521 __pmdp_idte(address, pmdp);
1522 else
1523 __pmdp_csp(pmdp);
1524 atomic_sub(0x10000, &mm->context.attach_count);
1525 }
1526
1527 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
1528
1529 #define __HAVE_ARCH_PGTABLE_DEPOSIT
1530 extern void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp,
1531 pgtable_t pgtable);
1532
1533 #define __HAVE_ARCH_PGTABLE_WITHDRAW
1534 extern pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp);
1535
1536 static inline int pmd_trans_splitting(pmd_t pmd)
1537 {
1538 return (pmd_val(pmd) & _SEGMENT_ENTRY_LARGE) &&
1539 (pmd_val(pmd) & _SEGMENT_ENTRY_SPLIT);
1540 }
1541
1542 static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr,
1543 pmd_t *pmdp, pmd_t entry)
1544 {
1545 *pmdp = entry;
1546 }
1547
1548 static inline pmd_t pmd_mkhuge(pmd_t pmd)
1549 {
1550 pmd_val(pmd) |= _SEGMENT_ENTRY_LARGE;
1551 pmd_val(pmd) |= _SEGMENT_ENTRY_YOUNG;
1552 pmd_val(pmd) |= _SEGMENT_ENTRY_PROTECT;
1553 return pmd;
1554 }
1555
1556 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG
1557 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma,
1558 unsigned long address, pmd_t *pmdp)
1559 {
1560 pmd_t pmd;
1561
1562 pmd = *pmdp;
1563 pmdp_flush_direct(vma->vm_mm, address, pmdp);
1564 *pmdp = pmd_mkold(pmd);
1565 return pmd_young(pmd);
1566 }
1567
1568 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR
1569 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm,
1570 unsigned long address, pmd_t *pmdp)
1571 {
1572 pmd_t pmd = *pmdp;
1573
1574 pmdp_flush_direct(mm, address, pmdp);
1575 pmd_clear(pmdp);
1576 return pmd;
1577 }
1578
1579 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR_FULL
1580 static inline pmd_t pmdp_huge_get_and_clear_full(struct mm_struct *mm,
1581 unsigned long address,
1582 pmd_t *pmdp, int full)
1583 {
1584 pmd_t pmd = *pmdp;
1585
1586 if (!full)
1587 pmdp_flush_lazy(mm, address, pmdp);
1588 pmd_clear(pmdp);
1589 return pmd;
1590 }
1591
1592 #define __HAVE_ARCH_PMDP_HUGE_CLEAR_FLUSH
1593 static inline pmd_t pmdp_huge_clear_flush(struct vm_area_struct *vma,
1594 unsigned long address, pmd_t *pmdp)
1595 {
1596 return pmdp_huge_get_and_clear(vma->vm_mm, address, pmdp);
1597 }
1598
1599 #define __HAVE_ARCH_PMDP_INVALIDATE
1600 static inline void pmdp_invalidate(struct vm_area_struct *vma,
1601 unsigned long address, pmd_t *pmdp)
1602 {
1603 pmdp_flush_direct(vma->vm_mm, address, pmdp);
1604 }
1605
1606 #define __HAVE_ARCH_PMDP_SET_WRPROTECT
1607 static inline void pmdp_set_wrprotect(struct mm_struct *mm,
1608 unsigned long address, pmd_t *pmdp)
1609 {
1610 pmd_t pmd = *pmdp;
1611
1612 if (pmd_write(pmd)) {
1613 pmdp_flush_direct(mm, address, pmdp);
1614 set_pmd_at(mm, address, pmdp, pmd_wrprotect(pmd));
1615 }
1616 }
1617
1618 static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma,
1619 unsigned long address,
1620 pmd_t *pmdp)
1621 {
1622 return pmdp_huge_get_and_clear(vma->vm_mm, address, pmdp);
1623 }
1624 #define pmdp_collapse_flush pmdp_collapse_flush
1625
1626 #define pfn_pmd(pfn, pgprot) mk_pmd_phys(__pa((pfn) << PAGE_SHIFT), (pgprot))
1627 #define mk_pmd(page, pgprot) pfn_pmd(page_to_pfn(page), (pgprot))
1628
1629 static inline int pmd_trans_huge(pmd_t pmd)
1630 {
1631 return pmd_val(pmd) & _SEGMENT_ENTRY_LARGE;
1632 }
1633
1634 static inline int has_transparent_hugepage(void)
1635 {
1636 return MACHINE_HAS_HPAGE ? 1 : 0;
1637 }
1638 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
1639
1640 /*
1641 * 64 bit swap entry format:
1642 * A page-table entry has some bits we have to treat in a special way.
1643 * Bits 52 and bit 55 have to be zero, otherwise a specification
1644 * exception will occur instead of a page translation exception. The
1645 * specification exception has the bad habit not to store necessary
1646 * information in the lowcore.
1647 * Bits 54 and 63 are used to indicate the page type.
1648 * A swap pte is indicated by bit pattern (pte & 0x201) == 0x200
1649 * This leaves the bits 0-51 and bits 56-62 to store type and offset.
1650 * We use the 5 bits from 57-61 for the type and the 52 bits from 0-51
1651 * for the offset.
1652 * | offset |01100|type |00|
1653 * |0000000000111111111122222222223333333333444444444455|55555|55566|66|
1654 * |0123456789012345678901234567890123456789012345678901|23456|78901|23|
1655 */
1656
1657 #define __SWP_OFFSET_MASK ((1UL << 52) - 1)
1658 #define __SWP_OFFSET_SHIFT 12
1659 #define __SWP_TYPE_MASK ((1UL << 5) - 1)
1660 #define __SWP_TYPE_SHIFT 2
1661
1662 static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset)
1663 {
1664 pte_t pte;
1665
1666 pte_val(pte) = _PAGE_INVALID | _PAGE_PROTECT;
1667 pte_val(pte) |= (offset & __SWP_OFFSET_MASK) << __SWP_OFFSET_SHIFT;
1668 pte_val(pte) |= (type & __SWP_TYPE_MASK) << __SWP_TYPE_SHIFT;
1669 return pte;
1670 }
1671
1672 static inline unsigned long __swp_type(swp_entry_t entry)
1673 {
1674 return (entry.val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK;
1675 }
1676
1677 static inline unsigned long __swp_offset(swp_entry_t entry)
1678 {
1679 return (entry.val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK;
1680 }
1681
1682 static inline swp_entry_t __swp_entry(unsigned long type, unsigned long offset)
1683 {
1684 return (swp_entry_t) { pte_val(mk_swap_pte(type, offset)) };
1685 }
1686
1687 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
1688 #define __swp_entry_to_pte(x) ((pte_t) { (x).val })
1689
1690 #endif /* !__ASSEMBLY__ */
1691
1692 #define kern_addr_valid(addr) (1)
1693
1694 extern int vmem_add_mapping(unsigned long start, unsigned long size);
1695 extern int vmem_remove_mapping(unsigned long start, unsigned long size);
1696 extern int s390_enable_sie(void);
1697 extern int s390_enable_skey(void);
1698 extern void s390_reset_cmma(struct mm_struct *mm);
1699
1700 /* s390 has a private copy of get unmapped area to deal with cache synonyms */
1701 #define HAVE_ARCH_UNMAPPED_AREA
1702 #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
1703
1704 /*
1705 * No page table caches to initialise
1706 */
1707 static inline void pgtable_cache_init(void) { }
1708 static inline void check_pgt_cache(void) { }
1709
1710 #include <asm-generic/pgtable.h>
1711
1712 #endif /* _S390_PAGE_H */
Linux kernel - Deliverables
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