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s390/mm: introduce ptep_flush_lazy helper
[deliverable/linux.git] / arch / s390 / include / asm / pgtable.h
1 /*
2 * S390 version
3 * Copyright IBM Corp. 1999, 2000
4 * Author(s): Hartmut Penner (hp@de.ibm.com)
5 * Ulrich Weigand (weigand@de.ibm.com)
6 * Martin Schwidefsky (schwidefsky@de.ibm.com)
7 *
8 * Derived from "include/asm-i386/pgtable.h"
9 */
10
11 #ifndef _ASM_S390_PGTABLE_H
12 #define _ASM_S390_PGTABLE_H
13
14 /*
15 * The Linux memory management assumes a three-level page table setup. For
16 * s390 31 bit we "fold" the mid level into the top-level page table, so
17 * that we physically have the same two-level page table as the s390 mmu
18 * expects in 31 bit mode. For s390 64 bit we use three of the five levels
19 * the hardware provides (region first and region second tables are not
20 * used).
21 *
22 * The "pgd_xxx()" functions are trivial for a folded two-level
23 * setup: the pgd is never bad, and a pmd always exists (as it's folded
24 * into the pgd entry)
25 *
26 * This file contains the functions and defines necessary to modify and use
27 * the S390 page table tree.
28 */
29 #ifndef __ASSEMBLY__
30 #include <linux/sched.h>
31 #include <linux/mm_types.h>
32 #include <linux/page-flags.h>
33 #include <asm/bug.h>
34 #include <asm/page.h>
35
36 extern pgd_t swapper_pg_dir[] __attribute__ ((aligned (4096)));
37 extern void paging_init(void);
38 extern void vmem_map_init(void);
39
40 /*
41 * The S390 doesn't have any external MMU info: the kernel page
42 * tables contain all the necessary information.
43 */
44 #define update_mmu_cache(vma, address, ptep) do { } while (0)
45 #define update_mmu_cache_pmd(vma, address, ptep) do { } while (0)
46
47 /*
48 * ZERO_PAGE is a global shared page that is always zero; used
49 * for zero-mapped memory areas etc..
50 */
51
52 extern unsigned long empty_zero_page;
53 extern unsigned long zero_page_mask;
54
55 #define ZERO_PAGE(vaddr) \
56 (virt_to_page((void *)(empty_zero_page + \
57 (((unsigned long)(vaddr)) &zero_page_mask))))
58 #define __HAVE_COLOR_ZERO_PAGE
59
60 /* TODO: s390 cannot support io_remap_pfn_range... */
61 #endif /* !__ASSEMBLY__ */
62
63 /*
64 * PMD_SHIFT determines the size of the area a second-level page
65 * table can map
66 * PGDIR_SHIFT determines what a third-level page table entry can map
67 */
68 #ifndef CONFIG_64BIT
69 # define PMD_SHIFT 20
70 # define PUD_SHIFT 20
71 # define PGDIR_SHIFT 20
72 #else /* CONFIG_64BIT */
73 # define PMD_SHIFT 20
74 # define PUD_SHIFT 31
75 # define PGDIR_SHIFT 42
76 #endif /* CONFIG_64BIT */
77
78 #define PMD_SIZE (1UL << PMD_SHIFT)
79 #define PMD_MASK (~(PMD_SIZE-1))
80 #define PUD_SIZE (1UL << PUD_SHIFT)
81 #define PUD_MASK (~(PUD_SIZE-1))
82 #define PGDIR_SIZE (1UL << PGDIR_SHIFT)
83 #define PGDIR_MASK (~(PGDIR_SIZE-1))
84
85 /*
86 * entries per page directory level: the S390 is two-level, so
87 * we don't really have any PMD directory physically.
88 * for S390 segment-table entries are combined to one PGD
89 * that leads to 1024 pte per pgd
90 */
91 #define PTRS_PER_PTE 256
92 #ifndef CONFIG_64BIT
93 #define PTRS_PER_PMD 1
94 #define PTRS_PER_PUD 1
95 #else /* CONFIG_64BIT */
96 #define PTRS_PER_PMD 2048
97 #define PTRS_PER_PUD 2048
98 #endif /* CONFIG_64BIT */
99 #define PTRS_PER_PGD 2048
100
101 #define FIRST_USER_ADDRESS 0
102
103 #define pte_ERROR(e) \
104 printk("%s:%d: bad pte %p.\n", __FILE__, __LINE__, (void *) pte_val(e))
105 #define pmd_ERROR(e) \
106 printk("%s:%d: bad pmd %p.\n", __FILE__, __LINE__, (void *) pmd_val(e))
107 #define pud_ERROR(e) \
108 printk("%s:%d: bad pud %p.\n", __FILE__, __LINE__, (void *) pud_val(e))
109 #define pgd_ERROR(e) \
110 printk("%s:%d: bad pgd %p.\n", __FILE__, __LINE__, (void *) pgd_val(e))
111
112 #ifndef __ASSEMBLY__
113 /*
114 * The vmalloc and module area will always be on the topmost area of the kernel
115 * mapping. We reserve 96MB (31bit) / 128GB (64bit) for vmalloc and modules.
116 * On 64 bit kernels we have a 2GB area at the top of the vmalloc area where
117 * modules will reside. That makes sure that inter module branches always
118 * happen without trampolines and in addition the placement within a 2GB frame
119 * is branch prediction unit friendly.
120 */
121 extern unsigned long VMALLOC_START;
122 extern unsigned long VMALLOC_END;
123 extern struct page *vmemmap;
124
125 #define VMEM_MAX_PHYS ((unsigned long) vmemmap)
126
127 #ifdef CONFIG_64BIT
128 extern unsigned long MODULES_VADDR;
129 extern unsigned long MODULES_END;
130 #define MODULES_VADDR MODULES_VADDR
131 #define MODULES_END MODULES_END
132 #define MODULES_LEN (1UL << 31)
133 #endif
134
135 /*
136 * A 31 bit pagetable entry of S390 has following format:
137 * | PFRA | | OS |
138 * 0 0IP0
139 * 00000000001111111111222222222233
140 * 01234567890123456789012345678901
141 *
142 * I Page-Invalid Bit: Page is not available for address-translation
143 * P Page-Protection Bit: Store access not possible for page
144 *
145 * A 31 bit segmenttable entry of S390 has following format:
146 * | P-table origin | |PTL
147 * 0 IC
148 * 00000000001111111111222222222233
149 * 01234567890123456789012345678901
150 *
151 * I Segment-Invalid Bit: Segment is not available for address-translation
152 * C Common-Segment Bit: Segment is not private (PoP 3-30)
153 * PTL Page-Table-Length: Page-table length (PTL+1*16 entries -> up to 256)
154 *
155 * The 31 bit segmenttable origin of S390 has following format:
156 *
157 * |S-table origin | | STL |
158 * X **GPS
159 * 00000000001111111111222222222233
160 * 01234567890123456789012345678901
161 *
162 * X Space-Switch event:
163 * G Segment-Invalid Bit: *
164 * P Private-Space Bit: Segment is not private (PoP 3-30)
165 * S Storage-Alteration:
166 * STL Segment-Table-Length: Segment-table length (STL+1*16 entries -> up to 2048)
167 *
168 * A 64 bit pagetable entry of S390 has following format:
169 * | PFRA |0IPC| OS |
170 * 0000000000111111111122222222223333333333444444444455555555556666
171 * 0123456789012345678901234567890123456789012345678901234567890123
172 *
173 * I Page-Invalid Bit: Page is not available for address-translation
174 * P Page-Protection Bit: Store access not possible for page
175 * C Change-bit override: HW is not required to set change bit
176 *
177 * A 64 bit segmenttable entry of S390 has following format:
178 * | P-table origin | TT
179 * 0000000000111111111122222222223333333333444444444455555555556666
180 * 0123456789012345678901234567890123456789012345678901234567890123
181 *
182 * I Segment-Invalid Bit: Segment is not available for address-translation
183 * C Common-Segment Bit: Segment is not private (PoP 3-30)
184 * P Page-Protection Bit: Store access not possible for page
185 * TT Type 00
186 *
187 * A 64 bit region table entry of S390 has following format:
188 * | S-table origin | TF TTTL
189 * 0000000000111111111122222222223333333333444444444455555555556666
190 * 0123456789012345678901234567890123456789012345678901234567890123
191 *
192 * I Segment-Invalid Bit: Segment is not available for address-translation
193 * TT Type 01
194 * TF
195 * TL Table length
196 *
197 * The 64 bit regiontable origin of S390 has following format:
198 * | region table origon | DTTL
199 * 0000000000111111111122222222223333333333444444444455555555556666
200 * 0123456789012345678901234567890123456789012345678901234567890123
201 *
202 * X Space-Switch event:
203 * G Segment-Invalid Bit:
204 * P Private-Space Bit:
205 * S Storage-Alteration:
206 * R Real space
207 * TL Table-Length:
208 *
209 * A storage key has the following format:
210 * | ACC |F|R|C|0|
211 * 0 3 4 5 6 7
212 * ACC: access key
213 * F : fetch protection bit
214 * R : referenced bit
215 * C : changed bit
216 */
217
218 /* Hardware bits in the page table entry */
219 #define _PAGE_CO 0x100 /* HW Change-bit override */
220 #define _PAGE_PROTECT 0x200 /* HW read-only bit */
221 #define _PAGE_INVALID 0x400 /* HW invalid bit */
222 #define _PAGE_LARGE 0x800 /* Bit to mark a large pte */
223
224 /* Software bits in the page table entry */
225 #define _PAGE_PRESENT 0x001 /* SW pte present bit */
226 #define _PAGE_TYPE 0x002 /* SW pte type bit */
227 #define _PAGE_YOUNG 0x004 /* SW pte young bit */
228 #define _PAGE_DIRTY 0x008 /* SW pte dirty bit */
229 #define _PAGE_WRITE 0x010 /* SW pte write bit */
230 #define _PAGE_SPECIAL 0x020 /* SW associated with special page */
231 #define __HAVE_ARCH_PTE_SPECIAL
232
233 /* Set of bits not changed in pte_modify */
234 #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_SPECIAL | _PAGE_CO | \
235 _PAGE_DIRTY | _PAGE_YOUNG)
236
237 /*
238 * handle_pte_fault uses pte_present, pte_none and pte_file to find out the
239 * pte type WITHOUT holding the page table lock. The _PAGE_PRESENT bit
240 * is used to distinguish present from not-present ptes. It is changed only
241 * with the page table lock held.
242 *
243 * The following table gives the different possible bit combinations for
244 * the pte hardware and software bits in the last 12 bits of a pte:
245 *
246 * 842100000000
247 * 000084210000
248 * 000000008421
249 * .IR....wdytp
250 * empty .10....00000
251 * swap .10....xxx10
252 * file .11....xxxx0
253 * prot-none, clean .11....00x01
254 * prot-none, dirty .10....01x01
255 * read-only, clean .01....00x01
256 * read-only, dirty .01....01x01
257 * read-write, clean .01....10x01
258 * read-write, dirty .00....11x01
259 *
260 * pte_present is true for the bit pattern .xx...xxxxx1, (pte & 0x001) == 0x001
261 * pte_none is true for the bit pattern .10...xxxx00, (pte & 0x603) == 0x400
262 * pte_file is true for the bit pattern .11...xxxxx0, (pte & 0x601) == 0x600
263 * pte_swap is true for the bit pattern .10...xxxx10, (pte & 0x603) == 0x402
264 */
265
266 #ifndef CONFIG_64BIT
267
268 /* Bits in the segment table address-space-control-element */
269 #define _ASCE_SPACE_SWITCH 0x80000000UL /* space switch event */
270 #define _ASCE_ORIGIN_MASK 0x7ffff000UL /* segment table origin */
271 #define _ASCE_PRIVATE_SPACE 0x100 /* private space control */
272 #define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */
273 #define _ASCE_TABLE_LENGTH 0x7f /* 128 x 64 entries = 8k */
274
275 /* Bits in the segment table entry */
276 #define _SEGMENT_ENTRY_ORIGIN 0x7fffffc0UL /* page table origin */
277 #define _SEGMENT_ENTRY_PROTECT 0x200 /* page protection bit */
278 #define _SEGMENT_ENTRY_INVALID 0x20 /* invalid segment table entry */
279 #define _SEGMENT_ENTRY_COMMON 0x10 /* common segment bit */
280 #define _SEGMENT_ENTRY_PTL 0x0f /* page table length */
281
282 #define _SEGMENT_ENTRY (_SEGMENT_ENTRY_PTL)
283 #define _SEGMENT_ENTRY_EMPTY (_SEGMENT_ENTRY_INVALID)
284
285 /* Page status table bits for virtualization */
286 #define PGSTE_ACC_BITS 0xf0000000UL
287 #define PGSTE_FP_BIT 0x08000000UL
288 #define PGSTE_PCL_BIT 0x00800000UL
289 #define PGSTE_HR_BIT 0x00400000UL
290 #define PGSTE_HC_BIT 0x00200000UL
291 #define PGSTE_GR_BIT 0x00040000UL
292 #define PGSTE_GC_BIT 0x00020000UL
293 #define PGSTE_UR_BIT 0x00008000UL
294 #define PGSTE_UC_BIT 0x00004000UL /* user dirty (migration) */
295 #define PGSTE_IN_BIT 0x00002000UL /* IPTE notify bit */
296
297 #else /* CONFIG_64BIT */
298
299 /* Bits in the segment/region table address-space-control-element */
300 #define _ASCE_ORIGIN ~0xfffUL/* segment table origin */
301 #define _ASCE_PRIVATE_SPACE 0x100 /* private space control */
302 #define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */
303 #define _ASCE_SPACE_SWITCH 0x40 /* space switch event */
304 #define _ASCE_REAL_SPACE 0x20 /* real space control */
305 #define _ASCE_TYPE_MASK 0x0c /* asce table type mask */
306 #define _ASCE_TYPE_REGION1 0x0c /* region first table type */
307 #define _ASCE_TYPE_REGION2 0x08 /* region second table type */
308 #define _ASCE_TYPE_REGION3 0x04 /* region third table type */
309 #define _ASCE_TYPE_SEGMENT 0x00 /* segment table type */
310 #define _ASCE_TABLE_LENGTH 0x03 /* region table length */
311
312 /* Bits in the region table entry */
313 #define _REGION_ENTRY_ORIGIN ~0xfffUL/* region/segment table origin */
314 #define _REGION_ENTRY_PROTECT 0x200 /* region protection bit */
315 #define _REGION_ENTRY_INVALID 0x20 /* invalid region table entry */
316 #define _REGION_ENTRY_TYPE_MASK 0x0c /* region/segment table type mask */
317 #define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type */
318 #define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type */
319 #define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type */
320 #define _REGION_ENTRY_LENGTH 0x03 /* region third length */
321
322 #define _REGION1_ENTRY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_LENGTH)
323 #define _REGION1_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_INVALID)
324 #define _REGION2_ENTRY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_LENGTH)
325 #define _REGION2_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_INVALID)
326 #define _REGION3_ENTRY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_LENGTH)
327 #define _REGION3_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_INVALID)
328
329 #define _REGION3_ENTRY_LARGE 0x400 /* RTTE-format control, large page */
330 #define _REGION3_ENTRY_RO 0x200 /* page protection bit */
331 #define _REGION3_ENTRY_CO 0x100 /* change-recording override */
332
333 /* Bits in the segment table entry */
334 #define _SEGMENT_ENTRY_ORIGIN_LARGE ~0xfffffUL /* large page address */
335 #define _SEGMENT_ENTRY_ORIGIN ~0x7ffUL/* segment table origin */
336 #define _SEGMENT_ENTRY_PROTECT 0x200 /* page protection bit */
337 #define _SEGMENT_ENTRY_INVALID 0x20 /* invalid segment table entry */
338
339 #define _SEGMENT_ENTRY (0)
340 #define _SEGMENT_ENTRY_EMPTY (_SEGMENT_ENTRY_INVALID)
341
342 #define _SEGMENT_ENTRY_LARGE 0x400 /* STE-format control, large page */
343 #define _SEGMENT_ENTRY_CO 0x100 /* change-recording override */
344 #define _SEGMENT_ENTRY_SPLIT 0x001 /* THP splitting bit */
345
346 #define _SEGMENT_ENTRY_SPLIT_BIT 0 /* THP splitting bit number */
347
348 /* Set of bits not changed in pmd_modify */
349 #define _SEGMENT_CHG_MASK (_SEGMENT_ENTRY_ORIGIN | _SEGMENT_ENTRY_LARGE \
350 | _SEGMENT_ENTRY_SPLIT | _SEGMENT_ENTRY_CO)
351
352 /* Page status table bits for virtualization */
353 #define PGSTE_ACC_BITS 0xf000000000000000UL
354 #define PGSTE_FP_BIT 0x0800000000000000UL
355 #define PGSTE_PCL_BIT 0x0080000000000000UL
356 #define PGSTE_HR_BIT 0x0040000000000000UL
357 #define PGSTE_HC_BIT 0x0020000000000000UL
358 #define PGSTE_GR_BIT 0x0004000000000000UL
359 #define PGSTE_GC_BIT 0x0002000000000000UL
360 #define PGSTE_UR_BIT 0x0000800000000000UL
361 #define PGSTE_UC_BIT 0x0000400000000000UL /* user dirty (migration) */
362 #define PGSTE_IN_BIT 0x0000200000000000UL /* IPTE notify bit */
363
364 #endif /* CONFIG_64BIT */
365
366 /*
367 * A user page table pointer has the space-switch-event bit, the
368 * private-space-control bit and the storage-alteration-event-control
369 * bit set. A kernel page table pointer doesn't need them.
370 */
371 #define _ASCE_USER_BITS (_ASCE_SPACE_SWITCH | _ASCE_PRIVATE_SPACE | \
372 _ASCE_ALT_EVENT)
373
374 /*
375 * Page protection definitions.
376 */
377 #define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_INVALID)
378 #define PAGE_READ __pgprot(_PAGE_PRESENT | _PAGE_PROTECT)
379 #define PAGE_WRITE __pgprot(_PAGE_PRESENT | _PAGE_WRITE | _PAGE_PROTECT)
380
381 #define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_WRITE | _PAGE_DIRTY)
382 #define PAGE_KERNEL __pgprot(_PAGE_PRESENT | _PAGE_WRITE | _PAGE_DIRTY)
383 #define PAGE_KERNEL_RO __pgprot(_PAGE_PRESENT | _PAGE_PROTECT)
384
385 /*
386 * On s390 the page table entry has an invalid bit and a read-only bit.
387 * Read permission implies execute permission and write permission
388 * implies read permission.
389 */
390 /*xwr*/
391 #define __P000 PAGE_NONE
392 #define __P001 PAGE_READ
393 #define __P010 PAGE_READ
394 #define __P011 PAGE_READ
395 #define __P100 PAGE_READ
396 #define __P101 PAGE_READ
397 #define __P110 PAGE_READ
398 #define __P111 PAGE_READ
399
400 #define __S000 PAGE_NONE
401 #define __S001 PAGE_READ
402 #define __S010 PAGE_WRITE
403 #define __S011 PAGE_WRITE
404 #define __S100 PAGE_READ
405 #define __S101 PAGE_READ
406 #define __S110 PAGE_WRITE
407 #define __S111 PAGE_WRITE
408
409 /*
410 * Segment entry (large page) protection definitions.
411 */
412 #define SEGMENT_NONE __pgprot(_SEGMENT_ENTRY_INVALID | \
413 _SEGMENT_ENTRY_PROTECT)
414 #define SEGMENT_READ __pgprot(_SEGMENT_ENTRY_PROTECT)
415 #define SEGMENT_WRITE __pgprot(0)
416
417 static inline int mm_has_pgste(struct mm_struct *mm)
418 {
419 #ifdef CONFIG_PGSTE
420 if (unlikely(mm->context.has_pgste))
421 return 1;
422 #endif
423 return 0;
424 }
425 /*
426 * pgd/pmd/pte query functions
427 */
428 #ifndef CONFIG_64BIT
429
430 static inline int pgd_present(pgd_t pgd) { return 1; }
431 static inline int pgd_none(pgd_t pgd) { return 0; }
432 static inline int pgd_bad(pgd_t pgd) { return 0; }
433
434 static inline int pud_present(pud_t pud) { return 1; }
435 static inline int pud_none(pud_t pud) { return 0; }
436 static inline int pud_large(pud_t pud) { return 0; }
437 static inline int pud_bad(pud_t pud) { return 0; }
438
439 #else /* CONFIG_64BIT */
440
441 static inline int pgd_present(pgd_t pgd)
442 {
443 if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2)
444 return 1;
445 return (pgd_val(pgd) & _REGION_ENTRY_ORIGIN) != 0UL;
446 }
447
448 static inline int pgd_none(pgd_t pgd)
449 {
450 if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2)
451 return 0;
452 return (pgd_val(pgd) & _REGION_ENTRY_INVALID) != 0UL;
453 }
454
455 static inline int pgd_bad(pgd_t pgd)
456 {
457 /*
458 * With dynamic page table levels the pgd can be a region table
459 * entry or a segment table entry. Check for the bit that are
460 * invalid for either table entry.
461 */
462 unsigned long mask =
463 ~_SEGMENT_ENTRY_ORIGIN & ~_REGION_ENTRY_INVALID &
464 ~_REGION_ENTRY_TYPE_MASK & ~_REGION_ENTRY_LENGTH;
465 return (pgd_val(pgd) & mask) != 0;
466 }
467
468 static inline int pud_present(pud_t pud)
469 {
470 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3)
471 return 1;
472 return (pud_val(pud) & _REGION_ENTRY_ORIGIN) != 0UL;
473 }
474
475 static inline int pud_none(pud_t pud)
476 {
477 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3)
478 return 0;
479 return (pud_val(pud) & _REGION_ENTRY_INVALID) != 0UL;
480 }
481
482 static inline int pud_large(pud_t pud)
483 {
484 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) != _REGION_ENTRY_TYPE_R3)
485 return 0;
486 return !!(pud_val(pud) & _REGION3_ENTRY_LARGE);
487 }
488
489 static inline int pud_bad(pud_t pud)
490 {
491 /*
492 * With dynamic page table levels the pud can be a region table
493 * entry or a segment table entry. Check for the bit that are
494 * invalid for either table entry.
495 */
496 unsigned long mask =
497 ~_SEGMENT_ENTRY_ORIGIN & ~_REGION_ENTRY_INVALID &
498 ~_REGION_ENTRY_TYPE_MASK & ~_REGION_ENTRY_LENGTH;
499 return (pud_val(pud) & mask) != 0;
500 }
501
502 #endif /* CONFIG_64BIT */
503
504 static inline int pmd_present(pmd_t pmd)
505 {
506 return pmd_val(pmd) != _SEGMENT_ENTRY_INVALID;
507 }
508
509 static inline int pmd_none(pmd_t pmd)
510 {
511 return pmd_val(pmd) == _SEGMENT_ENTRY_INVALID;
512 }
513
514 static inline int pmd_large(pmd_t pmd)
515 {
516 #ifdef CONFIG_64BIT
517 return (pmd_val(pmd) & _SEGMENT_ENTRY_LARGE) != 0;
518 #else
519 return 0;
520 #endif
521 }
522
523 static inline int pmd_bad(pmd_t pmd)
524 {
525 unsigned long mask = ~_SEGMENT_ENTRY_ORIGIN & ~_SEGMENT_ENTRY_INVALID;
526 return (pmd_val(pmd) & mask) != _SEGMENT_ENTRY;
527 }
528
529 #define __HAVE_ARCH_PMDP_SPLITTING_FLUSH
530 extern void pmdp_splitting_flush(struct vm_area_struct *vma,
531 unsigned long addr, pmd_t *pmdp);
532
533 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS
534 extern int pmdp_set_access_flags(struct vm_area_struct *vma,
535 unsigned long address, pmd_t *pmdp,
536 pmd_t entry, int dirty);
537
538 #define __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH
539 extern int pmdp_clear_flush_young(struct vm_area_struct *vma,
540 unsigned long address, pmd_t *pmdp);
541
542 #define __HAVE_ARCH_PMD_WRITE
543 static inline int pmd_write(pmd_t pmd)
544 {
545 return (pmd_val(pmd) & _SEGMENT_ENTRY_PROTECT) == 0;
546 }
547
548 static inline int pmd_young(pmd_t pmd)
549 {
550 return 0;
551 }
552
553 static inline int pte_present(pte_t pte)
554 {
555 /* Bit pattern: (pte & 0x001) == 0x001 */
556 return (pte_val(pte) & _PAGE_PRESENT) != 0;
557 }
558
559 static inline int pte_none(pte_t pte)
560 {
561 /* Bit pattern: pte == 0x400 */
562 return pte_val(pte) == _PAGE_INVALID;
563 }
564
565 static inline int pte_file(pte_t pte)
566 {
567 /* Bit pattern: (pte & 0x601) == 0x600 */
568 return (pte_val(pte) & (_PAGE_INVALID | _PAGE_PROTECT | _PAGE_PRESENT))
569 == (_PAGE_INVALID | _PAGE_PROTECT);
570 }
571
572 static inline int pte_special(pte_t pte)
573 {
574 return (pte_val(pte) & _PAGE_SPECIAL);
575 }
576
577 #define __HAVE_ARCH_PTE_SAME
578 static inline int pte_same(pte_t a, pte_t b)
579 {
580 return pte_val(a) == pte_val(b);
581 }
582
583 static inline pgste_t pgste_get_lock(pte_t *ptep)
584 {
585 unsigned long new = 0;
586 #ifdef CONFIG_PGSTE
587 unsigned long old;
588
589 preempt_disable();
590 asm(
591 " lg %0,%2\n"
592 "0: lgr %1,%0\n"
593 " nihh %0,0xff7f\n" /* clear PCL bit in old */
594 " oihh %1,0x0080\n" /* set PCL bit in new */
595 " csg %0,%1,%2\n"
596 " jl 0b\n"
597 : "=&d" (old), "=&d" (new), "=Q" (ptep[PTRS_PER_PTE])
598 : "Q" (ptep[PTRS_PER_PTE]) : "cc", "memory");
599 #endif
600 return __pgste(new);
601 }
602
603 static inline void pgste_set_unlock(pte_t *ptep, pgste_t pgste)
604 {
605 #ifdef CONFIG_PGSTE
606 asm(
607 " nihh %1,0xff7f\n" /* clear PCL bit */
608 " stg %1,%0\n"
609 : "=Q" (ptep[PTRS_PER_PTE])
610 : "d" (pgste_val(pgste)), "Q" (ptep[PTRS_PER_PTE])
611 : "cc", "memory");
612 preempt_enable();
613 #endif
614 }
615
616 static inline pgste_t pgste_get(pte_t *ptep)
617 {
618 unsigned long pgste = 0;
619 #ifdef CONFIG_PGSTE
620 pgste = *(unsigned long *)(ptep + PTRS_PER_PTE);
621 #endif
622 return __pgste(pgste);
623 }
624
625 static inline void pgste_set(pte_t *ptep, pgste_t pgste)
626 {
627 #ifdef CONFIG_PGSTE
628 *(pgste_t *)(ptep + PTRS_PER_PTE) = pgste;
629 #endif
630 }
631
632 static inline pgste_t pgste_update_all(pte_t *ptep, pgste_t pgste)
633 {
634 #ifdef CONFIG_PGSTE
635 unsigned long address, bits;
636 unsigned char skey;
637
638 if (pte_val(*ptep) & _PAGE_INVALID)
639 return pgste;
640 address = pte_val(*ptep) & PAGE_MASK;
641 skey = page_get_storage_key(address);
642 bits = skey & (_PAGE_CHANGED | _PAGE_REFERENCED);
643 /* Clear page changed & referenced bit in the storage key */
644 if (bits & _PAGE_CHANGED)
645 page_set_storage_key(address, skey ^ bits, 0);
646 else if (bits)
647 page_reset_referenced(address);
648 /* Transfer page changed & referenced bit to guest bits in pgste */
649 pgste_val(pgste) |= bits << 48; /* GR bit & GC bit */
650 /* Get host changed & referenced bits from pgste */
651 bits |= (pgste_val(pgste) & (PGSTE_HR_BIT | PGSTE_HC_BIT)) >> 52;
652 /* Transfer page changed & referenced bit to kvm user bits */
653 pgste_val(pgste) |= bits << 45; /* PGSTE_UR_BIT & PGSTE_UC_BIT */
654 /* Clear relevant host bits in pgste. */
655 pgste_val(pgste) &= ~(PGSTE_HR_BIT | PGSTE_HC_BIT);
656 pgste_val(pgste) &= ~(PGSTE_ACC_BITS | PGSTE_FP_BIT);
657 /* Copy page access key and fetch protection bit to pgste */
658 pgste_val(pgste) |=
659 (unsigned long) (skey & (_PAGE_ACC_BITS | _PAGE_FP_BIT)) << 56;
660 /* Transfer referenced bit to pte */
661 pte_val(*ptep) |= (bits & _PAGE_REFERENCED) << 1;
662 #endif
663 return pgste;
664
665 }
666
667 static inline pgste_t pgste_update_young(pte_t *ptep, pgste_t pgste)
668 {
669 #ifdef CONFIG_PGSTE
670 int young;
671
672 if (pte_val(*ptep) & _PAGE_INVALID)
673 return pgste;
674 /* Get referenced bit from storage key */
675 young = page_reset_referenced(pte_val(*ptep) & PAGE_MASK);
676 if (young)
677 pgste_val(pgste) |= PGSTE_GR_BIT;
678 /* Get host referenced bit from pgste */
679 if (pgste_val(pgste) & PGSTE_HR_BIT) {
680 pgste_val(pgste) &= ~PGSTE_HR_BIT;
681 young = 1;
682 }
683 /* Transfer referenced bit to kvm user bits and pte */
684 if (young) {
685 pgste_val(pgste) |= PGSTE_UR_BIT;
686 pte_val(*ptep) |= _PAGE_YOUNG;
687 }
688 #endif
689 return pgste;
690 }
691
692 static inline void pgste_set_key(pte_t *ptep, pgste_t pgste, pte_t entry)
693 {
694 #ifdef CONFIG_PGSTE
695 unsigned long address;
696 unsigned long nkey;
697
698 if (pte_val(entry) & _PAGE_INVALID)
699 return;
700 VM_BUG_ON(!(pte_val(*ptep) & _PAGE_INVALID));
701 address = pte_val(entry) & PAGE_MASK;
702 /*
703 * Set page access key and fetch protection bit from pgste.
704 * The guest C/R information is still in the PGSTE, set real
705 * key C/R to 0.
706 */
707 nkey = (pgste_val(pgste) & (PGSTE_ACC_BITS | PGSTE_FP_BIT)) >> 56;
708 page_set_storage_key(address, nkey, 0);
709 #endif
710 }
711
712 static inline void pgste_set_pte(pte_t *ptep, pte_t entry)
713 {
714 if (!MACHINE_HAS_ESOP && (pte_val(entry) & _PAGE_WRITE)) {
715 /*
716 * Without enhanced suppression-on-protection force
717 * the dirty bit on for all writable ptes.
718 */
719 pte_val(entry) |= _PAGE_DIRTY;
720 pte_val(entry) &= ~_PAGE_PROTECT;
721 }
722 *ptep = entry;
723 }
724
725 /**
726 * struct gmap_struct - guest address space
727 * @mm: pointer to the parent mm_struct
728 * @table: pointer to the page directory
729 * @asce: address space control element for gmap page table
730 * @crst_list: list of all crst tables used in the guest address space
731 */
732 struct gmap {
733 struct list_head list;
734 struct mm_struct *mm;
735 unsigned long *table;
736 unsigned long asce;
737 void *private;
738 struct list_head crst_list;
739 };
740
741 /**
742 * struct gmap_rmap - reverse mapping for segment table entries
743 * @gmap: pointer to the gmap_struct
744 * @entry: pointer to a segment table entry
745 * @vmaddr: virtual address in the guest address space
746 */
747 struct gmap_rmap {
748 struct list_head list;
749 struct gmap *gmap;
750 unsigned long *entry;
751 unsigned long vmaddr;
752 };
753
754 /**
755 * struct gmap_pgtable - gmap information attached to a page table
756 * @vmaddr: address of the 1MB segment in the process virtual memory
757 * @mapper: list of segment table entries mapping a page table
758 */
759 struct gmap_pgtable {
760 unsigned long vmaddr;
761 struct list_head mapper;
762 };
763
764 /**
765 * struct gmap_notifier - notify function block for page invalidation
766 * @notifier_call: address of callback function
767 */
768 struct gmap_notifier {
769 struct list_head list;
770 void (*notifier_call)(struct gmap *gmap, unsigned long address);
771 };
772
773 struct gmap *gmap_alloc(struct mm_struct *mm);
774 void gmap_free(struct gmap *gmap);
775 void gmap_enable(struct gmap *gmap);
776 void gmap_disable(struct gmap *gmap);
777 int gmap_map_segment(struct gmap *gmap, unsigned long from,
778 unsigned long to, unsigned long len);
779 int gmap_unmap_segment(struct gmap *gmap, unsigned long to, unsigned long len);
780 unsigned long __gmap_translate(unsigned long address, struct gmap *);
781 unsigned long gmap_translate(unsigned long address, struct gmap *);
782 unsigned long __gmap_fault(unsigned long address, struct gmap *);
783 unsigned long gmap_fault(unsigned long address, struct gmap *);
784 void gmap_discard(unsigned long from, unsigned long to, struct gmap *);
785
786 void gmap_register_ipte_notifier(struct gmap_notifier *);
787 void gmap_unregister_ipte_notifier(struct gmap_notifier *);
788 int gmap_ipte_notify(struct gmap *, unsigned long start, unsigned long len);
789 void gmap_do_ipte_notify(struct mm_struct *, unsigned long addr, pte_t *);
790
791 static inline pgste_t pgste_ipte_notify(struct mm_struct *mm,
792 unsigned long addr,
793 pte_t *ptep, pgste_t pgste)
794 {
795 #ifdef CONFIG_PGSTE
796 if (pgste_val(pgste) & PGSTE_IN_BIT) {
797 pgste_val(pgste) &= ~PGSTE_IN_BIT;
798 gmap_do_ipte_notify(mm, addr, ptep);
799 }
800 #endif
801 return pgste;
802 }
803
804 /*
805 * Certain architectures need to do special things when PTEs
806 * within a page table are directly modified. Thus, the following
807 * hook is made available.
808 */
809 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
810 pte_t *ptep, pte_t entry)
811 {
812 pgste_t pgste;
813
814 if (mm_has_pgste(mm)) {
815 pgste = pgste_get_lock(ptep);
816 pgste_set_key(ptep, pgste, entry);
817 pgste_set_pte(ptep, entry);
818 pgste_set_unlock(ptep, pgste);
819 } else {
820 if (!(pte_val(entry) & _PAGE_INVALID) && MACHINE_HAS_EDAT1)
821 pte_val(entry) |= _PAGE_CO;
822 *ptep = entry;
823 }
824 }
825
826 /*
827 * query functions pte_write/pte_dirty/pte_young only work if
828 * pte_present() is true. Undefined behaviour if not..
829 */
830 static inline int pte_write(pte_t pte)
831 {
832 return (pte_val(pte) & _PAGE_WRITE) != 0;
833 }
834
835 static inline int pte_dirty(pte_t pte)
836 {
837 return (pte_val(pte) & _PAGE_DIRTY) != 0;
838 }
839
840 static inline int pte_young(pte_t pte)
841 {
842 #ifdef CONFIG_PGSTE
843 if (pte_val(pte) & _PAGE_YOUNG)
844 return 1;
845 #endif
846 return 0;
847 }
848
849 /*
850 * pgd/pmd/pte modification functions
851 */
852
853 static inline void pgd_clear(pgd_t *pgd)
854 {
855 #ifdef CONFIG_64BIT
856 if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2)
857 pgd_val(*pgd) = _REGION2_ENTRY_EMPTY;
858 #endif
859 }
860
861 static inline void pud_clear(pud_t *pud)
862 {
863 #ifdef CONFIG_64BIT
864 if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3)
865 pud_val(*pud) = _REGION3_ENTRY_EMPTY;
866 #endif
867 }
868
869 static inline void pmd_clear(pmd_t *pmdp)
870 {
871 pmd_val(*pmdp) = _SEGMENT_ENTRY_INVALID;
872 }
873
874 static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
875 {
876 pte_val(*ptep) = _PAGE_INVALID;
877 }
878
879 /*
880 * The following pte modification functions only work if
881 * pte_present() is true. Undefined behaviour if not..
882 */
883 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
884 {
885 pte_val(pte) &= _PAGE_CHG_MASK;
886 pte_val(pte) |= pgprot_val(newprot);
887 if ((pte_val(pte) & _PAGE_DIRTY) && (pte_val(pte) & _PAGE_WRITE))
888 pte_val(pte) &= ~_PAGE_PROTECT;
889 return pte;
890 }
891
892 static inline pte_t pte_wrprotect(pte_t pte)
893 {
894 pte_val(pte) &= ~_PAGE_WRITE;
895 pte_val(pte) |= _PAGE_PROTECT;
896 return pte;
897 }
898
899 static inline pte_t pte_mkwrite(pte_t pte)
900 {
901 pte_val(pte) |= _PAGE_WRITE;
902 if (pte_val(pte) & _PAGE_DIRTY)
903 pte_val(pte) &= ~_PAGE_PROTECT;
904 return pte;
905 }
906
907 static inline pte_t pte_mkclean(pte_t pte)
908 {
909 pte_val(pte) &= ~_PAGE_DIRTY;
910 pte_val(pte) |= _PAGE_PROTECT;
911 return pte;
912 }
913
914 static inline pte_t pte_mkdirty(pte_t pte)
915 {
916 pte_val(pte) |= _PAGE_DIRTY;
917 if (pte_val(pte) & _PAGE_WRITE)
918 pte_val(pte) &= ~_PAGE_PROTECT;
919 return pte;
920 }
921
922 static inline pte_t pte_mkold(pte_t pte)
923 {
924 #ifdef CONFIG_PGSTE
925 pte_val(pte) &= ~_PAGE_YOUNG;
926 #endif
927 return pte;
928 }
929
930 static inline pte_t pte_mkyoung(pte_t pte)
931 {
932 return pte;
933 }
934
935 static inline pte_t pte_mkspecial(pte_t pte)
936 {
937 pte_val(pte) |= _PAGE_SPECIAL;
938 return pte;
939 }
940
941 #ifdef CONFIG_HUGETLB_PAGE
942 static inline pte_t pte_mkhuge(pte_t pte)
943 {
944 pte_val(pte) |= _PAGE_LARGE;
945 return pte;
946 }
947 #endif
948
949 /*
950 * Get (and clear) the user dirty bit for a pte.
951 */
952 static inline int ptep_test_and_clear_user_dirty(struct mm_struct *mm,
953 pte_t *ptep)
954 {
955 pgste_t pgste;
956 int dirty = 0;
957
958 if (mm_has_pgste(mm)) {
959 pgste = pgste_get_lock(ptep);
960 pgste = pgste_update_all(ptep, pgste);
961 dirty = !!(pgste_val(pgste) & PGSTE_UC_BIT);
962 pgste_val(pgste) &= ~PGSTE_UC_BIT;
963 pgste_set_unlock(ptep, pgste);
964 return dirty;
965 }
966 return dirty;
967 }
968
969 /*
970 * Get (and clear) the user referenced bit for a pte.
971 */
972 static inline int ptep_test_and_clear_user_young(struct mm_struct *mm,
973 pte_t *ptep)
974 {
975 pgste_t pgste;
976 int young = 0;
977
978 if (mm_has_pgste(mm)) {
979 pgste = pgste_get_lock(ptep);
980 pgste = pgste_update_young(ptep, pgste);
981 young = !!(pgste_val(pgste) & PGSTE_UR_BIT);
982 pgste_val(pgste) &= ~PGSTE_UR_BIT;
983 pgste_set_unlock(ptep, pgste);
984 }
985 return young;
986 }
987
988 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
989 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma,
990 unsigned long addr, pte_t *ptep)
991 {
992 pgste_t pgste;
993 pte_t pte;
994
995 if (mm_has_pgste(vma->vm_mm)) {
996 pgste = pgste_get_lock(ptep);
997 pgste = pgste_update_young(ptep, pgste);
998 pte = *ptep;
999 *ptep = pte_mkold(pte);
1000 pgste_set_unlock(ptep, pgste);
1001 return pte_young(pte);
1002 }
1003 return 0;
1004 }
1005
1006 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
1007 static inline int ptep_clear_flush_young(struct vm_area_struct *vma,
1008 unsigned long address, pte_t *ptep)
1009 {
1010 /* No need to flush TLB
1011 * On s390 reference bits are in storage key and never in TLB
1012 * With virtualization we handle the reference bit, without we
1013 * we can simply return */
1014 return ptep_test_and_clear_young(vma, address, ptep);
1015 }
1016
1017 static inline void __ptep_ipte(unsigned long address, pte_t *ptep)
1018 {
1019 if (!(pte_val(*ptep) & _PAGE_INVALID)) {
1020 #ifndef CONFIG_64BIT
1021 /* pto must point to the start of the segment table */
1022 pte_t *pto = (pte_t *) (((unsigned long) ptep) & 0x7ffffc00);
1023 #else
1024 /* ipte in zarch mode can do the math */
1025 pte_t *pto = ptep;
1026 #endif
1027 asm volatile(
1028 " ipte %2,%3"
1029 : "=m" (*ptep) : "m" (*ptep),
1030 "a" (pto), "a" (address));
1031 }
1032 }
1033
1034 static inline void ptep_flush_lazy(struct mm_struct *mm,
1035 unsigned long address, pte_t *ptep)
1036 {
1037 int active = (mm == current->active_mm) ? 1 : 0;
1038
1039 if (atomic_read(&mm->context.attach_count) > active)
1040 __ptep_ipte(address, ptep);
1041 else
1042 mm->context.flush_mm = 1;
1043 }
1044
1045 /*
1046 * This is hard to understand. ptep_get_and_clear and ptep_clear_flush
1047 * both clear the TLB for the unmapped pte. The reason is that
1048 * ptep_get_and_clear is used in common code (e.g. change_pte_range)
1049 * to modify an active pte. The sequence is
1050 * 1) ptep_get_and_clear
1051 * 2) set_pte_at
1052 * 3) flush_tlb_range
1053 * On s390 the tlb needs to get flushed with the modification of the pte
1054 * if the pte is active. The only way how this can be implemented is to
1055 * have ptep_get_and_clear do the tlb flush. In exchange flush_tlb_range
1056 * is a nop.
1057 */
1058 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
1059 static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
1060 unsigned long address, pte_t *ptep)
1061 {
1062 pgste_t pgste;
1063 pte_t pte;
1064
1065 if (mm_has_pgste(mm)) {
1066 pgste = pgste_get_lock(ptep);
1067 pgste = pgste_ipte_notify(mm, address, ptep, pgste);
1068 }
1069
1070 pte = *ptep;
1071 ptep_flush_lazy(mm, address, ptep);
1072 pte_val(*ptep) = _PAGE_INVALID;
1073
1074 if (mm_has_pgste(mm)) {
1075 pgste = pgste_update_all(&pte, pgste);
1076 pgste_set_unlock(ptep, pgste);
1077 }
1078 return pte;
1079 }
1080
1081 #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION
1082 static inline pte_t ptep_modify_prot_start(struct mm_struct *mm,
1083 unsigned long address,
1084 pte_t *ptep)
1085 {
1086 pgste_t pgste;
1087 pte_t pte;
1088
1089 if (mm_has_pgste(mm)) {
1090 pgste = pgste_get_lock(ptep);
1091 pgste_ipte_notify(mm, address, ptep, pgste);
1092 }
1093
1094 pte = *ptep;
1095 ptep_flush_lazy(mm, address, ptep);
1096
1097 if (mm_has_pgste(mm)) {
1098 pgste = pgste_update_all(&pte, pgste);
1099 pgste_set(ptep, pgste);
1100 }
1101 return pte;
1102 }
1103
1104 static inline void ptep_modify_prot_commit(struct mm_struct *mm,
1105 unsigned long address,
1106 pte_t *ptep, pte_t pte)
1107 {
1108 pgste_t pgste;
1109
1110 if (mm_has_pgste(mm)) {
1111 pgste = pgste_get(ptep);
1112 pgste_set_key(ptep, pgste, pte);
1113 pgste_set_pte(ptep, pte);
1114 pgste_set_unlock(ptep, pgste);
1115 } else
1116 *ptep = pte;
1117 }
1118
1119 #define __HAVE_ARCH_PTEP_CLEAR_FLUSH
1120 static inline pte_t ptep_clear_flush(struct vm_area_struct *vma,
1121 unsigned long address, pte_t *ptep)
1122 {
1123 pgste_t pgste;
1124 pte_t pte;
1125
1126 if (mm_has_pgste(vma->vm_mm)) {
1127 pgste = pgste_get_lock(ptep);
1128 pgste = pgste_ipte_notify(vma->vm_mm, address, ptep, pgste);
1129 }
1130
1131 pte = *ptep;
1132 __ptep_ipte(address, ptep);
1133 pte_val(*ptep) = _PAGE_INVALID;
1134
1135 if (mm_has_pgste(vma->vm_mm)) {
1136 pgste = pgste_update_all(&pte, pgste);
1137 pgste_set_unlock(ptep, pgste);
1138 }
1139 return pte;
1140 }
1141
1142 /*
1143 * The batched pte unmap code uses ptep_get_and_clear_full to clear the
1144 * ptes. Here an optimization is possible. tlb_gather_mmu flushes all
1145 * tlbs of an mm if it can guarantee that the ptes of the mm_struct
1146 * cannot be accessed while the batched unmap is running. In this case
1147 * full==1 and a simple pte_clear is enough. See tlb.h.
1148 */
1149 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL
1150 static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm,
1151 unsigned long address,
1152 pte_t *ptep, int full)
1153 {
1154 pgste_t pgste;
1155 pte_t pte;
1156
1157 if (!full && mm_has_pgste(mm)) {
1158 pgste = pgste_get_lock(ptep);
1159 pgste = pgste_ipte_notify(mm, address, ptep, pgste);
1160 }
1161
1162 pte = *ptep;
1163 if (!full)
1164 ptep_flush_lazy(mm, address, ptep);
1165 pte_val(*ptep) = _PAGE_INVALID;
1166
1167 if (!full && mm_has_pgste(mm)) {
1168 pgste = pgste_update_all(&pte, pgste);
1169 pgste_set_unlock(ptep, pgste);
1170 }
1171 return pte;
1172 }
1173
1174 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
1175 static inline pte_t ptep_set_wrprotect(struct mm_struct *mm,
1176 unsigned long address, pte_t *ptep)
1177 {
1178 pgste_t pgste;
1179 pte_t pte = *ptep;
1180
1181 if (pte_write(pte)) {
1182 if (mm_has_pgste(mm)) {
1183 pgste = pgste_get_lock(ptep);
1184 pgste = pgste_ipte_notify(mm, address, ptep, pgste);
1185 }
1186
1187 ptep_flush_lazy(mm, address, ptep);
1188 pte = pte_wrprotect(pte);
1189
1190 if (mm_has_pgste(mm)) {
1191 pgste_set_pte(ptep, pte);
1192 pgste_set_unlock(ptep, pgste);
1193 } else
1194 *ptep = pte;
1195 }
1196 return pte;
1197 }
1198
1199 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
1200 static inline int ptep_set_access_flags(struct vm_area_struct *vma,
1201 unsigned long address, pte_t *ptep,
1202 pte_t entry, int dirty)
1203 {
1204 pgste_t pgste;
1205
1206 if (pte_same(*ptep, entry))
1207 return 0;
1208 if (mm_has_pgste(vma->vm_mm)) {
1209 pgste = pgste_get_lock(ptep);
1210 pgste = pgste_ipte_notify(vma->vm_mm, address, ptep, pgste);
1211 }
1212
1213 __ptep_ipte(address, ptep);
1214
1215 if (mm_has_pgste(vma->vm_mm)) {
1216 pgste_set_pte(ptep, entry);
1217 pgste_set_unlock(ptep, pgste);
1218 } else
1219 *ptep = entry;
1220 return 1;
1221 }
1222
1223 /*
1224 * Conversion functions: convert a page and protection to a page entry,
1225 * and a page entry and page directory to the page they refer to.
1226 */
1227 static inline pte_t mk_pte_phys(unsigned long physpage, pgprot_t pgprot)
1228 {
1229 pte_t __pte;
1230 pte_val(__pte) = physpage + pgprot_val(pgprot);
1231 return __pte;
1232 }
1233
1234 static inline pte_t mk_pte(struct page *page, pgprot_t pgprot)
1235 {
1236 unsigned long physpage = page_to_phys(page);
1237 pte_t __pte = mk_pte_phys(physpage, pgprot);
1238
1239 if (pte_write(__pte) && PageDirty(page))
1240 __pte = pte_mkdirty(__pte);
1241 return __pte;
1242 }
1243
1244 #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
1245 #define pud_index(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
1246 #define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
1247 #define pte_index(address) (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE-1))
1248
1249 #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
1250 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
1251
1252 #ifndef CONFIG_64BIT
1253
1254 #define pmd_deref(pmd) (pmd_val(pmd) & _SEGMENT_ENTRY_ORIGIN)
1255 #define pud_deref(pmd) ({ BUG(); 0UL; })
1256 #define pgd_deref(pmd) ({ BUG(); 0UL; })
1257
1258 #define pud_offset(pgd, address) ((pud_t *) pgd)
1259 #define pmd_offset(pud, address) ((pmd_t *) pud + pmd_index(address))
1260
1261 #else /* CONFIG_64BIT */
1262
1263 #define pmd_deref(pmd) (pmd_val(pmd) & _SEGMENT_ENTRY_ORIGIN)
1264 #define pud_deref(pud) (pud_val(pud) & _REGION_ENTRY_ORIGIN)
1265 #define pgd_deref(pgd) (pgd_val(pgd) & _REGION_ENTRY_ORIGIN)
1266
1267 static inline pud_t *pud_offset(pgd_t *pgd, unsigned long address)
1268 {
1269 pud_t *pud = (pud_t *) pgd;
1270 if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2)
1271 pud = (pud_t *) pgd_deref(*pgd);
1272 return pud + pud_index(address);
1273 }
1274
1275 static inline pmd_t *pmd_offset(pud_t *pud, unsigned long address)
1276 {
1277 pmd_t *pmd = (pmd_t *) pud;
1278 if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3)
1279 pmd = (pmd_t *) pud_deref(*pud);
1280 return pmd + pmd_index(address);
1281 }
1282
1283 #endif /* CONFIG_64BIT */
1284
1285 #define pfn_pte(pfn,pgprot) mk_pte_phys(__pa((pfn) << PAGE_SHIFT),(pgprot))
1286 #define pte_pfn(x) (pte_val(x) >> PAGE_SHIFT)
1287 #define pte_page(x) pfn_to_page(pte_pfn(x))
1288
1289 #define pmd_page(pmd) pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT)
1290
1291 /* Find an entry in the lowest level page table.. */
1292 #define pte_offset(pmd, addr) ((pte_t *) pmd_deref(*(pmd)) + pte_index(addr))
1293 #define pte_offset_kernel(pmd, address) pte_offset(pmd,address)
1294 #define pte_offset_map(pmd, address) pte_offset_kernel(pmd, address)
1295 #define pte_unmap(pte) do { } while (0)
1296
1297 static inline void __pmd_idte(unsigned long address, pmd_t *pmdp)
1298 {
1299 unsigned long sto = (unsigned long) pmdp -
1300 pmd_index(address) * sizeof(pmd_t);
1301
1302 if (!(pmd_val(*pmdp) & _SEGMENT_ENTRY_INVALID)) {
1303 asm volatile(
1304 " .insn rrf,0xb98e0000,%2,%3,0,0"
1305 : "=m" (*pmdp)
1306 : "m" (*pmdp), "a" (sto),
1307 "a" ((address & HPAGE_MASK))
1308 : "cc"
1309 );
1310 }
1311 }
1312
1313 static inline void __pmd_csp(pmd_t *pmdp)
1314 {
1315 register unsigned long reg2 asm("2") = pmd_val(*pmdp);
1316 register unsigned long reg3 asm("3") = pmd_val(*pmdp) |
1317 _SEGMENT_ENTRY_INVALID;
1318 register unsigned long reg4 asm("4") = ((unsigned long) pmdp) + 5;
1319
1320 asm volatile(
1321 " csp %1,%3"
1322 : "=m" (*pmdp)
1323 : "d" (reg2), "d" (reg3), "d" (reg4), "m" (*pmdp) : "cc");
1324 }
1325
1326 #if defined(CONFIG_TRANSPARENT_HUGEPAGE) || defined(CONFIG_HUGETLB_PAGE)
1327 static inline unsigned long massage_pgprot_pmd(pgprot_t pgprot)
1328 {
1329 /*
1330 * pgprot is PAGE_NONE, PAGE_READ, or PAGE_WRITE (see __Pxxx / __Sxxx)
1331 * Convert to segment table entry format.
1332 */
1333 if (pgprot_val(pgprot) == pgprot_val(PAGE_NONE))
1334 return pgprot_val(SEGMENT_NONE);
1335 if (pgprot_val(pgprot) == pgprot_val(PAGE_READ))
1336 return pgprot_val(SEGMENT_READ);
1337 return pgprot_val(SEGMENT_WRITE);
1338 }
1339
1340 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
1341 {
1342 pmd_val(pmd) &= _SEGMENT_CHG_MASK;
1343 pmd_val(pmd) |= massage_pgprot_pmd(newprot);
1344 return pmd;
1345 }
1346
1347 static inline pmd_t mk_pmd_phys(unsigned long physpage, pgprot_t pgprot)
1348 {
1349 pmd_t __pmd;
1350 pmd_val(__pmd) = physpage + massage_pgprot_pmd(pgprot);
1351 return __pmd;
1352 }
1353
1354 static inline pmd_t pmd_mkwrite(pmd_t pmd)
1355 {
1356 /* Do not clobber PROT_NONE pages! */
1357 if (!(pmd_val(pmd) & _SEGMENT_ENTRY_INVALID))
1358 pmd_val(pmd) &= ~_SEGMENT_ENTRY_PROTECT;
1359 return pmd;
1360 }
1361 #endif /* CONFIG_TRANSPARENT_HUGEPAGE || CONFIG_HUGETLB_PAGE */
1362
1363 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
1364
1365 #define __HAVE_ARCH_PGTABLE_DEPOSIT
1366 extern void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp,
1367 pgtable_t pgtable);
1368
1369 #define __HAVE_ARCH_PGTABLE_WITHDRAW
1370 extern pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp);
1371
1372 static inline int pmd_trans_splitting(pmd_t pmd)
1373 {
1374 return pmd_val(pmd) & _SEGMENT_ENTRY_SPLIT;
1375 }
1376
1377 static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr,
1378 pmd_t *pmdp, pmd_t entry)
1379 {
1380 if (!(pmd_val(entry) & _SEGMENT_ENTRY_INVALID) && MACHINE_HAS_EDAT1)
1381 pmd_val(entry) |= _SEGMENT_ENTRY_CO;
1382 *pmdp = entry;
1383 }
1384
1385 static inline pmd_t pmd_mkhuge(pmd_t pmd)
1386 {
1387 pmd_val(pmd) |= _SEGMENT_ENTRY_LARGE;
1388 return pmd;
1389 }
1390
1391 static inline pmd_t pmd_wrprotect(pmd_t pmd)
1392 {
1393 pmd_val(pmd) |= _SEGMENT_ENTRY_PROTECT;
1394 return pmd;
1395 }
1396
1397 static inline pmd_t pmd_mkdirty(pmd_t pmd)
1398 {
1399 /* No dirty bit in the segment table entry. */
1400 return pmd;
1401 }
1402
1403 static inline pmd_t pmd_mkold(pmd_t pmd)
1404 {
1405 /* No referenced bit in the segment table entry. */
1406 return pmd;
1407 }
1408
1409 static inline pmd_t pmd_mkyoung(pmd_t pmd)
1410 {
1411 /* No referenced bit in the segment table entry. */
1412 return pmd;
1413 }
1414
1415 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG
1416 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma,
1417 unsigned long address, pmd_t *pmdp)
1418 {
1419 unsigned long pmd_addr = pmd_val(*pmdp) & HPAGE_MASK;
1420 long tmp, rc;
1421 int counter;
1422
1423 rc = 0;
1424 if (MACHINE_HAS_RRBM) {
1425 counter = PTRS_PER_PTE >> 6;
1426 asm volatile(
1427 "0: .insn rre,0xb9ae0000,%0,%3\n" /* rrbm */
1428 " ogr %1,%0\n"
1429 " la %3,0(%4,%3)\n"
1430 " brct %2,0b\n"
1431 : "=&d" (tmp), "+&d" (rc), "+d" (counter),
1432 "+a" (pmd_addr)
1433 : "a" (64 * 4096UL) : "cc");
1434 rc = !!rc;
1435 } else {
1436 counter = PTRS_PER_PTE;
1437 asm volatile(
1438 "0: rrbe 0,%2\n"
1439 " la %2,0(%3,%2)\n"
1440 " brc 12,1f\n"
1441 " lhi %0,1\n"
1442 "1: brct %1,0b\n"
1443 : "+d" (rc), "+d" (counter), "+a" (pmd_addr)
1444 : "a" (4096UL) : "cc");
1445 }
1446 return rc;
1447 }
1448
1449 #define __HAVE_ARCH_PMDP_GET_AND_CLEAR
1450 static inline pmd_t pmdp_get_and_clear(struct mm_struct *mm,
1451 unsigned long address, pmd_t *pmdp)
1452 {
1453 pmd_t pmd = *pmdp;
1454
1455 __pmd_idte(address, pmdp);
1456 pmd_clear(pmdp);
1457 return pmd;
1458 }
1459
1460 #define __HAVE_ARCH_PMDP_CLEAR_FLUSH
1461 static inline pmd_t pmdp_clear_flush(struct vm_area_struct *vma,
1462 unsigned long address, pmd_t *pmdp)
1463 {
1464 return pmdp_get_and_clear(vma->vm_mm, address, pmdp);
1465 }
1466
1467 #define __HAVE_ARCH_PMDP_INVALIDATE
1468 static inline void pmdp_invalidate(struct vm_area_struct *vma,
1469 unsigned long address, pmd_t *pmdp)
1470 {
1471 __pmd_idte(address, pmdp);
1472 }
1473
1474 #define __HAVE_ARCH_PMDP_SET_WRPROTECT
1475 static inline void pmdp_set_wrprotect(struct mm_struct *mm,
1476 unsigned long address, pmd_t *pmdp)
1477 {
1478 pmd_t pmd = *pmdp;
1479
1480 if (pmd_write(pmd)) {
1481 __pmd_idte(address, pmdp);
1482 set_pmd_at(mm, address, pmdp, pmd_wrprotect(pmd));
1483 }
1484 }
1485
1486 #define pfn_pmd(pfn, pgprot) mk_pmd_phys(__pa((pfn) << PAGE_SHIFT), (pgprot))
1487 #define mk_pmd(page, pgprot) pfn_pmd(page_to_pfn(page), (pgprot))
1488
1489 static inline int pmd_trans_huge(pmd_t pmd)
1490 {
1491 return pmd_val(pmd) & _SEGMENT_ENTRY_LARGE;
1492 }
1493
1494 static inline int has_transparent_hugepage(void)
1495 {
1496 return MACHINE_HAS_HPAGE ? 1 : 0;
1497 }
1498
1499 static inline unsigned long pmd_pfn(pmd_t pmd)
1500 {
1501 return pmd_val(pmd) >> PAGE_SHIFT;
1502 }
1503 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
1504
1505 /*
1506 * 31 bit swap entry format:
1507 * A page-table entry has some bits we have to treat in a special way.
1508 * Bits 0, 20 and bit 23 have to be zero, otherwise an specification
1509 * exception will occur instead of a page translation exception. The
1510 * specifiation exception has the bad habit not to store necessary
1511 * information in the lowcore.
1512 * Bits 21, 22, 30 and 31 are used to indicate the page type.
1513 * A swap pte is indicated by bit pattern (pte & 0x603) == 0x402
1514 * This leaves the bits 1-19 and bits 24-29 to store type and offset.
1515 * We use the 5 bits from 25-29 for the type and the 20 bits from 1-19
1516 * plus 24 for the offset.
1517 * 0| offset |0110|o|type |00|
1518 * 0 0000000001111111111 2222 2 22222 33
1519 * 0 1234567890123456789 0123 4 56789 01
1520 *
1521 * 64 bit swap entry format:
1522 * A page-table entry has some bits we have to treat in a special way.
1523 * Bits 52 and bit 55 have to be zero, otherwise an specification
1524 * exception will occur instead of a page translation exception. The
1525 * specifiation exception has the bad habit not to store necessary
1526 * information in the lowcore.
1527 * Bits 53, 54, 62 and 63 are used to indicate the page type.
1528 * A swap pte is indicated by bit pattern (pte & 0x603) == 0x402
1529 * This leaves the bits 0-51 and bits 56-61 to store type and offset.
1530 * We use the 5 bits from 57-61 for the type and the 53 bits from 0-51
1531 * plus 56 for the offset.
1532 * | offset |0110|o|type |00|
1533 * 0000000000111111111122222222223333333333444444444455 5555 5 55566 66
1534 * 0123456789012345678901234567890123456789012345678901 2345 6 78901 23
1535 */
1536 #ifndef CONFIG_64BIT
1537 #define __SWP_OFFSET_MASK (~0UL >> 12)
1538 #else
1539 #define __SWP_OFFSET_MASK (~0UL >> 11)
1540 #endif
1541 static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset)
1542 {
1543 pte_t pte;
1544 offset &= __SWP_OFFSET_MASK;
1545 pte_val(pte) = _PAGE_INVALID | _PAGE_TYPE | ((type & 0x1f) << 2) |
1546 ((offset & 1UL) << 7) | ((offset & ~1UL) << 11);
1547 return pte;
1548 }
1549
1550 #define __swp_type(entry) (((entry).val >> 2) & 0x1f)
1551 #define __swp_offset(entry) (((entry).val >> 11) | (((entry).val >> 7) & 1))
1552 #define __swp_entry(type,offset) ((swp_entry_t) { pte_val(mk_swap_pte((type),(offset))) })
1553
1554 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
1555 #define __swp_entry_to_pte(x) ((pte_t) { (x).val })
1556
1557 #ifndef CONFIG_64BIT
1558 # define PTE_FILE_MAX_BITS 26
1559 #else /* CONFIG_64BIT */
1560 # define PTE_FILE_MAX_BITS 59
1561 #endif /* CONFIG_64BIT */
1562
1563 #define pte_to_pgoff(__pte) \
1564 ((((__pte).pte >> 12) << 7) + (((__pte).pte >> 1) & 0x7f))
1565
1566 #define pgoff_to_pte(__off) \
1567 ((pte_t) { ((((__off) & 0x7f) << 1) + (((__off) >> 7) << 12)) \
1568 | _PAGE_INVALID | _PAGE_PROTECT })
1569
1570 #endif /* !__ASSEMBLY__ */
1571
1572 #define kern_addr_valid(addr) (1)
1573
1574 extern int vmem_add_mapping(unsigned long start, unsigned long size);
1575 extern int vmem_remove_mapping(unsigned long start, unsigned long size);
1576 extern int s390_enable_sie(void);
1577
1578 /*
1579 * No page table caches to initialise
1580 */
1581 static inline void pgtable_cache_init(void) { }
1582 static inline void check_pgt_cache(void) { }
1583
1584 #include <asm-generic/pgtable.h>
1585
1586 #endif /* _S390_PAGE_H */
Linux kernel - Deliverables
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